A Power Factor Correction with Voltage Doubler Rectifier 1LYamamoto, K-Matsui (Chubu University, Dep. Electrical Eng, ‘Kasugai 487-8501, Japan E-Mai:keiju@isc.chubu.ac.jp Abstract. For small capacity rectifier circuits with @ small capacity, such as those for consumer electronics and appliances, capacitor input type rectifier circuits are generally used. Consequently, various harmonics generated within the power system become a serious problem. Various studies of this ‘effect have been presented previously so far. However, most of these employ switching devices, such as FETs and the like, The absence of switching devices makes systems more tolerant to over-load, and brings low radio noise benefits. We propose a power factor correction scheme using a voltage doubler rectifier without switching devices. In this method, the input current is divided into two periods, where one period charge the small input capacitor and the other charge the large output capacitor. By dividing the input current into two different modes, the current ‘conduction period can be widened and harmonics can largely be canceled between the two modes. Hence, the harmonic characteristics can be significantly improved, whereby the lower order harmonics, such as the fifth ‘and seventh orders, are much reduced. The results are confirmed by theoretical and experimental implementations. 1, Introduetion For personal computers and television sets, single-phase rectifier circuits are used, which generally have an input capacitor filter, are used. It is well known that such rectifier circuits generate various harmonics in the power system, Hence, within a large number of applications incorporating such rectifiers, harmonics in the power system will be increased. In addition, various nonlinear semiconductor circuits are ‘used in industrial applications, leading to a further Iharmonic increase in the power system. Under such 0-7803-6456-2/00/$10.00 ©2000 IEEE Ueda ‘Chubu Electric Power Co.,Inc. Ootaka, Midoriku, Nagoya, 459-8522, Japan circumstances, various power factor correction circuits for single-phase rectifiers have been proposed and studied{I-4], These methods attempt to improve the ‘input current to a sinusoidal waveform by using switching devices and therefore degrade the cost performance. From this point of view, it is also important to discuss harmonic reduction methods that ‘operate without switching devices. In this method, using a voltage doubler rectifier, the input current is divided into two periods, where one period charges the small input capacitor and the other charges the large output capacitor through a filter inductor. By so dividing the input curent into two different modes, the current conduction period can be widened and harmonics can be largely canceled between the two modes. In this paper, we will discuss a novel power factor correction scheme that operate without switching devices. xe = a, Fig.l. Fundamental voltage doubler rectifier. 2. Principle of Operation ‘A. Voltage Doubler Rectifier with Reduced Inpat Capacitors In the conventional voltage doubler rectifier in Fig.l, let us consider how to achieve harmonic reduction in the input current waveform by means of cading the phase angle of the input current. To 264110 gia $1.00 270F uF Yaar “0.38mi ” 109 1000 ‘Capectanca iL F) Fig2 Reltiontio between pu capacance and toro fectr ofp arene accomplish this idea, the input capacitance C\(-C:)is selected to be small, so that the conduction commencement angle of the input current is advanced, For the output capacitor, which must smooth the load voltage, the capacitance C; is designed to be large. The fundamental principle of reducing the harmonics by using a small input capacitance had been already presented, using the conventional voltage doubler rectifier method[S]. Moreover, another improved technique was presented incorporating a voltage doubler rectifier with additional capacitors by Fujiwara, et all6]. According to reference[S,6], a fundamental characteristic ofthe circuit shown in Fig.| is presented. AAs the input capacitance C\(=C;)gradually decreases, the distortion factor D is also decreasing as shown in Fig.2. However, when C; is reduced beyond about 100 HF, the distortion factor is increasing again. This hhappens due to reduction of C), when the role of the inverse-paralleled diodes with C, or C: becomes dominant, so the charging current to output capacitor ; becomes large and the distortion factor is also increased. It varies according to the output power range, but an optimum value would be in the ‘neighborhood of about 100.4 F in the case shown in Fig2. 1B. Principle of Two Input Current Modes Power factor correction with two input current modes had been presented by Takahashi, et al{7], ‘where an LC resonant circuit is parallel-connected in a de link circuit to widen the input current conduction period. In our method, the input current can be also devided into two current modes, that is, one charging the input capacitor C, and the other charging the output capacitor C;. From this point of view, the proposed circuit operation might be considered to follow the principle of the two input current modes in [7]. In ‘order to describe exactly the reasoning behind our proposed method, we will discribe in detail how the ‘dea came about. In the circuit already reported in [8], shown in Fig.3, ‘two circuits are connected in parallel to reduce the hharmonics, that is, one including a small capacitor C, and the other including an additional inductor L. It ‘was found that the total harmonics in the power system are significantly reduced by interactions of each harmonic between the two circuits. Thus, by reducing the capacitance C; , the input current phase leads, as shown by ic in Fig.3(b). By adding an inductor L:, the ‘input current phase lags, as shown by i, Consequently, the phases of the harmonics in both circuits are efficiently shifted from each other, and we can obtain an improved waveform as shown by is, with lower ‘harmonics. The purpose of the work in this paper is to realize the same function by means of a single circuit. @ © Fig.3. A harmonic reduction by parallel connection, (@)eireuit and (bywaveforms C. Proposal for a Novel Power Factor Correction Rectifier Fig shows a novel power factor correction rectifier. In order to fulfil the functions mentioned previously, the capacitor C\(-C:) is designed to be small. The ‘capacitor C; is specified to be large to smooth the output voltage. Firstly, in the same way as in Fig.3, the small capacitor C; is charged by ic. When the sum of the capacitor voltages v., and v.: becomes larger than the output voltage v.s, the output current i, starts to flow. Fig.5 shows various waveforms of this operation.Fig4. Proposed single phase rectifier ‘While the supply voltage e, is falling from the peak value, a current i, continues to flow, whose phase lags due tothe reactor L> in series with e,. Hence, since ‘the phase of the harmonics of ic leads and that of i. lags, both harmonics negate each other between the two current waveforms. At the end of the period, the capacitor on the opposite side (C:) is discharged, and ‘gets ready for the next operation. During this operation, since the line inductance of the power system and the output inductance L; are connected in series, the phase delay of i is more effective, 3. Cirenit Analysis ‘As mentioned above, it can be seen thatthe phase of harmonics of ic lead due to the small C\(=C:), and that of i lags, due to L>. In this chapter, we resolve the optimum circuit constants for which the harmonics effectively negate each other between the two currents, such that the distortion factor of the input current becomes a minimum. ‘A. Circuit Differential Equations In Fig, the circuit differential equations can be expressed as follows, where all devices are ideal and circuit resistances are represented by R, for the input and R, for the output, and ici, ico and ics are the discharging currents of each capacitor. ent eRitre at isin tis eat Ss Rus—ve: a ics is, ivsbtis (is<0) ‘where, due to the function of the diodes, i:=0 for 1:0 , vei=0 for vei<0 and veo=0 for ve> <0. sessceeeeee(l) B. Circuit Operations () Period 1(0¥cs, this period ends. (2) Period I(t) is completely discharged, this 2643