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Nguyn Vn Hng

hung.rocket42@gmail.com

HVKTQS

1. Module A/D Trong Pic18 c b chuyn i A/D 8bit, 10bit ty tng h VK. Di y R gii thiu v ADC 10bit, i vi ADC 8bit mi th gn nh l tng t. Module A/D ca Pic cng ging nh vi cc chip ADC thng thng. V th ai bit qua v ADC th qu trnh tm hiu A/D module trong Pic tht s l n gin. Let go! y R ko trnh by chi tit v phn cng: cc thanh ghi, cc bit bit chi tit v chng cc bn c th xem trong datasheet ca loi VK m bn dng. Cc thanh ghi s dng cho module A/D: Thanh Thanh Thanh Thanh ghi ghi ghi ghi ADRESH: thanh ghi 8bit cao lu k t qu A/D ADRESL: thanh ghi 8bit thp lu kt qu A/D ADCON0: thanh ghi iu khin A/D ADCON1: thanh ghi iu khin A/D

Ta c th la chn in p tham chiu l Vref+/Vref- hoc Vdd/Vss. Nh hnh di chng ta c th thy n c la chn bng cp bit VCFG1:VCFG0 (xem chi tit trong datasheet ca thit b)

Nguyn Vn Hng

hung.rocket42@gmail.com

HVKTQS

Cc bc lp trnh cho ADC: 1. 2. Cu hnh module A/D Cu hnh chn analog, in p tham chiu, v I/O s Chn knh u vo A/D Chn clock cho chuyn i A/D Bt module A/D Cu hnh ngt A/D (nu cn) Clear bit c ngt ADIF (bit c ngt A/D) Set bit cho php ngt ADIE (bit cho php ngt A/D) Set bit cho php ngt ton cc: GIE (bit cho php ngt ton cc)
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Nguyn Vn Hng

hung.rocket42@gmail.com

HVKTQS

3. Cho thi gian acquision yu cu (khi nim ny s trnh by bn di) 4. Bt u chuyn i - Set bit GO/DONE (ADCON0) 5. Ch cho qu trnh chuyn i hon thnh - Hi vng bit GO/DONE hoc bit c ngt ADIF - Ch cho ngt A/D (nu s dng ngt) 6. c kt qu A/D trong thanh ghi ADRESH:ADRESL ; clear bit ADIF nu cn thit 7. Qu trnh chuyn i tip theo (cn thit ci t li A/D th lp li bc 1 hoc 2) Tip theo ta xem thi gian acquision l ci g? Thi gian Acquision Hnh di l m hnh u vo analog ca Pic:

Nhn vo m hnh u vo analog trn ta c th thy ngay rng ly c tn hiu u vo chnh xc th t C H O LD cn thit phi c thi gian np in p n t c gi tr ng bng gi tr u vo.
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Nguyn Vn Hng

hung.rocket42@gmail.com

HVKTQS

chnh l thi gian Acquision. Vy c d liu u vo chnh xc th nht thit rng phi tri qua thi gian ny th qu trnh chuyn i mi bt u nu ko t cha np ng gi tr th ta s chuyn i gi tr sai. chnh l l do phi ch qua thi gian ny th qu trnh chuyn i A/D mi bt u Tnh ton thi gian Acquision:

Thi gian settling Amplifier + thi gian np ca t Holding + h s nhit

V d tnh ton thi gian TACQ yu cu nh nht. Tnh ton da trn cc gi tr:

V d tnh ton thi gian TACQ yu cu nh nht:

- Tr khng ln nht ca ngun analog l 10k - Sau khi convert hon thnh cn thi gian delay 2.0T A D trc khi Acquision bt u li. Trong thi gian ny t holding khng kt ni vi knh u vo A/D
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Nguyn Vn Hng

hung.rocket42@gmail.com

HVKTQS

Sau qu trnh Acquision s l qu trnh conversion A/D. Vy ti y ta c th thy tng thi gian cho ly 1 mu A/D l: thi gian Acquision + thi gian conversion
Qu trnh conversion
Thi gian ly mu
Thi gian Acquision Thi gian A/D conversion

Conversion A/D hon thnh Kt qu c load vo thanh ghi ADRES. Bit ADIF c set Qu trnh conversion bt u. bng set bit GO T holding bt u np. Sau khi conver A/D hoc khi knh mi A/D c chn

Thi gian conversion mt 12 T A D t khi ta bt u set bit GO (hnh di):

Bt u conversion T hodling c ngt vi u vo analog (thng l 100ns) Set bit GO ADRES c load. Bit GO c clear. Bit ADIF c set. T holding c ni vi u vo analog

Chn clock conversion A/D T A D Ngun clock A/D c th c chn bng phn mm. C 4 la chn: 2 TOSC 8 TOSC
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Nguyn Vn Hng

hung.rocket42@gmail.com

HVKTQS

32 T O S C B to dao ng RC bn trong V d: nu ta chn 2T O S C th T A D =2 T O S C Gi s tn s thit b ta chn l f=20MHz T A D =2 T O S C =2*1/20=0.1 s = 100 ns Ta c bng tnh ton T A D tng ng vi 1 s tn s thit b v la chn T AD :

Ch : T A D = RC thng thng chn bng 4 s Tm li cng vic chnh ca chuyn i A/D 1 tn hiu l la chn tn s ly mu sao cho sau khi khi phc tn hiu c nh c da trn nh lut ly mu Kachenhikov. V th tn s ly mu 1/T A D phi c la chn ph hp da trn tn hiu cn chuyn i A/D chnh l cng vic la chn cu hnh v tn s thit b V d ta mun chuyn i tn hiu c tn s f=500Hz (T=2ms). Theo nh l ly mu th thi gian ly mu T 0 <=4ms Gi s vi T A C Q = 20 s f A C Q = 1/20 s = 0.05 MHz Tng thi gian ly mu T 0 = 12 T A D + T A C Q T A D <= (T 0 - T A C Q )/12=(4000-20)/12=331 s Nu ta cu hnh T A D = 32 T O S C th T O S C < 10 s f O S C > 0.1 MHz vy tn s thch anh nh nht ta c th dng l 0.1 Mhz, nu ta dng thch anh c tn s cng ln th thi gian ly mu s nh xung v ta s ly c nhiu mu hn trong 1 chu k tn hiu. V nh vy qu trnh khi phc tn hiu s c tn hiu cng ging vi tn hiu gc. Nhng i li
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Nguyn Vn Hng

hung.rocket42@gmail.com

HVKTQS

ta li phi tn nhiu ti nguyn hn trong qu trnh lu tr cc mu d liu Hot ng khi SLEEP Module A/D c th hot ng trong ch SLEEP bng cch chn ngun clock RC Khi clock RC c chn, module A/D ch 1 chu k lnh trc khi bt u conversion, thi gian ny cho php lnh SLEEP thc thi Khi qu trnh chuyn i hon thnh bit GO/DONE c clear v kt qu c lu vo trong thanh ghi ADRES. Nu ngt A/D cho php th thit b s c wake-up t Sleep. Nu ngt ko cho php th module A/D s turn-off bt chp khi ny bit ADON ang set Khi clock A/D ko phi l RC, lnh SLEEP s ngt qu trnh conversion ang thc thi v turn-off module A/D Turn-off A/D s lm cho module A/D tiu tn dng thp nht nh hng ca RESET Khi RESET, n s tt module A/D v qu trnh conversion ang thc hin cng b ngt gia chng Gi tr thanh ghi ADRESH:ADRESL ko c sa bi reset POWER-ON v thanh ghi ny s cha d liu ko bit sau khi reset POWER-ON 2. Lp trnh A/D bng MPLAB C18 V d: /******************************************************* *************** * * FileName: * Processor: ADC.C Pic18xxx
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Nguyn Vn Hng

hung.rocket42@gmail.com

HVKTQS

* Compiler:

C18 v3.40 or higher

*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~ * Author Date

*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~ * Nguyen Van Hung 25/10/2011

* Lop: Thiet Ke He Thong Dieu Khien Ten Lua K42 - HVKTQS *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~ *CHUONG TRINH CONVERSION A/D ******************************************************** **************/ #define USE_OR_MASKS #include <p18cxxx.h> #include "adc.h"

unsigned int ADCResult=0; float voltage=0;

void main(void) {

Nguyn Vn Hng

hung.rocket42@gmail.com

HVKTQS

unsigned char channel=0x00,config1=0x00,config2=0x00,config3=0x00,portconfig=0 x00,i=0;

//-- clear adc interrupt and turn-off adc --CloseADC();

//--khoi tao adc--/**** cau hinh ADC: * clock cho chuyen doi A/D = FOSC/2 * Aquisition time =2 TAD * chon kenh 1 cho lay mau * bat ngat ADC * chon dien ap tham chieu VDD & VSS */ config1 = ADC_FOSC_2 | ADC_RIGHT_JUST | ADC_2_TAD ; config2 = ADC_CH0 | ADC_INT_ON | ADC_REF_VDD_VSS ; portconfig = ADC_15ANA ; OpenADC(config1,config2,portconfig);

//---khoi tao ngat ADC va cho phep ngat--9

Nguyn Vn Hng

hung.rocket42@gmail.com

HVKTQS

ADC_INT_ENABLE();

//---sample and convert---for(i=0;i<16;i++) { ConvertADC(); while(BusyADC()); ADCResult += (unsigned int) ReadADC(); } ADCResult /= 16; voltage = (ADCResult*5.0)/1024; // chuyen ra dien ap

CloseADC();

//tat ADC

while(1); }

//ket thuc chuong trinh

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