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  • DFF

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    api-26691029
    72 tayangan4 halaman
    This document describes a D flip-flop (DFF) circuit implemented on an FPGA. The DFF takes in a data input D, a clock input CLK, and a reset input RST. It outputs the stored value Q and its inverse QBAR. The DFF uses a synchronous process sensitive to the clock and reset to load the D input on the rising edge of CLK, unless RST is asserted, in which case it loads a 0. Timing analysis shows the circuit meets timing constraints with less than 1% FPGA resource utilization.

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    Judul Asli

    Dff

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    This document describes a D flip-flop (DFF) circuit implemented on an FPGA. The DFF takes in a data input D, a clock input CLK, and a reset input RST. It outputs the stored value Q and its inverse QBAR. The DFF uses a synchronous process sensitive to the clock and reset to load the D input on the rising edge of CLK, unless RST is asserted, in which case it loads a 0. Timing analysis shows the circuit meets timing constraints with less than 1% FPGA resource utilization.

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    Attribution Non-Commercial (BY-NC)
    Unduh sebagai DOC, PDF, TXT atau baca online dari Scribd
    Tandai sebagai konten tidak pantas
    72 tayangan4 halaman

    DFF

    Diunggah oleh

    api-26691029
    This document describes a D flip-flop (DFF) circuit implemented on an FPGA. The DFF takes in a data input D, a clock input CLK, and a reset input RST. It outputs the stored value Q and its inverse QBAR. The DFF uses a synchronous process sensitive to the clock and reset to load the D input on the rising edge of CLK, unless RST is asserted, in which case it loads a 0. Timing analysis shows the circuit meets timing constraints with less than 1% FPGA resource utilization.

    Hak Cipta:

    Attribution Non-Commercial (BY-NC)
    Unduh sebagai DOC, PDF, TXT atau baca online dari Scribd
    Tandai sebagai konten tidak pantas
    dari 4

     D Flip Flop

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity Dff is
    Port ( d : in std_logic;
    clk : in std_logic;
    rst: in std_logic;
    q : inout std_logic;
    qbar : out std_logic);
    end Dff;

    architecture Behavioral of Dff is

    begin
    process(rst,clk)
    begin

    if (rst='1') then
    q <='0';
    else if(clk='1' and clk'event) then
    q<= d;
    end if;
    qbar<= not q;
    end if;

    end process;
    end Behavioral;

    Device utilization summary:-


    Selected Device : xqvr300cb228-4

    Number of Slices: 2 out of 3072 0%


    Number of Slice Flip Flops: 3 out of 6144 0%
    Number of 4 input LUTs: 1 out of 6144 0%
    Number of bonded IOBs: 3 out of 166 1%
    Number of GCLKs: 2 out of 4 50%
    TIMING REPORT:-

    Clock Information:

    -----------------------------------+------------------------+-------+
    Clock Signal | Clock buffer(FF name) | Load |
    -----------------------------------+------------------------+-------+
    clk | BUFGP |2 |
    rst | BUFGP |1 |
    -----------------------------------+------------------------+-------+

    Timing Summary:-
    Speed Grade: -4

    Minimum period: No path found


    Minimum input arrival time before clock: 3.228ns
    Maximum output required time after clock: 8.426ns
    Maximum combinational path delay: No path found

    Timing Detail:-

    All values displayed in nanoseconds (ns)

    Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'


    Offset: 3.228ns (Levels of Logic = 1)
    Source: d (PAD)
    Destination: q (FF)
    Destination Clock: clk rising

    Data Path: d to q
    Gate Net
    Cell:in->out fanout Delay Delay Logical Name (Net Name)
    ---------------------------------------- ------------
    IBUF:I->O 2 0.989 1.474 d_IBUF (d_IBUF)
    FDC:D 0.765 q
    Total 3.228ns (1.754ns logic, 1.474ns route)
    (54.3% logic, 45.7% route)

    Timing constraint:- Default OFFSET OUT AFTER for Clock 'clk'


    Offset: 8.289ns (Levels of Logic = 1)
    Source: q_1 (FF)
    Destination: q (PAD)
    Source Clock: clk rising

    Data Path: q_1 to q


    Gate Net
    Cell:in->out fanout Delay Delay Logical Name (Net Name)
    ---------------------------------------------------------------------------------
    FDC:C->Q 1 1.372 1.265 q_1 (q_1)
    OBUF:I->O 5.652 q_OBUF (q)
    ---------------------------------------------------------------------------------
    Total 8.289ns (7.024ns logic, 1.265ns route)
    (84.7% logic, 15.3% route)

    -----------------------------------------------------------------------------------
    Timing constraint: Default OFFSET OUT AFTER for Clock 'rst'
    Offset: 8.426ns (Levels of Logic = 1)
    Source: qbar (LATCH)
    Destination: qbar (PAD)
    Source Clock: rst rising

    Data Path: qbar to qbar


    Gate Net
    Cell:in->out fanout Delay Delay Logical Name (Net Name)
    --------------------------------------------------------------------------------
    LD_1:G->Q 1 1.509 1.265 qbar (qbar_OBUF)
    OBUF:I->O 5.652 qbar_OBUF (qbar)
    -------------------------------------------------------------------------------
    Total 8.426ns (7.161ns logic, 1.265ns route)
    (85.0% logic, 15.0% route)

    CPU : 10.92 / 12.88 s | Elapsed : 10.00 / 12.00 s

    Total memory usage is 60440 kilobytes.


    RTL Schematics:-

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