Verilog For Finite state machines

Outline O tli
Three Verilog code styles for FSMs Verilog codes for Moore and Mealy Two examples
Sequence detector Control circuit for swapping

Design process by problem 8.9

Specifications State diagram Code simulation

Verilog template for Moore FSMs

module FSM_name (Clock, Resetn, input_signal, output_signal); input Clock, Resetn, input_signal; output output_signal; reg [n:1] state_present, STATE_NEXT; g[ ] _p _ parameter [n:1] STATE1 = 2'b00, STATE2 = 2'b01. ; // Define the next state combinational circuit always @(input_signal or state_present) case (state present) (state_present) STATE1: if (input_signal) STATE_NEXT = ; else STATE_NEXT = ; STATE2: if (input_signal) STATE_NEXT = ; else STATE_NEXT = ; default: STATE_NEXT = n'bxx; endcase // Define the sequential block always @(negedge Resetn or posedge Clock) if (Resetn == 0)y <= STATE1; elsey <= Y; // Define output D fi t t assign output_signal = .; endmodule

3 parallel blocks: 1) always block: combinational circuit for next state 2) always block: update states 3) assign: i combinational circuit for output y Flip-flops

w clock

Next state circuit

Output z circuit

resetn

Example: sequence detector

module simple (Clock Resetn w, z); (Clock, Resetn, w input Clock, Resetn, w; output z; reg [2:1] y, Y; parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10; // Define the next state combinational circuit always @(w or y) case (y) A: if (w) Y = B; else Y = A; B: if (w) Y = C; else Y = A; C: if (w) Y = C; else Y = A; default: Y = 2'bxx; endcase // Define the sequential block e e t e seque t a b oc always @(negedge Resetn or posedge Clock) if (Resetn == 0)y <= A; elsey <= Y; // Define output D fi t t assign z = (y == C); endmodule

y: present state t t t Y: next state State assignment

w clock

Next state circuit

Y Flip-flops

Output z circuit

resetn

Second Verilog template

module FSM_name (Clock, Resetn, input_signal, output_signal); input Clock, Resetn, input_signal; output output_signal; reg [n:1] state_present, STATE_NEXT; g[ ] _p _ parameter [n:1] STATE1 = 2'b00, STATE2 = 2'b01. ; // Define the next state combinational circuit always @(input_signal or state_present) begin case (state_present) STATE1: if (input_signal) STATE_NEXT = ; else STATE_NEXT = ; STATE2: if (input_signal) STATE_NEXT = ; else STATE_NEXT = ; default: STATE_NEXT = n'bxx; endcase // Define output output_signal=.; end // Define the sequential block always @( l @(negedge R t or posedge Cl k) d Resetn d Clock) if (Resetn == 0)y <= STATE1; elsey <= Y; endmodule

2 parallel blocks: 1) always block: combinational circuit for next state output 2) always block: update states d t t t merge Y Flip-flops y

w clock

Next state circuit

Output z circuit

resetn

Example: sequence detector

module simple (Clock Resetn w, z); (Clock, Resetn, w input Clock, Resetn, w; output z; reg z; reg [2:1] y, Y; parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10; // Define the next state combinational circuit always @(w or y) begin case (y) A: if (w) Y = B; else Y = A; B: if (w) Y = C; else Y = A; C: if (w) Y = C; else Y = A; default: Y = 2'bxx; e dcase endcase // Define output z = (y == C); end // Define the sequential block always @( l @(negedge R t or posedge Cl k) d Resetn d Clock) if (Resetn == 0)y <= A; elsey <= Y; endmodule

y: present state t t t Y: next state State assignment

w clock

Next state circuit

Y Flip-flops

Output z circuit

resetn

Third Verilog template

module FSM_name (Clock, Resetn, input_signal, output_signal); input Clock, Resetn, input_signal; output output_signal; reg [n:1] state; // dont need state_present, STATE_NEXT; g[ ] _p _ parameter [n:1] STATE1 = 2'b00, STATE2 = 2'b01. ; // Define the sequential block always @(negedge Resetn or posedge Clock) if (Resetn == 0) state <= STATE1; else case (state) STATE1: if (input_signal) state < = ; else state < = ; STATE2: if (input_signal) state <= ; else state < = ; default: state <= n'bxx; n bxx; endcase // Define output assign output_signal=.;

2 parallel blocks: 1) always block: sequential circuit for next state and update 2) assign bl k i block: for output assign cannot be put inside the always block merge

w clock

Next state circuit

Y Flip-flops

Output z circuit

resetn

endmodule

Example: sequence detector

module simple (Clock, Resetn, w, z); input Clock, Resetn, w; output z; reg [2:1] y; parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10; // Define the sequential block always @(negedge Resetn or posedge Clock) if (Resetn == 0) y <= A; else case (y) A: if (w) y <= B; else y <= A; B: if (w) y <= C; else y <= A; C: if (w) y <= C; else y <= A; default: y <= 2'bxx; endcase // Define output assign z = (y == C); endmodule

Summary of Verilog for FSMs S f V il f FSM

No standard way for writing code that represents an FSM. However, However there are 3 templates we can use to code, based on state diagram. The 3 templates provide identical functionality, but may produce different circuits. The first two templates are recommended. Similar templates exist for Mealy FSMs

Example: control of swapping

module control (Clock, Resetn, w, R1in, R1out, d l t l (Cl k R t R1i R1 t R2in, R2out, R3in, R3out,Done); input Clock, Resetn, w; output R1in, R1out, R2in, R2out, R3in, R3 t D R3i R3out, Done; reg [2:1] y, Y; parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11; // Define the next state combinational circuit always @(w or y) case (y) A: if (w) Y = B; else Y = A; B: Y = C; C: Y = D; D: Y = A; endcase // Define the sequential block always @(negedge Resetn or posedge Clock) if (Resetn == 0) y <= A; else y <= Y;

// Define outputs assign R2out = (y == B); assign R3in = (y == B); assign R1out = (y == C); assign R2in = (y == C); assign R3out = (y == D); assign R1in = (y == D); assign Done = (y == D); endmodule

Verilog for Mealy FSMs V il f M l FSM

Similar to Moore FSMs The main difference between Mealy and Moore:
For Moore, the output is defined independent of inputs, so the code for output is separated from the code for state transitions, e.g. case For Mealy, the code for output is written within the case statement that also defines the state transitions.

Two parallel blocks:

always @ (inputs or current states) defines the next state current_states) and output. alwasy @ (negedge resetn or posedge clock) defines flipflops. flops

Example: Verilog for Mealy

module mealy (Clock, Resetn, w, z); (Clock Resetn w input Clock, Resetn, w; output z; reg y, Y, z; parameter A = 0, B = 1; // Define the next state and output //combinational circuits always @(w or y) case (y) A: if (w) begin z = 0; Y = B; end else begin z = 0; Y = A; end B: if (w) beg begin z = 1; Y = B; end else begin z=0 Y=A 0; A; end endcase // Define the sequential block always @(negedge Resetn or posedge Clock) y @( g g p g ) if (Resetn == 0) y <= A; else y <= Y; endmodule

Reset w = 1z= 0 A w = 0z= 0 w = 0z= 0 B w = 1z= 1

Verilog template for Mealy FSMs

module FSM_name (Clock, Resetn, input_signal, output_signal); input Clock, Resetn, input_signal; output output_signal; reg [ 1] state_present, S A [n:1] STATE_NEXT; parameter [n:1] STATE1 = 2'b00, STATE2 = 2'b01. ; // Define the next state combinational circuit and outputs always @(input_signal or state_p y @( p g present) ) case (state_present) STATE1: if (input_signal) define output and next state; else define output and next state; STATE2: if (input_signal) define output and next state; else define o tp t and ne t state; output next default: define output and next state; endcase // Define the sequential block always @(negedge Resetn or posedge Clock) if (Resetn == 0)y <= STATE1; elsey <= Y;

2 parallel blocks: 1) always block: combinational circuit for next state and output 2) always block: update states

w clock

Next state circuit

Y Flip-flops

Output z circuit

endmodule

resetn

Design example: D i l
a sequential circuit has two inputs, w1 and w2, and an output, z. q p , , p , Its function is to compare the input sequences on the two inputs. If w1 =w2 during any four consecutive clock cycles, the circuit produces z=1; otherwise, z=0. For example w1: 0 1 1 0 1 1 1 0 0 0 1 1 0 w2: 1 1 1 0 1 0 1 0 0 0 1 1 1 z: 0 0 0 0 1 0 0 0 0 1 1 1 0

state di t t diagram
w = w1 w2
Mealy FSM W=1 A W 0 W=0 W=1 B W=0 W=1 W=1 D W=0 / z=1 C W=0 3 equal 4 equal 2 equal 1 equal resetn W1 != w2

: Verilog code
module prob8_9 (Clock, Resetn, w1, w2, z); input Clock, Resetn, w1, w2; output z; reg z; reg [2 1] y, Y [2:1] Y; wire w; parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11; // Define the next state and output combinational circuits assign w = w1 ^ w2; g ; always @(w or y) case (y) A: if (w) begin Y = A; z = 0; else begin Y = B; z = 0; B: if (w) begin Y = A; z = 0; else begin Y = C; z = 0; C: if (w) begin Y = A; z = 0; else begin Y = D; z = 0; D: if (w) begin Y = A; z = 0; else begin Y = D; z = 1; endcase // Define the sequential block always @(negedge Resetn or posedge Clock) if (Resetn == 0) y <= A; else y <= Y; endmodule

end end end end end end end end

simulation i l ti
Specify input signals w1 and w2:
Assume that w1 and w2 may change their values only after the positive edges of clock with a small delay. This assumption is reasonable because w1 and w2 most likely come from a circuit with the same clock. Otherwise, Otherwise the simulation result may be not what you expected.

simulation i l ti

simulation problem i l ti bl
If inputs are not specified appropriately.

W1, w2, clock change at the same time confused