HLNAND: A New Standard for High Performance Flash Memory

Peter Gillingham MOSAID Technologies Inc. gillingham@mosaid.com

Santa Clara, CA USA August 2008

Objectives
Address performance and density requirements of Solid State Drive (SSD) Cost effectively serve lower end applications
4 Key Flash Applications
SSD for HDD Replacement Flash Memory Card
1000

Sustainable Bandwidth (MB/s)

100 SSD High-end Flash Card for Prosumer 10 Generic Flash Memory Card & USB Driver Compressed Digital Video

USB Flash Drive

Embedded Apps

HD Digital Video

MP3 1 4GB 8GB 16GB 32GB Density Santa Clara, CA USA August 2008 64GB 128GB 256GB

NAND Flash Standards

Defacto standard for asynchronous NAND Flash established by Toshiba in the early 1990s ONFI 1.0 formal standard for asynchronous NAND Flash to resolve incompatibilities among suppliers ONFI 2.0 evolutionary standard adding source synchronous DDR to 133MB/s HyperLink NAND (HLNAND) synchronous DDR ring topology introduced by MOSAID RamLink IEEE standard published in 1996 for DRAM main memory using ring topology
Santa Clara, CA USA August 2008

Memory Interface Comparison

DRAM Address/ Command Data Address/ Command/ Data Address/ Command/ Data In Address/ Command/ Data Out NAND HLNAND

DRAM code storage low latency operation issue commands during data transfers multi-drop bus limited number of loads

Conventional NAND Flash high latency core long data transfers interrupt data transfer to issue commands multi-drop bus limited number of loads

HLNAND Flash high latency core long data transfers interrupt data transfer to issue commands point-to-point daisy chain unlimited number of loads

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Conventional NAND Flash Interface

8 bit, bidirectional, multi-drop bus Asynchronous LVTTL signaling up to 40Mb/s/pin Speed degradation with more than 4 devices on bus

Chip Enable (CE) signal required for each device

Power hungry 3.3V I/O CE2 CE3

CE1 Host Controller NAND

Santa Clara, CA USA August 2008

NAND

NAND

HLNAND Flash Interface

Unidirectional, point-to-point, daisy-chain cascade supporting as many as 255 devices in a ring No bandwidth degradation with additional devices Device address assigned on initialization High speed DDR signaling up to 800Mb/s/pin Dynamic link width programmable from 1 to 8 bits Low Power 1.8V I/O HLNAND Host Interface Controller HLNAND HLNAND HLNAND

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HyperLink Packet Truncation

Once packet reaches addressed device the write data payload is truncated Simultaneous data transfer possible if write device is upstream of read device
write 0 HLNAND 0 HLNAND 1

Controller
HLNAND 3 read 2
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HLNAND 2
read 2
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HyperLink Advantages
Bandwidth
Point-to-point signaling extends to much higher data-rates than multi-drop bus

Power
No termination resistors required Point-to-point I/O drivers are much smaller than multi-drop bus drivers and have significantly lower capacitance Packet truncation at destination device reduces power

Scalability
Up to 255 devices in a single ring
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HL1 Interface
DDR signaling up to 266MB/s, no PLL required No changes to existing Flash process
CSO DSO Q[7:0]
CSI DSI D[7:0] CSO DSO Q[7:0] CSI DSI D[7:0] CSO DSO Q[7:0] CSI DSI D[7:0] CSO DSO Q[7:0] CSI DSI D[7:0] CSO DSO Q[7:0]

RST# CE# CK CK#

RST# CE# CK CK#

RST# CE# CK CK#

RST# CE# CK CK#

Controller
CK# CK CE# RST#

RST# CE# CK CK#

RST# CE# CK CK#

RST# CE# CK CK#

RST# CE# CK CK#

D[7:0] CSI DSI

Q[7:0]
CSO DSO

D[7:0] CSI DSI

Q[7:0]
CSO DSO

D[7:0] CSI DSI

Q[7:0] CSO DSO

D[7:0] CSI DSI

Q[7:0] CSO DSO

D[7:0] CSI DSI

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HL1 Timing
CSI/CSO Command and write data Strobe Input/Output DSI/DSO read Data Strobe Input/Output Data bursts can be interrupted by terminating CSI/DSI
tCK
tCKL

CK CK#
tT tCKH

CSI or DSI
tIS tIH

D0..w-1
tIH tIS

CSO or DSO
tOA tOH

Q0..w-1
tOH

w = current li nk width

Santa Clara, CA USA August 2008

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HL2 Interface
Source synchronous DDR to 800MB/s with on-chip PLL May require improvement to I/O transistor performance Fully backward compatible to HL1
CKO CKO# CSO DSO Q[7:0]
CK CK# CSI DSI D[7:0] CKO CKO# CSO DSO Q[7:0] RST# CE# Vref CK CK# CSI DSI D[7:0] CKO CKO# CSO DSO Q[7:0] RST# CE# Vref CK CK# CSI DSI D[7:0] CKO CKO# CSO DSO Q[7:0] RST# CE# Vref CK CK# CSI DSI D[7:0] CKO CKO# CSO DSO Q[7:0]

RST# CE# Vref

Controller
Vref CE# RST#

RST# CE# Vtrf

RST# CE# Vtrf

RST# CE# Vtrf

RST# CE# Vtrf

D[7:0] CSI DSI CKI# CKI

Santa Clara, CA USA August 2008

Q[7:0] CSO DSO CKO# CKO

D[7:0] CSI DSI CK# CK

Q[7:0] CSO DSO CKO# CKO

Q[7:0] CSI DSI CK# CK

Q[7:0] CSO DSO CKO# CKO

D[7:0] CSI DSI CK# CK

Q[7:0] CSO DSO CKO# CKO

D[7:0] CSI DSI CK# CK

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HLNAND Instructions
Operation Page Read Page Read for Copy Burst Data Read Burst Data Load Start Burst Data Load Page Program Block Erase Address Input Page-pair Erase Address Input Erase Operation Abort Read Status Register Read Device Information Register Read Link Configuration Register Write Link Configuration Register
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1st Byte DA DA DA DA DA DA DA DA DA DA DA DA DA FF

2nd Byte 0Xh 1Xh 2Xh 4Xh 5Xh 6Xh 8Xh 9Xh AXh CXh Fyh F4h F7h FFh

3rd Byte RA RA CA CA CA RA RA RA

4th Byte RA RA CA CA CA RA RA RA

5th Byte RA RA

6th Byte

7th Byte

8th Byte

2116th Byte

DATA DATA DATA DATA DATA DATA DATA DATA RA RA RA

DATA DATA

DATA DATA
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DA = Device Address, CA = Column Address, RA = Row Address, X = Bank Number

HLNAND Resources
Available at hlnand.com
Architectural Specification Datasheets White papers Technical papers Verilog Behavioral model

Santa Clara, CA USA August 2008

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HLNAND Emulation System

DIMM module using DRAM and FPGA fully emulates 200MB/s HLNAND Flash device Available to controller and end product manufacturers for system development and benchmarking

Santa Clara, CA USA August 2008

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HLNAND Multi-Chip Package

First generation product using conventional NAND Small bridge chip provides HyperLink interface Significant power savings
Device0 Device1 Device2 Device3

4Gb (plane0)

4Gb (plane1)

4Gb (plane0)

4Gb (plane1)

4Gb (plane0)

4Gb (plane1)

4Gb (plane0)

4Gb (plane1)

4KB Page

4KB Page

4KB Page

4KB Page

4KB Page

4KB Page

4KB Page

4KB Page

X8 I/O

X8 I/O

X8 I/O

X8 I/O

4KB SRAM (Plane0)

4KB SRAM (Plane1)

4KB SRAM (Plane0)

4KB SRAM (Plane1)

4KB SRAM (Plane0)

4KB SRAM (Plane1)

4KB SRAM (Plane0)

4KB SRAM (Plane1)

Bank0

Bank1

Bank2

Bank3

HLNAND interface

Santa Clara, CA USA August 2008

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