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A

Compal Confidential
2

PAWGC/D Schematics Document


AMD APU Ontario-FT1 + FCH Hudson-M1 + GPU Roberson XT

2010-11-10

REV:1.0

CIT RD Only

2010/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Cover Page
Size
B
Date:

Document Number

Rev
1.0

LA6755P/7P
Tuesday, November 30, 2010

Sheet
E

of

48

For PAWGC
1. POWER BOARD
2. Card Reader BOARD

Compal confidential
File Name : PAWGC/D

For PAWGD
1. POWER BOARD
2. Card reader BOARD
3. 4*LED+SW(3pin)
+SW(4pin) BOARD
4. ODD BOARD

LVDS Conn.

Memory BUS(DDRIII) 200pin DDRII-SO-DIMM X2

page 10

AMD Brazos APU


CRT Conn.
HDMI Conn.

page 8,9

BANK 0, 1, 2, 3

1.5V DDRIII 1333

FT1
BGA 413-Ball
19mm x 19mm

page 12

AMD Robson

Single Channel

page 11

page 5,6,7

VRAM 64*16
DDR3*4

x4 PCI-E GPP GEN2


x4 UMI Gen. 1
2.5GT/s per lane

page 18 ~ 24

2Channel Speaker

page 27

Internal MIC

Audio Codec

Hudson M1

AZALIA

page 27

BGA 605-Ball
23mm x 23mm

Audio Jacks
Stereo
HeadPhone Output
Microphone Input

14*USB2.0

4 * x1 PCI-E 2.0
WLAN &WiMax

page 13,14,15,16,17

page 30

GIGA LAN
AR8151/8152

page 27

CX20671

6*SATA serial

LPC BUS

CMOS Camera page 10


BlueTooth CONN page 34
USB PORT 2.0 x3(Left)

USB PORT 2.0 x1(Right)

page 34

page 35

page 25,26

SPI ROM

WLAN/WiMAX

EC

page 15

ENE KB930

Card Reader

page 31

PCI Express
Mini card Slot 1

USB(WiMAX)

Realtek RTS5139
SD/MMC/MS/MS Pro/XD

PCI-E(WLAN)

WLAN/WiMAX page 30

Int.KBD
page 32

Touch Pad

ESATA HDD AND USB CONN


(Left)
page 34

SPI ROM

page 32

page 33

SATA3.0 HDD CONN


page 29
Thermal Sensor
SATA ODD CONN
page 29

EMC1403 page 28

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/06/30

Issued Date

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Block Diagrams
Size
B
Date:

Document Number

Rev
1.0

LA6755P/7P
Tuesday, November 30, 2010

Sheet
E

of

48

Voltage Rails

Power Plane

Description

S1

VIN

Adapter power supply (19V)

N/A

B+

AC or battery power rail for power circuit.

N/A

S5

FCH Hudson-M1
USB Port List

N/A

N/A

USB1.1

N/A

N/A

S3

+APU_CORE

Core voltage for CPU (0.7-1.2V)

ON

OFF

OFF

+APU_CORE_NB

1.0V switched power rail

ON

OFF

OFF

+1.5V

1.5V power rail for CPU VDDIO and DDRIII

ON

ON

OFF

+0.75VS

0.75VS switched power rail for DDR terminator

ON

OFF

OFF

+1.0VS

1.0V switched power rail for NB VDDC & VGA

ON

OFF

OFF

+1.1VS

1.1VS switched power rail

ON

OFF

OFF

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+3V_LAN

3.3V power rail for LAN

ON ON(WOL)

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

OFF

+5VS

5V switched power rail

ON

OFF

OFF

+VSB

VSB always on power rail

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

+1.1VALW

1.1V always on power rail

ON

ON

ON*

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address

EC SM Bus2 address

Device

Address

HEX

Smart Battery

0001-011xb

15H

SM Bus Controller 0
Device

Address

HEX

EMC1412-2 (dGPU)

1111-100xb

F8H

EMC1403-2(DDR,WLAN)

1001-101xb

9AH

SB-TSI

1001-100xb

98H

Device

Port0

NC

Port1

NC

PCIE1
PCIE2

SATA0
GPU
PCIE x4

PCIE3

Device

HEX

1001-000xb

90

DDR DIMM2 (FCH_SMB0)

1001-001xb

92

eSATA

SATA3

NC

Left USB1

PCIE0

LAN

SATA4

NC

USB Camera

PCIE1

WLAN

SATA5

NC

Port2

Left(Combo)

PCIE2

NC

Port3

Left USB2

PCIE3

NC

Port4

Right USB

Port5

BT

Port6

CardReader

Port7

Mini-PCIE

Port8

NC

Port9

NC

Port10

NC

Port11

NC

Port12

NC

Port13

NC

BOM Structure
UMA@
PX@

: UMA only
: DIS muxluss
- PX3@ : PX3.0 only
- BACO@ : Baco only

GIGA@ : AR8151
8152@ : AR8152
CMOS@ : USB camera
HDMI@ : HDMI function
nonHDMI@ : w/o HDMI function
ESATA@: eSATA function
BT@
: BT function
ME@
: ME components
X76@, H1G@, H512@, S1G@, S512@ : VRAM
45@
: 45 Level
HWM@ : hardware monitor function
nonHWM@: w/o hardware monitor function

(FCH_SMB0)

Address

ODD

SATA2

Port1

HEX

DDR DIMM1 (FCH_SMB0)

SATA1

Port0

H_THERMTRIP# (FCH_ALERT#)

SM Bus Controller 1

HDD

USB2.0

APU SIC/SID (FCH_SMB3)

FCH Hudson-M1
SATA Port List

PCIE0

(FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)

Address

Brazos
PCIE Port List

APU

FCH

WLAN (FCH_SMB0)

2010/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Notes List
Size
B
Date:

Document Number

Rev
1.0

LA6755P/7P
Tuesday, November 30, 2010

Sheet
E

of

48

Power-Up/Down Sequence

BACO option :

2. VDDR3 should ramp-up before or simultaneously with VDDC.

PE_GPIO0 : High ->Normal operation (dGPU is not reset on BACO mode)


PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)

3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10.
4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and
VDD_CT have ramped up.
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
ramp-up (or vice versa).)

VDDR3(3.3VGS)

Note: Do not drive any IOs before VDDR3 is ramped up.

PCIE_VDDC(1.0V)
C

PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation


PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON

1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up
sequence, though a shorter ramp-up duration is preferred.

Without BACO option :

VDDR1(1.5VGS)

dGPU Power Pins

Voltage

PX 3.0

BACO Mode Max current

PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT,


DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
DPLL_PVDD, MPV18, and SPV18

1.8V

OFF

ON

1679mA

DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and


SPV10

1.0V

OFF

ON

575mA

PCIE_VDDC

1.0V

OFF

ON

2A

VDDR3 , and A2VDD

3.3V

OFF

ON

190mA

BIF_VDDC (current consumption = 55mA@1.0V, in


BACO mode)

Same as
VDDC

OFF

ON
Same as
PCIE_VDDC

70mA

VDDR1

1.5V

OFF

OFF

2.8A

VDDC/VDDCI

1.12V

OFF

OFF

12.9A

VDDC/VDDCI(1.12V)
VDD_CT(1.8V)

iGPU

PE_GPIO0

PE_EN

dGPU

PERSTb

BACO Switch

BIF_VDDC
PE_GPIO1

REFCLK

PX_mode

+3.3VALW

Straps Reset

+1.0V

Straps Valid

MOS

Regulator

+3.3VGS

1
+1.0VGS

+1.5V

+1.5VGS

SI4800

Regulator

Global ASIC Reset


+1.8V

SI4800

T4+16clock

+B

+1.8VGS

+VGA_CORE

PWRGOOD

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/06/30

Deciphered Date

2012/07/14

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

dGPU Block Diagram


Size
B
Date:

Document Number

Rev
1.0

LA6755P/7P
Tuesday, November 30, 2010

Sheet
1

of

48

B9
A9

TDP1_TXP1
TDP1_TXN1

(11) HDMI_TX0P
(11) HDMI_TX0N

C512 1
C513 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

HDMI_TX0P_C
HDMI_TX0N_C

D10
C10

TDP1_TXP2
TDP1_TXN2

(11) HDMI_CLKP
(11) HDMI_CLKN

C514 1
C515 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

HDMI_CLKP_C
HDMI_CLKN_C

A10
B10

TDP1_TXP3
TDP1_TXN3

(10) LVDS_A2
(10) LVDS_A2#

B5
A5

LTDP0_TXP0
LTDP0_TXN0

(10) LVDS_A1
(10) LVDS_A1#

D6
C6

LTDP0_TXP1
LTDP0_TXN1

+3VS

R811 1

2 10K_0402_5%

HDMI_DATA

R812 1

2 10K_0402_5%

HDMI_CLK

R410 1

2 1K_0402_5%

APU_PROCHOT#

R411 1

2 1K_0402_5%

APU_ALERT#_R

R412 1

2 1K_0402_5%

APU_SIC

R414 1

2 1K_0402_5%

APU_SID

(10) LVDS_A0
(10) LVDS_A0#

A6
B6

(10) LVDS_ACLK
(10) LVDS_ACLK#

D8
C8

APU_CLK
APU_CLK#

(13)
(13)

DISP_CLK
DISP_CLK#

D2
D1

APU_SVC
APU_SVD

J1
J2

SVC
SVD

P3
P4

SIC
SID

(44)
(44)

T3
T4

(13) LDT_RST#
(13) APU_PWRGD

R807 1

(31) EC_PROCHOT#

R808 1

2 0_0402_5% APU_PROCHOT#
2 0_0402_5%

LTDP0_TXP3
LTDP0_TXN3

(13)
(13)

APU_SIC
APU_SID

(13) FCH_PROCHOT#

LTDP0_TXP2
LTDP0_TXN2

V2
V1

(15) APU_ALERT#_FCH
(31) APU_ALERT#_EC

Connection to EC, FCH input

APU_PROCHOT#
U1
APU_THERMTRIP# U2
APU_ALERT#_R T2
R418 1
@
2 0_0402_5%
R873 1
2 0_0402_5%
APU_TDI
N2
APU_TDO
need to pull-down
N1
APU_TCK
P1
APU_TMS
P2
APU_TRST#
M4
T93PAD
APU_DBRDY
M3
T94PAD
Close to APU
APU_DBREQ#
M1

(44) APU_VDDNB_RUN_FB_H
(44) APU_VDD0_RUN_FB_H
T77PAD

F4
G1
F3
F1

(44) APU_VDD0_RUN_FB_L

B4
W11
V5
+3VS

DP MISC

2
2

VGA DAC

(11) HDMI_TX1P
(11) HDMI_TX1N

TDP1_TXP0
TDP1_TXN0

CLKIN_H
CLKIN_L
DISP_CLKIN_H
DISP_CLKIN_L

RESET_L
PWROK
PROCHOT_L
THERMTRIP_L
ALERT_L
TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L

TEST

APU_DBREQ#
APU_SVC
APU_SVD
LDT_RST#
APU_PWRGD
TEST_25_L
TEST36

HDMI_TX1P_C
HDMI_TX1N_C

DISPLAYPORT 0

300_0402_5%
1K_0402_5%
1K_0402_5%
300_0402_5%
300_0402_5%
510_0402_1%
1K_0402_5%

0.1U_0402_16V7K
0.1U_0402_16V7K

CLK

1
2
2
1
1
2
2

C510 1
C511 1

A8
B8

SER

2
1
1
2
2
1
1

HDMI_TX2P_C
HDMI_TX2N_C

CTRL

R404
R399
R400
R405
R401
R402
R403

0.1U_0402_16V7K
0.1U_0402_16V7K

C508 1
C509 1

JTAG

2
2

(11) HDMI_TX2P
(11) HDMI_TX2N

DISPLAYPORT 1

U22B
+1.8VS

VDDCR_NB_SENSE
VDDCR_CPU_SENSE
VDDIO_MEM_S_SENSE

H3
G2
H2
H1

TDP1_AUXP
TDP1_AUXN

B2
C2

TDP1_HPD

C1

LTDP0_AUXP
LTDP0_AUXN

A3
B3

EDID_CLK
EDID_DATA

LTDP0_HPD

D3

R406 1

DAC_RED
DAC_REDB
DAC_GREEN
DAC_GREENB
DAC_BLUE
DAC_BLUEB
DAC_HSYNC
DAC_VSYNC

C12
D13
A12
B12
A13
B13

F2
D4

DAC_ZVSS

D12

TEST4
TEST5
TEST6
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST31
TEST33_H
TEST33_L
TEST34_H
TEST34_L
TEST35
TEST36
TEST37

2 150_0402_1%
APU_ENBKL (10)
APU_ENVDD (10)
APU_BLPWM (10)

HDMI_CLK
HDMI_DATA

R1
R2
R6
T5
E4
K4
L1
L2
M2
K1
K2
L5
M5
M21
J18
J19
U15
T15
H4
N5
R5

HDMI_CLK (11)
HDMI_DATA (11)
HDMI_DET (11)
EDID_CLK (10)
EDID_DATA (10)
2 100K_0402_5%

R407 1

2 150_0402_1%

R408 1

2 150_0402_1%

R409 1

2 150_0402_1%

DAC_RED (12)
DAC_GRN (12)
DAC_BLU (12)

E1
E2

DAC_SCL
DAC_SDA

CRT_HSYNC (12)
CRT_VSYNC (12)
CRT_DDC_CLK (12)
CRT_DDC_DATA (12)
R413 1

2 499_0402_1%
PAD T66
PAD T67

TEST15

AMD check list update


20101110

PAD T68

R415 1
@
2 1K_0402_5%
PAD T69
PAD T95
TEST18
R416 1
2 1K_0402_5%
TEST19
R417 1
2 1K_0402_5%
TEST25_H
R419 1
2 510_0402_1%
TEST_25_L
TEST28_H
PAD T71
TEST28_L
PAD T72
TEST31
PAD T73
TEST33_H
C516 1
R420 1
2 0.1U_0402_16V4Z
TEST33_L
C517 1
R421 1
2 0.1U_0402_16V4Z
Delete Test point for layout limitation
20100818
TEST35
R422 1
2 1K_0402_5%
TEST36
nonHDMI@
TEST37
R958 1
2 1K_0402_5%
PAD T76
+1.8VS
HDMI@

2 51_0402_1%
2 51_0402_1%

Pull-high to enable HDMI function


20100812

VSS_SENSE
TEST38
DMAACTIVE_L

RSVD_1
RSVD_2
RSVD_3

R398 1

DP_ZVSS
DP_BLON
DP_DIGON
DP_VARY_BL

K3
T1

ALLOW_STOP# (13)
R423 1

2 1K_0402_5%

+1.8VS

ONTARIO-2M161000-1.6G_BGA413

R424
10K_0402_5%

2
B

R425

1K_0402_5%
1

AMD Debug

Q79
1

H_THERMTRIP# (14)

+1.8VS

MMBT3904_NL_SOT23-3
1
R427 @

2
0_0402_5%

R842

If FCH internal pull-up disabled, level-shifter could be deleted.


Need BIOS to disable internal pull-up!!

APU_TRST#

Vgs(th): min 1.0V


Typ 1.6V
Max 2.0V

need to pop for HDT debug


20101012
@
0_0402_5%
R846 1
2

EC_SMB_DA

Q80A
2N7002DW-T/R7_SOT363-6

1
R431

1
R429
1
R430

FCH_SID

2
0_0402_5%
EC_SMB_DA2
2
0_0402_5%

Q80B
2N7002DW-T/R7_SOT363-6
1
R434
5

1 1K_0402_5%

APU_TDI

R845 2

1 1K_0402_5%

APU_TRST#_R

APU_PWRGD
+1.8VS
LDT_RST#

R848 2 @

1 10K_0402_5%

APU_DBRDY

R849 2 @

1 10K_0402_5%

APU_DBREQ#

R850 1 @

2 300_0402_5%

J108_PLLTST0

R851 1 @

2 0_0402_5%

TEST_19

J108_PLLTST1

R852 1 @

2 0_0402_5%

TEST_18

Please be noted about TEST_18 and TEST_19


FCH_SID

(14)

T0 FCH

EC_SMB_DA2 (19,29,31) TO

need to pop for HDT debug


20101012

EC

2
0_0402_5%

@
APU_SIC

1 1K_0402_5%

R844 2

1 10K_0402_5%

If Q80 or R429, R432 implemented,


R747 & R748 need to be mounted

R843 2

APU_TMS

R847 2 @

@
APU_SID

APU_TCK

APU_TDO

R428
10K_0402_5%
@

2N7002DW-T/R7

+3VS

1K_0402_5%

APU_THERMTRIP#

EC_SMB_CK

@
1
R432
1
R433

FCH_SIC
2
0_0402_5%
EC_SMB_CK2
2
0_0402_5%

FCH_SIC

(14)

T0 FCH

EC_SMB_CK2 (19,29,31) TO EC

Compal Secret Data

Security Classification
2010/06/30

Issued Date

2012/06/30

Deciphered Date

Compal Electronics, Inc.


FT1 CTRL/DP/CRT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2
0_0402_5%

Title

Size Document Number


Custom
Date:

Rev
1.0

LA6755P/7P

Tuesday, November 30, 2010

Sheet
1

of

48

U22E

(8,9) DDR_A_DQS0
(8,9) DDR_A_DQS#0
(8,9) DDR_A_DQS1
(8,9) DDR_A_DQS#1
(8,9) DDR_A_DQS2
(8,9) DDR_A_DQS#2
(8,9) DDR_A_DQS3
(8,9) DDR_A_DQS#3
(8,9) DDR_A_DQS4
(8,9) DDR_A_DQS#4
(8,9) DDR_A_DQS5
(8,9) DDR_A_DQS#5
(8,9) DDR_A_DQS6
(8,9) DDR_A_DQS#6
(8,9) DDR_A_DQS7
(8,9) DDR_A_DQS#7

(8)
(8)
(8)
(8)
(9)
(9)
(9)
(9)

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK3
DDR_B_CLK#3

(8)
(8)
(9)
(9)

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

A16
B16
B20
A20
E23
E22
J22
J23
R22
P22
W22
V22
AC20
AC21
AB16
AC16

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK3
DDR_B_CLK#3

M17
M16
M19
M18
N18
N19
L18
L17

DDR_CKE0
DDR_CKE1

(8,9) DDR_CKE0
(8,9) DDR_CKE1

D15
B19
D21
H22
P23
V23
AB20
AA16

DDR_RST#
DDR_EVENT#

(8,9) DDR_RST#
(8,9) DDR_EVENT#

(8)
(8)
(9)
(9)

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_ODT0
DDR_A_ODT1
DDR_B_ODT0
DDR_B_ODT1

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#

F15
E15

DDR_A_ODT0
DDR_A_ODT1
DDR_B_ODT0
DDR_B_ODT1

W19
V15
U19
W15

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#

T17
W16
U17
V16

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

(8,9) DDR_A_RAS#
(8,9) DDR_A_CAS#
(8,9) DDR_A_WE#

L23
N17

U18
V19
V17

M_DATA0
M_DATA1
M_DATA2
M_DATA3
M_DATA4
M_DATA5
M_DATA6
M_DATA7
M_DATA8
M_DATA9
M_DATA10
M_DATA11
M_DATA12
M_DATA13
M_DATA14
M_DATA15

DDR SYSTEM MEMORY

R18
T18
F16

(8,9) DDR_A_BS0
(8,9) DDR_A_BS1
(8,9) DDR_A_BS2

M_ADD0
M_ADD1
M_ADD2
M_ADD3
M_ADD4
M_ADD5
M_ADD6
M_ADD7
M_ADD8
M_ADD9
M_ADD10
M_ADD11
M_ADD12
M_ADD13
M_ADD14
M_ADD15
M_BANK0
M_BANK1
M_BANK2
M_DM0
M_DM1
M_DM2
M_DM3
M_DM4
M_DM5
M_DM6
M_DM7
M_DQS_H0
M_DQS_L0
M_DQS_H1
M_DQS_L1
M_DQS_H2
M_DQS_L2
M_DQS_H3
M_DQS_L3
M_DQS_H4
M_DQS_L4
M_DQS_H5
M_DQS_L5
M_DQS_H6
M_DQS_L6
M_DQS_H7
M_DQS_L7

M_DATA16
M_DATA17
M_DATA18
M_DATA19
M_DATA20
M_DATA21
M_DATA22
M_DATA23
M_DATA24
M_DATA25
M_DATA26
M_DATA27
M_DATA28
M_DATA29
M_DATA30
M_DATA31
M_DATA32
M_DATA33
M_DATA34
M_DATA35
M_DATA36
M_DATA37
M_DATA38
M_DATA39
M_DATA40
M_DATA41
M_DATA42
M_DATA43
M_DATA44
M_DATA45
M_DATA46
M_DATA47

M_CLK_H0
M_CLK_L0
M_CLK_H1
M_CLK_L1
M_CLK_H2
M_CLK_L2
M_CLK_H3
M_CLK_L3

M_DATA48
M_DATA49
M_DATA50
M_DATA51
M_DATA52
M_DATA53
M_DATA54
M_DATA55

M_RESET_L
M_EVENT_L
M_CKE0
M_CKE1

M_DATA56
M_DATA57
M_DATA58
M_DATA59
M_DATA60
M_DATA61
M_DATA62
M_DATA63

M0_ODT0
M0_ODT1
M1_ODT0
M1_ODT1
M0_CS_L0
M0_CS_L1
M1_CS_L0
M1_CS_L1

B14
A15
A17
D18
A14
C14
C16
D16

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7

C18
A19
B21
D20
A18
B18
A21
C20

DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15

C23
D23
F23
F22
C22
D22
F20
F21

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23

H21
H23
K22
K21
G23
H20
K20
K23

DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31

N23
P21
T20
T23
M20
P20
R23
T22

DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39

V20
V21
Y23
Y22
T21
U23
W23
Y21

DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47

Y20
AB22
AC19
AA18
AA23
AA20
AB19
Y18

DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55

AC17
Y16
AB14
AC14
AC18
AB18
AB15
AC15

DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

M23

+MEM_VREF

M22

R437

DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_DM[0..7]

DDR_A_D[0..63]

(8,9)

DDR_A_MA[0..15]
DDR_A_DM[0..7]

(8,9)
(8,9)

U22A
(18) PCIE_CRX_GTX_P0
(18) PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

AA6
Y6

(18) PCIE_CRX_GTX_P1
(18) PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

AB4
AC4

(18) PCIE_CRX_GTX_P2
(18) PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

AA1
AA2

(18) PCIE_CRX_GTX_P3
(18) PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

Y4
Y3

+1.0VS

1
2
R435 2K_0402_1%

P_ZVDD_10

Y14

P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3

P_GPP_TXP0
P_GPP_TXN0

PCIE I/F

R17
H19
J17
H18
H17
G17
H15
G18
F19
E19
T19
F17
E18
W17
E16
G15

P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3

P_ZVDD_10

P_ZVSS

AB6 PCIE_CTX_C_GRX_P0 C518 1


AC6 PCIE_CTX_C_GRX_N0 C519 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_CTX_GRX_P0 (18)
PCIE_CTX_GRX_N0 (18)

AB3 PCIE_CTX_C_GRX_P1 C520 1


AC3 PCIE_CTX_C_GRX_N1 C521 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_CTX_GRX_P1 (18)
PCIE_CTX_GRX_N1 (18)

Y1
Y2

PCIE_CTX_C_GRX_P2 C522 1
PCIE_CTX_C_GRX_N2 C523 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_CTX_GRX_P2 (18)
PCIE_CTX_GRX_N2 (18)

V3
V4

PCIE_CTX_C_GRX_P3 C524 1
PCIE_CTX_C_GRX_N3 C525 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_CTX_GRX_P3 (18)
PCIE_CTX_GRX_N3 (18)

AA14 P_ZVSS

R436 1

1.27K_0402_1%

Less than 1"


Less than 1"
(13) UMI_RX0P
(13) UMI_RX0N

AA12
Y12

(13) UMI_RX1P
(13) UMI_RX1N

AA10
Y10

(13) UMI_RX2P
(13) UMI_RX2N

AB10
AC10

(13) UMI_RX3P
(13) UMI_RX3N

AC7
AB7

P_UMI_RXP0
P_UMI_RXN0
P_UMI_RXP1
P_UMI_RXN1
P_UMI_RXP2
P_UMI_RXN2
P_UMI_RXP3
P_UMI_RXN3

P_UMI_TXP0
P_UMI_TXN0

UMI I/F

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3

AB12
AC12

UMI_TX0P_C
UMI_TX0N_C

C526 1
C527 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

AC11
AB11

UMI_TX1P_C
UMI_TX1N_C

C528 1
C529 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

AA8
Y8

UMI_TX2P_C
UMI_TX2N_C

C530 1
C531 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

AB8
AC8

UMI_TX3P_C
UMI_TX3N_C

C532 1
C533 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

UMI_TX0P (13)
UMI_TX0N (13)
UMI_TX1P (13)
UMI_TX1N (13)
UMI_TX2P (13)
UMI_TX2N (13)
UMI_TX3P (13)
UMI_TX3N (13)

ONTARIO-2M161000-1.6G_BGA413

M_VREF

M_RAS_L
M_CAS_L
M_WE_L
M_ZVDDIO_MEM_S
ONTARIO-2M161000-1.6G_BGA413

+1.5V

39.2_0402_1%

+1.5V

+1.5V

R438
1K_0402_1%
DDR_EVENT#

2
1K_0402_5%

+MEM_VREF

R444 1

R439
1K_0402_1%

C535

1
1

C534

1000P_0402_50V7K

0.1U_0402_16V4Z

Place within 1000 mils to APU


20100526

Compal Secret Data

Security Classification
Issued Date

2010/06/30

2012/0630

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


FT1 DDRIII/UMI/PCIE

Size
Document Number
Custom
Date:

Rev
1.0

LA6755P/7P

Tuesday, November 30, 2010

Sheet
E

of

48

+APU_CORE
+1.8VS

10U_0603_6.3V6M

1U_0402_6.3V6K
C549

1U_0402_6.3V6K
C548

1U_0402_6.3V6K
C547

1U_0402_6.3V6K
C538

0.1U_0402_16V7K
C546

180P_0402_50V8J
C537

C545

10U_0603_6.3V6M

1U_0402_6.3V6K
C558

C556

10U_0603_6.3V6M

5.5A

1U_0402_6.3V6K
C567

2
1

0.1U_0402_16V7K
C566

L32

+VDD_10

0.5A

10U_0603_6.3V6M
C574

1U_0402_6.3V6K
C573

2
1

1U_0402_6.3V6K
C572

U13
W13
V12
T12

VDD_10_1
VDD_10_2
VDD_10_3
VDD_10_4

FBMA-L11-201209-221LMA30T_0805

10U_0603_6.3V6M

C564

+VDDL_10
180P_0402_50V8J
C565

U11

VDDPL_10

FBMA-L11-201209-221LMA30T_0805
Change from SM010014520 to SD002000080
20100816

+3VS
ONTARIO-2M161000-1.6G_BGA413

A4

VDD_33

N13
N20
N22
P10
P14
R4
R7
R20
T6
T9
T11
T13
U4
U5
U7
U12
U20
U22
V8
V9
V11
V13
W1
W2
W4
W5
W7
W12
W20
Y5
Y7
Y9
Y11
Y13
Y15
Y17
Y19
AA4
AA22
AB2
AB5
AB9
AB13
AB17
AB21
AC5
AC9
AC13
A11

C602

C603

C598

1U_0402_6.3V6K

+1.5V

Near CPU Socket

Issued Date

(S ELE CAP 330U 6.3V M 6.3X5.9 LESR15M VU)*1=(SF000002000)


20100813
4

2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

C615

C614

C613

C612

180P_0402_50V8J

Compal Electronics, Inc.


P07-FT1 PWR/VSS

Size
C
Date:

180P_0402_50V8J

C611

C610

180P_0402_50V8J

C609

180P_0402_50V8J

Compal Secret Data

Security Classification

Near CPU Socket

0.1U_0402_16V7K

0.1U_0402_16V7K

C624

C623

C622

(330uF_6.3V_4.2L_ESR17m)*1=(SF000002Z00)

330U_2.5V_M

Near CPU Socket

22U_0805_6.3V6M

10U_0603_6.3V6M

C608

+1.8VS

unpop for PVT 20101004

0.1U_0402_16V7K

+1.5V

POWER
0.1U_0402_16V7K

POWER

C625

By case (Along split)

1
C619

330U_D2_2.5VY_R9M

+1.0VS

10U_0603_6.3V6M

C618

+1.0VS has been raised to +1.05VS for


AMD design guide 45339_R1.02 update 20101004

VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSSBG_DAC

180P_0402_50V8J

1U_0402_6.3V6K

C597

L31

180P_0402_50V8J

C601

330U_6.3V_M

C616

10U_0603_6.3V6M

1
C607

330U_D2E_2.5VM_R9M

C606

Near CPU Socket

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49

POWER

+APU_CORE_NB

Change from SM010014520 to SD002000080


20100816

10U_0603_6.3V6M

C590
C596

1U_0402_6.3V6K

0.1U_0402_16V7K

330U_D2E_2.5VM_R9M

C600

C621

+
2

C599

220U_B2_2.5VM_R35

10U_0603_6.3V6M

C620

+1.0VS

330U_D2E_2.5VM_R9M

C605

0.1U_0402_16V7K

C595

+APU_CORE

U22D
A7
B7
B11
B17
B22
C4
D5
D7
D9
D11
D14
B15
D17
D19
E7
E9
E12
E20
F8
F11
F13
G4
G5
G7
G9
G12
G20
G22
H6
H11
H13
J4
J5
J7
J20
K10
K14
L4
L6
L8
L11
L13
L20
L22
M7
N4
N6
N8
N11

+1.5V

POWER

180P_0402_50V8J
C557

C589

10U_0603_6.3V6M

C588

1U_0402_6.3V6K

180P_0402_50V8J

180P_0402_50V8J

C587

C586

1U_0402_6.3V6K

0.1U_0402_16V7K

1U_0402_6.3V6K

C585
C594

0.1U_0402_16V7K

1U_0402_6.3V6K

C584
C593

C583
C592

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

C582
C591

0.2A

ONTARIO-2M161000-1.6G_BGA413
1

FBMA-L11-201209-221LMA30T_0805

0.1U_0402_16V7K
C571

VDDIO_MEM_S_1
VDDIO_MEM_S_2
VDDIO_MEM_S_3
VDDIO_MEM_S_4
VDDIO_MEM_S_5
VDDIO_MEM_S_6
VDDIO_MEM_S_7
VDDIO_MEM_S_8
VDDIO_MEM_S_9
VDDIO_MEM_S_10
VDDIO_MEM_S_11

0.1U_0402_16V7K
C570

C579

G16
G19
E17
J16
L16
L19
N16
R16
R19
W18
U16

1U_0402_6.3V6K

2A

10U_0603_6.3V6M

C578

10U_0603_6.3V6M

C577

10U_0603_6.3V6M

C576

10U_0603_6.3V6M

POWER

DP Phy/IO

10U_0603_6.3V6M

+VDD_18_DAC

DDR3

C575

L30
W9

VDD_18_DAC

PCIE/IO/DDR3 Phy

+1.5V

Change from SM010014520 to SD002000080


20100816
+1.8VS

C568

+APU_CORE_NB

VDDCR_NB_1
VDDCR_NB_2
VDDCR_NB_3
VDDCR_NB_4
VDDCR_NB_5
VDDCR_NB_6
VDDCR_NB_7
VDDCR_NB_8
VDDCR_NB_9
VDDCR_NB_10
VDDCR_NB_11
VDDCR_NB_12
VDDCR_NB_13
VDDCR_NB_14
VDDCR_NB_15
VDDCR_NB_16
VDDCR_NB_17
VDDCR_NB_18
VDDCR_NB_19
VDDCR_NB_20
VDDCR_NB_21
VDDCR_NB_22

L29
2
1
FBMA-L11-201209-221LMA30T_0805

0.15A

10A
E8
E11
E13
F9
F12
G11
G13
H9
H12
K11
K13
L10
L12
L14
M11
M12
M13
N10
N12
N14
P11
P13

180P_0402_50V8J
C569

10U_0603_6.3V6M

C540
C555

180P_0402_50V8J

+APU_CORE_NB

U8
W8
U6
U9
W6
T7
V7

VDD_18_1
VDD_18_2
VDD_18_3
VDD_18_4
VDD_18_5
VDD_18_6
VDD_18_7

C580

VDDCR_CPU_1
VDDCR_CPU_2
VDDCR_CPU_3
VDDCR_CPU_4
VDDCR_CPU_5
VDDCR_CPU_6
VDDCR_CPU_7
VDDCR_CPU_8
VDDCR_CPU_9
VDDCR_CPU_10
VDDCR_CPU_11
VDDCR_CPU_12
VDDCR_CPU_13
VDDCR_CPU_14
VDDCR_CPU_15

0.1U_0402_16V7K
C581

C563

E5
E6
F5
F7
G6
G8
H5
H7
J6
J8
L7
M6
M8
N7
R8

0.1U_0402_16V7K

10U_0603_6.3V6M

C544
C554

180P_0402_50V8J

C543

10U_0603_6.3V6M

10U_0603_6.3V6M

C542

1U_0402_6.3V6K

C553
C562

0.1U_0402_16V7K

C541

10U_0603_6.3V6M
1U_0402_6.3V6K

C552
C561

0.1U_0402_16V7K

C536

10U_0603_6.3V6M
1U_0402_6.3V6K

C551
C560

0.1U_0402_16V7K

10U_0603_6.3V6M

C539
C550
C559

DIS PLL

GPU AND NB CORE

DAC

+VDD_18

GND

CPU CORE

1U_0402_6.3V6K

0.1U_0402_16V7K

2A
TSense/PLL/DP/PCIE/IO

U22C

11A

+APU_CORE

Document Number

Rev
1.0

LA6755P/7P
Tuesday, November 30, 2010
1

Sheet

of

48

+1.5V

DDR_A_D26
DDR_A_D27

(6,9) DDR_CKE0
C

(6,9) DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
(6) DDR_A_CLK0
(6) DDR_A_CLK#0
DDR_A_MA10
(6,9) DDR_A_BS0
(6,9) DDR_A_WE#
(6,9) DDR_A_CAS#
DDR_A_MA13
(6) DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33
(6,9) DDR_A_DQS#4
(6,9) DDR_A_DQS4

DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
(6,9) DDR_A_DQS#6
(6,9) DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7

1
R446
10K_0402_5%

205
207

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
GND1
BOSS1

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
BOSS2

2
1

+VREF_CA
2

DDR_A_DM1

R443
1K_0402_1%
1

R442
1K_0402_1%

DDR_RST# (6,9)
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21

Combine to one?

DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3 (6,9)
DDR_A_DQS3 (6,9)
DDR_A_D30
DDR_A_D31

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_A_MA11
DDR_A_MA7

0.1U_0402_16V4Z
2
C628

1
0.1U_0402_16V4Z

DDR_A_MA6
DDR_A_MA4

C629
1

0.1U_0402_16V4Z
2
C630

1
0.1U_0402_16V4Z

C631
1

0.1U_0402_16V4Z
2
C632

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

C633

C634
@
1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

C635
@

C636
@
1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

C637
@

C638
@
1
0.1U_0402_16V4Z

C639
@

DDR_A_MA2
DDR_A_MA0
DDR_A_CLK1 (6)
DDR_A_CLK#1 (6)
DDR_A_BS1 (6,9)
DDR_A_RAS# (6,9)
DDR_CS0_DIMMA# (6)
DDR_A_ODT0 (6)

CRB 0.1u X1

4.7u X1

CRB

100U

DDR_A_ODT1 (6)

X2

+1.5V
+0.75VS
+VREF_CA

DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45

1
+
2

20100729
DDR_A_DQS#5 (6,9)
DDR_A_DQS5 (6,9)

Place near JDIMM1

DDR_A_D46
DDR_A_D47

SF000002Y00

DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7 (6,9)
DDR_A_DQS7 (6,9)
DDR_A_D62
DDR_A_D63
A

DDR_EVENT# (6,9)
FCH_SMDAT0 (9,14,30)
FCH_SMCLK0 (9,14,30)
+0.75VS

Compal Secret Data

Security Classification

DDR3 SO-DIMM A
Reverse Type

+1.5V

DDR_CKE1 (6,9)
DDR_A_MA15
DDR_A_MA14

206
208

LCN_DAN06-K4406-0103

+VREF_DQ

DDR_A_D12
DDR_A_D13

0.1U_0402_16V4Z

C647

C646

+3VS

2.2U_0603_6.3V4Z

DDR_A_D58
DDR_A_D59
R445
10K_0402_5%
1
2

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

R441
1K_0402_1%

C643

DDR_A_DM3

R440
1K_0402_1%

DDR_A_DM[0..7] (6,9)

220U_6.3V_M

DDR_A_D24
DDR_A_D25

DDR_A_MA[0..15] (6,9)

DDR_A_DM[0..7]

DDR_A_D6
DDR_A_D7

4.7U_0603_6.3V6K

DDR_A_D18
DDR_A_D19

+1.5V

C642

(6,9) DDR_A_DQS#2
(6,9) DDR_A_DQS2

DDR_A_MA[0..15]

DDR_A_DQS#0 (6,9)
DDR_A_DQS0 (6,9)

+1.5V
(6,9)

0.1U_0402_16V4Z

DDR_A_D16
DDR_A_D17

DDR_A_D[0..63]

C641

DDR_A_D10
DDR_A_D11

DDR_A_D[0..63]

0.1U_0402_16V4Z

(6,9) DDR_A_DQS#1
(6,9) DDR_A_DQS1

DDR_A_D4
DDR_A_D5

C640

DDR_A_D8
DDR_A_D9

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

0.1U_0402_16V4Z

DDR_A_D2
DDR_A_D3

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

C644

DDR_A_DM0

ME@

1000P_0402_50V7K

DDR_A_D0
DDR_A_D1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

C645

C627

1000P_0402_50V7K

0.1U_0402_16V4Z

C626

+1.5V
JDIMM1

+VREF_DQ

Issued Date

2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

Compal Electronics, Inc.


DDR3 SODIMM-I Socket

Size Document Number


Custom
Date:

Rev
1.0

LA6755P/7P

Tuesday, November 30, 2010

Sheet
1

of

48

+1.5V

DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9

(6,8) DDR_A_DQS#1
(6,8) DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
(6,8) DDR_A_DQS#2
(6,8) DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

DDR_A_D4
DDR_A_D5
DDR_A_DQS#0 (6,8)
DDR_A_DQS0 (6,8)

DDR_A_D[0..63]

DDR_A_DM[0..7]

DDR_RST# (6,8)
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3 (6,8)
DDR_A_DQS3 (6,8)

+1.5V

DDR_A_D30
DDR_A_D31
2

0.1U_0402_16V4Z
2

(6) DDR_B_CLK2
(6) DDR_B_CLK#2
DDR_A_MA10
(6,8) DDR_A_BS0
(6,8) DDR_A_WE#
(6,8) DDR_A_CAS#
DDR_A_MA13
(6) DDR_CS1_DIMMB#

DDR_A_D32
DDR_A_D33
(6,8) DDR_A_DQS#4
(6,8) DDR_A_DQS4

DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
(6,8) DDR_A_DQS#6
(6,8) DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
For DRAM strap pin reservation
20100817
R961 1
R448 1

DDR_A_D58
DDR_A_D59

2 10K_0402_5%
2 10K_0402_5%

+3VS

1
C667
2.2U_0603_6.3V4Z

C668
2
0.1U_0402_16V4Z

only one 4.7k

R449
10K_0402_5%

205

G1

G2

1
1
0.1U_0402_16V4Z

C654

C655

1
0.1U_0402_16V4Z

C656
@

1
1
0.1U_0402_16V4Z

C657
@

0.1U_0402_16V4Z
2
2
C658
@

1
0.1U_0402_16V4Z

C659
@

2
C660
@

1
0.1U_0402_16V4Z

C661
0.1U_0402_16V4Z
@

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4

CRB 0.1u X1

4,7uX1

DDR_A_MA2
DDR_A_MA0
+0.75VS
DDR_B_CLK3 (6)
DDR_B_CLK#3 (6)

DDR_A_BS1 (6,8)
DDR_A_RAS# (6,8)

DDR_CS0_DIMMB# (6)
DDR_B_ODT0 (6)

DDR_B_ODT1 (6)
+VREF_CA
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

Place near JDIMM2

DDR_A_DQS#5 (6,8)
DDR_A_DQS5 (6,8)
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7 (6,8)
DDR_A_DQS7 (6,8)
DDR_A_D62
DDR_A_D63
DDR_EVENT# (6,8)
FCH_SMDAT0 (8,14,30)
FCH_SMCLK0 (8,14,30)

+0.75VS

206

LCN_DAN06-K4806-0103

R962
10K_0402_5%

DDR3 SO-DIMM B
Reverse Type

For DRAM strap pin reservation


20100817

C653

0.1U_0402_16V4Z
2
2

DDR_A_MA15
DDR_A_MA14

CRB

C652

0.1U_0402_16V4Z
2
2

C662

DDR_A_MA3
DDR_A_MA1

1
0.1U_0402_16V4Z

DDR_CKE1 (6,8)

C651

0.1U_0402_16V4Z
2
2

C666

DDR_A_MA8
DDR_A_MA5

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

1000P_0402_50V7K

DDR_A_MA12
DDR_A_MA9

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

C665

(6,8) DDR_A_BS2

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDR_A_DM[0..7] (6,8)

DDR_A_DM1

0.1U_0402_16V4Z

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

(6,8) DDR_CKE0

(6,8)

DDR_A_MA[0..15] (6,8)

DDR_A_D12
DDR_A_D13

C650
C

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_D6
DDR_A_D7

C664

DDR_A_DM0

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

4.7U_0603_6.3V6K

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

C663

C648 C649
2

ME@

0.1U_0402_16V4Z

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

DDR_A_D0
DDR_A_D1

0.1U_0402_16V4Z

1000P_0402_50V7K

0.1U_0402_16V4Z

+1.5V
JDIMM2

+VREF_DQ

Compal Secret Data

Security Classification
2010/06/30

Issued Date

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

Compal Electronics, Inc.


DDR3 SODIMM-II Socket

Size Document Number


Custom
Date:

Rev
1.0

LA6755P/7P

Tuesday, November 30, 2010

Sheet
1

of

48

LCD POWER CIRCUIT


+LCDVDD

+5VALW

+3VS

R458
150_0603_1%

LVDS_A0
LVDS_A0#

1
2
G

Change footprint
20100812

C669
4.7U_0603_6.3V6K

S
LVDS_A1
LVDS_A1#

Change footprint
20100812

LVDS_A2
LVDS_A2#
LVDS_ACLK
LVDS_ACLK#

(5) APU_ENVDD

IN

(5) LVDS_ACLK
(5) LVDS_ACLK#

LVDS_A2
LVDS_A2#

Q81
2N7002H_SOT23-3

220K_0402_5%

LVDS_A1
LVDS_A1#

(5)
(5)

R462

OUT

(5)
(5)

LVDS_A0
LVDS_A0#

GND

(5)
(5)

EDID_CLK
EDID_DATA

EDID_CLK
EDID_DATA

W=60mils
Change footprint
20100812

(5)
(5)

R459
100K_0402_5%

Q82
AP2301GN-HF_SOT23-3

C670

W=60mils

0.1U_0402_16V4Z
+LCDVDD
1

Q83
DTC124EKAT146_SC59-3

C671
4.7U_0603_6.3V6K

2
1
R491
1
R490

(31) INVT_PWM

2
0_0402_5%
2
0_0402_5%

FBMA-L11-201209-221LMA30T_0805

R473
@
100K_0402_5%

(5) APU_BLPWM

+LCDVDD_CONN

L33

C672
0.1U_0402_16V4Z

Change footprint
20100812

INVTPWM

pop R490 instead of R491


20100727
R477 1

0_0402_5%

ENBKL

(31)

(5) APU_ENBKL

+LEDVDD

R480
100K_0402_1%

B+

C673
680P_0402_50V7K
@

2 0_0805_5%

1 R479

C674
4.7U_0805_25V6-K
+3VS

+3VS
@
680P_0402_50V7K
C675

(31)

CE_EN

CE_EN
INVTPWM
DISPOFF#

AMD check list update


20101110

+5VS

R487
2K_0402_5%

GNDGND

USB20_N1
USB20_P1

USB20_N1 (14)
USB20_P1 (14)

+3VS_CMOS

CMOS

LVDS_A0#
LVDS_A0

@
R483
10K_0402_5%

1
R484

LVDS_A1#
LVDS_A1
LVDS_A2#
LVDS_A2

(31)

2
0_0402_5%

BKOFF#

LVDS_ACLK#
LVDS_ACLK

DISPOFF#

RB751V_SOD323
D4 @
B

R485
10K_0402_5%

31

ACES_87142-3041-BS
ME@

R486
2K_0402_5%
EDID_CLK
EDID_DATA

32

JLVDS1
1 1
3 3
5 5
7
7
9 9
11 11
13
13
15 15
17 17
19 19
21 21
23 23
25 25
27 27
29 29

(60 MIL)

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

+LCDVDD_CONN

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

CMOS Camera
+3VS

R928 1 CMOS@ 2 0_0402_5%

+5VS_CMOS

2 0_0402_5%

1 @
C679

CMOS@

100K_0402_5%

20100728
(31) CMOS_OFF#

OUT

R938
0_0402_5%
@

IN

GND

20100728

+5VALW

R488

2010/06/30

Issued Date

R880
150K_0402_5%

C680
2

CMOS@

C676
0.1U_0402_16V4Z
2 CMOS@

+3VS_CMOS
1
C681
10U_0805_10V4Z
2 CMOS@

Q85
DTC124EKAT146_SC59-3
CMOS@

2012/06/30

Deciphered Date

1
R489
0_0603_5%
CMOS@

0.1U_0402_16V4Z

CMOS@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

CMOS1
1

Compal Secret Data

Security Classification

+CMOS_PW

CMOS@
Change footprint
20100812

DISPOFF#

For EMI

AP2301GN-HF_SOT23-3

R927 1 @

470P_0402_50V7K

470P_0402_50V7K

1 @
C677

+5VS

Q84
APU_BLPWM

Title

Compal Electronics, Inc.


LVDS/CAMERA

Size
B
Date:

Document Number

Rev
1.0

LA6755P/7P
Tuesday, November 30, 2010

Sheet
1

10

of

48

+5VS
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)

R513
R514
R515
R516
R517
R518
R519
R520

HDMI_CLKP
HDMI_CLKN
HDMI_TX0P
HDMI_TX0N
HDMI_TX1P
HDMI_TX1N
HDMI_TX2P
HDMI_TX2N

1
1
1
1
1
1
1
1

HDMI@
HDMI@
HDMI@
HDMI@
HDMI@
HDMI@
HDMI@
HDMI@

2
2
2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

HDMI_CLK+_CONN
HDMI_CLK-_CONN
HDMI_TX0+_CONN
HDMI_TX0-_CONN
HDMI_TX1+_CONN
HDMI_TX1-_CONN
HDMI_TX2+_CONN
HDMI_TX2-_CONN

+5VS

3
HDMIDAT_R

@
D5
BAT54S-7-F_SOT23-3

HDMICLK_R

@
D6
BAT54S-7-F_SOT23-3

+3VS

@ L34
1

HDMI_CLK+_CONN
HDMI_CLK+_CONN

1
R500

HDMI_CLKN

HDMI_CLK-_CONN

HDMI_CLK-_CONN

1
R501

HDMI_TX0+_CONN

WCM-2012-900T_4P

1
R502

HDMI_TX0-_CONN

@ L35
HDMI_TX0P

HDMI_TX0+_CONN

1
R503

HDMI_TX1+_CONN

1
R505

HDMI_TX0N

HDMI_TX0-_CONN

HDMI_TX1-_CONN

1
R506

HDMI_TX2+_CONN

WCM-2012-900T_4P

1
R508

HDMI_TX2-_CONN

HDMI_TX1P

HDMI_TX1N

1
4

HDMI_TX1+_CONN

HDMI_TX1-_CONN

1
R509

499_0402_1%
499_0402_1%

499_0402_1%
499_0402_1%

499_0402_1%

0_0402_5%
Q87
2N7002H_SOT23-3
HDMI@

@
R512
100K_0402_5%

HDMI_TX2+_CONN

NEAR CONNECT
3

2
G
3

HDMIDAT_R

2N7002KDWH_SOT363-6
Q86B
HDMI@

@
R815

@
R816

2 0_0402_5%

HDMI_TX2N

(5) HDMI_DATA

499_0402_1%

@ L37
HDMI_TX2P

HDMICLK_R

6
2N7002KDWH_SOT363-6
Q86A
HDMI@

499_0402_1%

+5VS

WCM-2012-900T_4P

Change footprint
20100812

(5) HDMI_CLK

499_0402_1%

@ L36

2
HDMI@
2
HDMI@
2
HDMI@
2
HDMI@
2
HDMI@
2
HDMI@
2
HDMI@
2
HDMI@

HDMI_CLKP

HDMI_TX2-_CONN

WCM-2012-900T_4P
@ R521
0_0805_5%
D7

Add fuse for safety requirement


+5VS_HDMI_F
20100923
2
2

+5VS

0_0402_5%
HDMI@

R525
1
2
150K_0402_5%
@

HDMI_DET

HDMIDAT_R
HDMICLK_R
HDMI_CLK-_CONN
HDMI_CLK+_CONN
HDMI_TX0-_CONN

@
R528
100K_0402_5%

HDMI_TX0+_CONN
HDMI_TX1-_CONN

1
2

JHDMI1
HDMI_HPD

@
D8
BAT54S-7-F_SOT23-3

HDMI_HPD

@
R527
200K_0402_5%
R530
100K_0402_5%
HDMI@

HDMI_HPD

2
B
E

C
@ Q88
MMBT3904_NL_SOT23-3

C690
0.1U_0402_16V4Z
HDMI@

AMD check list update


20101110

3
+3VS

(5)

2
1

R524

HDMI@
R523
2K_0402_5%
1

HDMI@
R522
2K_0402_5%

+5VS

+5VS_HDMI
1

RB491D_SC59-3
HDMI@

HDMI@
F2
1.1A_6V_SMD1812P110TF
1

HDMI_TX1+_CONN
HDMI_TX2-_CONN
HDMI_TX2+_CONN

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKG1
CK_shield
G2
CK+
G3
D0G4
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

20
21
22
23

SUYIN_100042GR019M23DZL
ME@
A

2010/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

HDMI Connector
Size Document Number
Custom
Date:

Rev
1.0

LA6755P/7P

Tuesday, November 30, 2010

Sheet
1

11

of

48

(5)

DAC_GRN

(5)

DAC_BLU

FCM1608CF-121T03 0603
1
2
L38
FCM1608CF-121T03 0603
1
2
L39
FCM1608CF-121T03 0603
1
2
L40
1
1

DAC_RED
DAC_GRN
DAC_BLU

DAC_RED

(5)

1
R533
150_0402_1%

R532
150_0402_1%

R531
150_0402_1%

1
C692

C693

C694
10P_0402_50V8J

10P_0402_50V8J 10P_0402_50V8J

CLOSE TO CONN

RED

GREEN
BLUE

C697

1
C695

C696
10P_0402_50V8J

+5VS

+5VS

10P_0402_50V8J10P_0402_50V8J

+5VS

BLUE

RED

BAT54S-7-F_SOT23-3

@
D9
BAT54S-7-F_SOT23-3
+CRT_VCC

GREEN

@
D10
BAT54S-7-F_SOT23-3

@
D11

R537

+5VS

+5VS

1
3
JVGA_HS

2
5

1K_0402_5%

P
2

OE#

2
(5) CRT_HSYNC

JVGA_VS

C699
0.1U_0402_16V4Z

CRT_HSYNC_1

3
+CRT_VCC

JVGA_HS

1
2
L41
FCM1608CF-121T03 0603

U23
SN74AHCT1G125DCKR_SC70-5

R543

2
@
D12
BAT54S-7-F_SOT23-3

@
D13
BAT54S-7-F_SOT23-3

@
C700
10P_0402_50V8J

P
2

A
G

(5) CRT_VSYNC

2
OE#

C701
0.1U_0402_16V4Z

1K_0402_5%

CRT_VSYNC_1

1
2
L42
FCM1608CF-121T03 0603

U24
SN74AHCT1G125DCKR_SC70-5

JVGA_VS

@ C702
10P_0402_50V8J

D14

2
3

+3VS

CRT Connector

+CRT_VCC

+5VS

F1

2
1

RB491D_SC59-3

+3VS

+CRT_VCC

1
R549
2K_0402_5%
JCRT1

Change footprint
20100812

CRT_DDC_DAT_CONN

CRT_DDC_DAT_CONN
GREEN

2N7002KDW H_SOT363-6
Q89B

JVGA_HS
BLUE
JVGA_VS

(5) CRT_DDC_CLK

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

RED

(5) CRT_DDC_DATA

CRT_DDC_CLK_CONN

CRT_DDC_CLK_CONN
2N7002KDW H_SOT363-6
Q89A

@
C703
100P_0402_50V8J

1
R964

2
0_0402_5%

1
R965

2
0_0402_5%

@
C704
68P_0402_50V8K

AMD check list update


20101110

Compal Secret Data

Security Classification
2010/06/30

Issued Date

Deciphered Date

2012/06/30

Title

G
G

16
17

C698

CONTE_80431-5K1-152

100P_0402_50V8J

ME@

Compal Electronics, Inc.


CRT Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

C691
0.1U_0402_16V4Z

R548
2K_0402_5%

R547
2K_0402_5%

W=40mils
R546
2K_0402_5%

1.1A_6V_SMD1812P110TF

Size
Document Number
Custom
Date:

Rev
1.0

LA6755P/7P

Tuesday, November 30, 2010

Sheet
E

12

of

48

1
1

590_0402_1%
2K_0402_1%

2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

AA22
Y21
AA25
AA24
W23
V24
W24
W25

PCIE_FRX_DTX_P0
PCIE_FRX_DTX_N0
PCIE_FRX_DTX_P1
PCIE_FRX_DTX_N1

close to FCH within 1"


(5)
(5)

DISP_CLK
DISP_CLK#

AA28
AA29
Y29
Y28
Y26
Y27
W28
W29

R564 1
R565 1

2 0_0402_5%
2 0_0402_5%

M23
P23

DISP_CLK_R
DISP_CLK#_R

U29
U28
T26
T27

(18) CLK_PCIE_VGA
(18) CLK_PCIE_VGA#

R569 1
R570 1

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_VGA_R
CLK_PCIE_VGA#_R

V23
T23

(26) CLK_PCIE_LAN
(26) CLK_PCIE_LAN#

R571 1
R572 1

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R

L29
L28

LAN

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_WLAN_R
CLK_PCIE_WLAN#_R

WLAN

(30) CLK_PCIE_WLAN
(30) CLK_PCIE_WLAN#

R573 1
R574 1

N29
N28
M29
M28

L24
L23

CPU_HT_CLKP
CPU_HT_CLKN
SLT_GFX_CLKP
SLT_GFX_CLKN
GPP_CLK0P
GPP_CLK0N
GPP_CLK1P
GPP_CLK1N
GPP_CLK2P
GPP_CLK2N
GPP_CLK3P
GPP_CLK3N
GPP_CLK4P
GPP_CLK4N

P29
P28

GPP_CLK6P
GPP_CLK6N

N26
N27

GPP_CLK7P
GPP_CLK7N

Y5

1M_0603_5%
25M_CLK_X2
R576

L27

AJ6
AG6
AG4
AJ4

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27

LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME_L
LDRQ0_L
LDRQ1_L/CLK_REQ6_L/GPIO49
SERIRQ/GPIO48

@ R562 20M_0402_5%
@R562
1
2
Change from 22P to 18P for RTC correction
20101012
C719
RTC_32KHO
1
2

ALLOW_LDTSTP/DMA_ACTIVE_L
PROCHOT_L
LDT_PG
LDT_STP_L
LDT_RST_L

H24
H25
J27
J26
H29
H28
G28
J25
AA18
AB19

25M_X1

25M_X2

NC

RTC_32KHI

+3VS

R568
10K_0402_5%
PE_GPIO1 (20,21,43)
APU_PWRGD

H_PWRGD_L (44)

SB_ARST#_GATE
FDV301N_NL_SOT23-3
Q90

For PX function reserved

2 0_0402_5%

R575 1
R854 1

LPCCLK0 (17)

2 22_0402_5%
2 0_0402_5%

LPC_CLK0_EC (31)
CLK_PCI_DB (30)

LPC_AD0 (30,31)
LPC_AD1 (30,31)
LPC_AD2 (30,31)
LPC_AD3 (30,31)
LPC_FRAME# (30,31)

@
C1011
100P_0402_50V8J

Reserve for EMI for PVT build


20101005

SERIRQ (31)

G21
H21
K19
G22
J24

ALLOW_STOP# (5)
FCH_PROCHOT# (5)
APU_PWRGD (5)
LDT_RST# (5)

32K_X1

RTC_32KHI

32K_X2

C2

RTC_32KHO

D2
B2
B1

Deciphered Date

OSC

32.768KHZ_12.5PF_9H03200413

+1.8VS

@
1 R920
@
1 R921

SUSCLK

2 0_0402_5%

FCH_RTCX1_OUT (31)

2 0_0402_5%

FCH_RTCX2_OUT (31)

(31)

W=20mils

+RTCBATT
1
R577

2
510_0402_5%

1
C723
2

2012/06/30

CLRP1 @
SHORT PADS

for Clear CMOS

Compal Secret Data


2010/06/30

NC

18P_0402_50V8J

21807-A11-HUDSON-M1_FCBGA605

OSC

C720
1
2

C1

RTCCLK
INTRUDER_ALERT_L
VDDBT_RTC_G

Y4
4

Title

Compal Electronics, Inc.


FCH PCIE/PCI/ACPI/LPC/RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

Close to SB

(17)
(17)
(17)
(17)
(17)

R563
20M_0603_5%

14M_25M_48M_OSC

Security Classification

2 100K_0402_5%

CLK_PCI_DB_R (17)

GPP_CLK8P
GPP_CLK8N

Issued Date

PX@ 2 100K_0402_5%

18P_0402_50V8J

25MHZ_20PF_7A25000012

PE_GPIO0 R918 1

PE_GPIO0 (18)

R853 1

L26

INTE_L/GPIO32
INTF_L/GPIO33
INTG_L/GPIO34
INTH_L/GPIO35

PE_GPIO1 R919 1

20101012

C722
22P_0402_50V8J
1
2

NB_HT_CLKP
NB_HT_CLKN

RTC

C721
22P_0402_50V8J

NB_DISP_CLKP
NB_DISP_CLKN

CPU

25M_CLK_X1

PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN

GPP_CLK5P
GPP_CLK5N

L25

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N

P25
M25

T29
T28

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N

LPC

T25
V25

PCIE_CALRP
PCIE_CALRN

V21
T21

PAD T92
AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7

APU_CLK_R
APU_CLK#_R

PCI_CLK3 (17)
PCI_CLK4 (17)

V2

2 0_0402_5%
2 0_0402_5%

APU_CLK
APU_CLK#

AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0_L
CBE1_L
CBE2_L
CBE3_L
FRAME_L
DEVSEL_L
IRDY_L
TRDY_L
PAR
STOP_L
PERR_L
SERR_L
REQ0_L
REQ1_L/GPIO40
REQ2_L/CLK_REQ8_L/GPIO41
REQ3_L/CLK_REQ5_L/GPIO42
GNT0_L
GNT1_L/GPO44
GNT2_L/GPO45
GNT3_L/CLK_REQ7_L/GPIO46
CLKRUN_L
LOCK_L

CLOCK GENERATOR

R566 1
R567 1

(5)
(5)

PCI_CLK1 (17)

10K_0402_5%

AD29
AD28
PCIE_FTX_DRX_P0
PCIE_FTX_DRX_N0
PCIE_FTX_DRX_P1
PCIE_FTX_DRX_N1

UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N

PCI I/F

(26)
(26)
(30)
(30)

PCIE_FTX_C_DRX_P0
PCIE_FTX_C_DRX_N0
PCIE_FTX_C_DRX_P1
PCIE_FTX_C_DRX_N1

1
1
1
1

PCIRST_L

PAD T96
PCI_CLK2

(26)
(26)
(30)
(30)

2
2
C715
C716
C717
C718

UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N

W2
W1
W3
W4
Y1

LAN
WLAN

R560
R561

PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39

+PCIE_VDDAN

AE24
AE23
AD25
AD24
AC24
AC25
AB25
AB24

PCIE_RST_L
A_RST_L

UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N

AD26
AD27
AC28
AC29
AB29
AB28
AB26
AB27

(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)

UMI_RX0P_C
UMI_RX0N_C
UMI_RX1P_C
UMI_RX1N_C
UMI_RX2P_C
UMI_RX2N_C
UMI_RX3P_C
UMI_RX3N_C

PCI EXPRESS I/F

update for PX function


20100811

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

2
2
2
2
2
2
2
2

P1
L1

PLT_RST# (26,30,31)

UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N

1
1
1
1
1
1
1
1

U26E
A_RST#

1 PX@
2
R559
0_0603_5%

(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)

C707
C708
C709
C710
C711
C712
C713
C714

1 33_0402_5%

10K_0402_5%

NC7SZ08P5X_NL_SC70-5

R557 2

PLT_RST#

R554

150P_0402_50V8J
C706 1
2

PX_RST# (18)

R558

Y
A

5
B

2
1

Watchdog timer on NB_PWRGD


enable for pull-up
+3VS
disable for pull-down
20100527
@

T78
PAD

PCI CLKS

R555
100K_0402_5%

1U_0402_6.3V4Z

update for PX function


20100811

@ U25

PLT_RST#

0.1U_0402_16V4Z
SB_ARST#_GATE
2

+3VALW

C705

Size Document Number


Custom
Date:

Rev
1.0

LA6755P/7P

Tuesday, November 30, 2010

Sheet
E

13

of

48

+3VALW

U26A

2 10K_0402_5%
(26,30) FCH_PCIE_WAKE#
(5) H_THERMTRIP#

G1

(31) EC_RSMRST#
20100802
R580 2

(33) SATA_DET#
(26) LAN_CLKREQ#

1 0_0402_5%

R581 2

1 0_0402_5%

5
P
4

@
C1008
100P_0402_50V8J

(30) WLAN_CLKREQ#

ICH_POK (31)

VGATE (31,44)

@
NC7SZ08P5X_NL_SC70-5
C725
U27 @
0.1U_0402_16V7K
3

Y
G

(44) FCH_PWRGD

@
(19) PEG_CLKREQ#
C1009
100P_0402_50V8J

USB_OC7#

R583 1
R585 1

2 33_0402_5%
2 33_0402_5%

R593

2 10K_0402_5%
2 10K_0402_5%

2 10K_0402_5%

10K_0402_5%
R910

10K_0402_5%
R911
2 BACO@ 1

nonHDMI@
2
1

10K_0402_5%
R912
PX@ 1
2

R596

GPIO189
GPIO190
GPIO191

R913

10K_0402_5%
R913

10K_0402_5%
R914
2 UMA@ 1

2 HDMI@ 1

10K_0402_5%
R915
2 UMA@ 1

R600

BOARD
Config.

2 10K_0402_5%

2 10K_0402_5%

1
T85
T86

0_0402_5%

SD028000080

PAD
PAD

For BRD Config.

GPIO189

GPIO190

GPIO191

T1
T4
L6
L5
T9
U1
U3
T2
U2
T5
V5
P5
M5
P9
T7
P7
M7
P4
M9
V7

GPIO187 E23
GPIO188 E24
F21
G29
GPIO189
GPIO190
GPIO191

PX3@

M3
N1
L2
M2
M1
M4
N2
P2

D27
F28
F29
E27

BLINK/USB_OC7_L/GEVENT18_L
USB_OC6_L/IR_TX1/GEVENT6_L
USB_OC5_L/IR_TX0/GEVENT17_L
USB_OC4_L/IR_RX0/GEVENT16_L
USB_OC3_L/AC_PRES/TDO/GEVENT15_L
USB_OC2_L/TCK/GEVENT14_L
USB_OC1_L/TDI/GEVENT13_L
USB_OC0_L/TRST_L/GEVENT12_L

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST_L
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST_L
GBE_PHY_INTR

GBE LAN

+3VALW +3VALW +3VALW

H3
D1
E4
D4
E8
F7
E7
F8

B12
A12

USB_HSD12P
USB_HSD12N

F11
E11

PS2_DAT/SDA4/GPIO187
PS2_CLK/SCL4/GPIO188
SPI_CS2_L/GBE_STAT2/GPIO166
FC_RST_L/GPO160

USB_RCOMP 1

2
11.8K_0402_1%

Root

E14
E12
J12
J14
A13
B13
D13
C13
G12
G14

USB20_P7 (30)
USB20_N7 (30)

G16
G18

USB20_P6 (34)
USB20_N6 (34)

USB_HSD5P
USB_HSD5N

D16
C16

USB20_P5 (33)
USB20_N5 (33)

USB_HSD4P
USB_HSD4N

B14
A14

USB20_P4 (34)
USB20_N4 (34)

USB_HSD3P
USB_HSD3N

E18
E16

USB20_P3 (33)
USB20_N3 (33)

USB_HSD2P
USB_HSD2N

J16
J18

USB20_P2 (33)
USB20_N2 (33)

B17
A17

USB20_P1 (10)
USB20_N1 (10)

A16
B16

USB20_P0 (33)
USB20_N0 (33)

USB_HSD7P
USB_HSD7N
USB_HSD6P
USB_HSD6N

USB_HSD1P
USB_HSD1N
USB_HSD0P
USB_HSD0N

SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/GPIO199
EC_PWM3/EC_TIMER3/GPIO200

EMBEDDED CTRL

R5911
R5921
+3VALW

HDA_BITCLK
HDA_SDOUT
HDA_SDIN0

2 33_0402_5% HDA_SYNC
2 33_0402_5% HDA_RST#

R589 1
R590 1

(28) HDA_SYNC_AUDIO
(28) HDA_RST_AUDIO#

USB_OC5#

(46) ODD_DA#_FCH
(46) ODD_DETECT#
(34) USB_OC2#
(33) USB_OC1#
(33) USB_OC0#

(28) HDA_BITCLK_AUDIO
(28) HDA_SDOUT_AUDIO
(28) HDA_SDIN0

Pull-down for enable high performance mode


20100527 (required for M1)

1
0_0402_5%

USB_HSD13P
USB_HSD13N

USB_HSD8P
USB_HSD8N

HD AUDIO

PEG_CLKREQ#_R
2
10K_0402_5%
FCH_SMCLK1
2
10K_0402_5%
FCH_SMDAT1
2
10K_0402_5%
EC_RSMRST#
2
2.2K_0402_5%
HDA_BITCLK
2
10K_0402_5%
HDA_SDIN0
2
10K_0402_5%
HDA_SDOUT
2
10K_0402_5%

(31) EC_LID_OUT#

Reserve for EMI for PVT build


20101005
1
R823
1
R587
1
R588
1
R606
1
R607
1
R608
1
R609

USB_FSD0P/GPIO185
USB_FSD0N

H9
J8

USB_HSD9P
USB_HSD9N

USB OC

Reserve for EMI for PVT build


20101005

R582

J10
H11

USB_HSD10P
USB_HSD10N

USB 2.0

+3VS @
C724 0.1U_0402_16V7K
1
2

R578
G19

USB_FSD1P/GPIO186
USB_FSD1N

USB_HSD11P
USB_HSD11N

RSMRST_L
CLK_REQ4_L/SATA_IS0_L/GPIO64
CLK_REQ3_L/SATA_IS1_L/GPIO63
SMARTVOLT1/SATA_IS2_L/GPIO50
CLK_REQ0_L/SATA_IS3_L/GPIO60
SATA_IS4_L/FANOUT3/GPIO55
SATA_IS5_L/FANIN3/GPIO59
SPKR_GPIO66
SCL0_GPIO43
SDA0_GPIO47
SCL1_GPIO227
SDA1_GPIO228
CLK_REQ2_L/FANIN4_GPIO62
CLK_REQ1_L/FANOUT4_GPIO61
IR_LED_L/LLB_L/GPIO184
SMARTVOLT2/SHUTDOWN_L/GPIO51
DDR3_RST_L/GEVENT7_L
GBE_LED0/GPIO183
GBE_LED1/GEVENT9_L
GBE_LED2/GEVENT10_L
GBE_STAT0/GEVENT11_L
CLK_REQG_L/GPIO65_OSCIN

A10

10mils and <1"

GPIO

(28) FCH_SPKR
(8,9,30) FCH_SMCLK0
(8,9,30) FCH_SMDAT0

AD19
AA16
AB21
AC18
AF20
AE19
AF19
AD22
AE22
FCH_SMCLK1
F5
FCH_SMDAT1
F4
AH21
AB18
E1
AJ21
H4
D5
D7
G5
K3
PEG_CLKREQ#_R AA20

USB_RCOMP

KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226

D25
F23
B26
E26
F25
E22
F22
E21

GPIO193
GPIO194

R584 2
R586 2

RP
LP2
COMBO Root
CMOS
LP1

1 10K_0402_5%
1 10K_0402_5%
FCH_SIC (5)
FCH_SID (5)

EC_PWM2
EC_PWM3

Internal Pull-Up available

G24
G25
E28
E29
D29
D28
C29
C28

+3VALW
3

B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22

PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192

EC_PWM3
EC_PWM2

EC_PWM3 EC_PWM2

21807-A11-HUDSON-M1_FCBGA605

Function

WLAN Root
CR
BT

10K_0402_5%
1
2
R595

GATEA20
KB_RST#
EC_SCI#
EC_SMI#

USBCLK/14M_25M_48M_OSC

2.2K_0402_5%
2
1
R602

(31)
SLP_S3#
(31)
SLP_S5#
(31) PBTN_OUT#

PCI_PME_L/GEVENT4_L
RI_L/GEVENT22_L
SPI_CS3_L/GBE_STAT1/GEVENT21_L
SLP_S3_L
SLP_S5_L
PWR_BTN_L
PWR_GOOD
SUS_STAT_L
TEST0
TEST1/TMS
TEST2
GA20IN/GEVENT0_L
KBRST_L/GEVENT1_L
LPC_PME_L/GEVENT3_L
LPC_SMI_L/GEVENT23_L
GEVENT5_L
SYS_RESET_L/GEVENT19_L
WAKE_L/GEVENT8_L
IR_RX1/GEVENT20_L
THRMTRIP_L/SMBALERT_L/GEVENT2_L
NB_PWRGD

10K_0402_5%
1
2
R594

R579 1

20100810

USB 1.1

+3VALW

J2
K1
D3
F1
H1
F2
FCH_PWRGD H5
G6
B3
T82PAD
C4
T83PAD
F6
T84PAD
AD21
AE21
K2
J29
H2
J1
H6
F3
J6
NB_PWRGD
AC19

(31) PCI_PME#
(46) Kill_SW#

(31)
(31)
(31)
(31)

LAN_CLKREQ#
2
10K_0402_5%
WLAN_CLKREQ#
2
10K_0402_5%
NB_PWRGD
2
4.7K_0402_5%
FCH_SMCLK0
2
2.2K_0402_5%
FCH_SMDAT0
2
2.2K_0402_5%

1
R817
1
R818
1
R597
1
R598
1
R599

USB_OC7#
2
10K_0402_5%
EC_LID_OUT#
2
10K_0402_5%
USB_OC5#
2
10K_0402_5%
ODD_DA#_FCH
2
10K_0402_5%
ODD_DETECT#
2
10K_0402_5%

2.2K_0402_5%
2
1
R601

USB MISC

+3VS

1
R929
1
R930
1
R931
1
R932
1
R933

ACPI/WAKE UP EVENTS

USB_OC2#
2
10K_0402_5%
USB_OC1#
2
10K_0402_5%
USB_OC0#
2
10K_0402_5%
FCH_SIC
2
10K_0402_5%
FCH_SID
2
10K_0402_5%
FCH_PCIE_WAKE#
2
10K_0402_5%

1
R870
1
R871
1
R872
1
R603
1
R604
1
R605

ROM TYPE

SPI ROM

UMA

Reserved

DIS

Reserved

PX3

LPC ROM

PX4

2010/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

w/o HDMI
B

Title

FCH HDA/USB/ACPI
Size Document Number
Custom
Date:

Rev
1.0

LA6755P/7P

Tuesday, November 30, 2010

Sheet
E

14

of

48

U26B

HDD

C726
C727

(29) SATA_ITX_DRX_P0
(29) SATA_ITX_DRX_N0

SATA_ITX_C_DRX_P0 AH9
SATA_ITX_C_DRX_N0 AJ9

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

1
1

(29) SATA_DTX_C_IRX_N0
(29) SATA_DTX_C_IRX_P0

ODD

C728
C729

(46) SATA_ITX_DRX_P1
(46) SATA_ITX_DRX_N1

SATA_TX2P
SATA_TX2N

AJ12
AH12

SATA_RX2N
SATA_RX2P

AH14
AJ14

SATA_TX3P
SATA_TX3N

AG14
AF14

SATA_RX3N
SATA_RX3P

ESATA@

(33) SATA_DTX_C_IRX_N2
(33) SATA_DTX_C_IRX_P2

SATA_RX1N
SATA_RX1P

AG17
AF17

SATA_TX4P
SATA_TX4N

AJ17
AH17

SATA_RX5N
SATA_RX5P

10 mils and < 1"


SATA_CALRP
SATA_CALRN

2 1K_0402_1%
2 931_0402_1%

1
1

AB14
AA14

SATA_CALRP
SATA_CALRN

AD11

(46) HDD_LED#
R616 1

@ C980
22P_0402_50V8J
@ C981
22P_0402_50V8J
1
2

25M_SATA_X1 AD16

1M_0603_5%
R861

25M_SATA_X2 AC16

SATA_X2

SPI_SO_R
SPI_SI_R
SPI_CLK_FCH_R
SPI_SB_CS0#_R
GPIO161

T87 PAD

J5
E2
K4
K9
G2

SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1_L/GPIO165
ROM_RST_L/GPIO161

SPI ROM

25MHZ_20PF_7A25000012

FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58

VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182

SATA_X1

@
Y7

FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54

TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT_L/GPIO174
TEMP_COMM

SATA_ACT_L/GPIO67

2 10K_0402_5%

+3VS

HW MONITOR

SATA_TX5P
SATA_TX5N

AH19
AJ19
R610
R611

FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143

SATA_RX4N
SATA_RX4P

AJ18
AH18

+1.1VS

GPIOD

1
1

SATA_ITX_C_DRX_P2 AG12
SATA_ITX_C_DRX_N2 AF12

SERIAL ATA

(33) SATA_ITX_DRX_P2
(33) SATA_ITX_DRX_N2

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

FC_OE_L/GPIOD145
FC_AVD_L/GPIOD146
FC_WE_L/GPIOD148
FC_CE1_L/GPIOD149
FC_CE2_L/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147

SATA_TX1P
SATA_TX1N

AG10
AF10

ESATA@

C730
C731

FC_CLK
FC_FBCLKOUT
FC_FBCLKIN

SATA_RX0N
SATA_RX0P

SATA_ITX_C_DRX_P1 AH10
SATA_ITX_C_DRX_N1 AJ10

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

1
1

(46) SATA_DTX_C_IRX_N1
(46) SATA_DTX_C_IRX_P1

eSATA

SATA_TX0P
SATA_TX0N

AJ8
AH8

NC1
NC2

AH28
AG28
AF26
AF28
AG29
AG26
AF27
AE29
AF29
AH27
AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26

W5
W6
Y9

ODD_EN (29)
BT_OFF# (33)

W7
V9
W8

WL_OFF# (30)

B6
A6
A5
B5
C7

TEMPIN0 R612 2
TEMPIN1 R613 2
TEMPIN2 R614 2
R615 2

1
1
1
1

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

A3
B4
A4
C5
A7
B7
B8
A8

GPIO175
GPIO176
GPIO177
GPIO178
GPIO179
GPIO180
GPIO181
GPIO182

1
1
1
1
1
1
1
1

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

APU_ALERT#_FCH (5)
R617
R618
R619
R620
R621
R622
R623
R624

2
2
2
2
2
2
2
2

VIN6/GBE_STAT3/GPIO181
Enable integrated pull-down/up and leave unconnected

G27
Y2

21807-A11-HUDSON-M1_FCBGA605

2MB SPI ROM


& Non-share ROM.

SPI_CLK_FCH

+3VS

2 SPI_WP#
3.3K_0402_5%

R627 1

2 SPI_HOLD#
3.3K_0402_5%

R625
33_0402_5%
@
R626 1

+3VS

R628
0_0402_5%
SPI_SB_CS0#_R 1
2
SPI_SO_R
1
2

SPI_SB_CS0#1
SPI_SO_L
2
SPI_WP#
3
33_0402_5%
4
R629

U28
CS#
SO
WP#
GND

0.1U_0402_16V4Z
VCC
HOLD#
SCLK
SI

8
7
6
5

SPI_HOLD#
0_0402_5% R631
SPI_CLK_FCH 1
2 SPI_CLK_FCH_R
SPI_SI
1
2 SPI_SI_R

MX25L1605AM2C-12G_SO8

SA00003FO00
SA00002KI00
A

C732
22P_0402_50V8J
@

C733
1
2

33_0402_5%
R630

2010/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

Title

FCH-SATA/SPI
Size Document Number
Custom
Date:

Rev
1.0

LA6755P/7P

Tuesday, November 30, 2010

Sheet
E

15

of

48

VDDRF_GBE_S

FBMA-L11-201209-221LMA30T_0805

C742

+
2

10U_0603_6.3V6M

22U_0805_6.3V6M

C743

C752

1U_0402_6.3V6K

C741

1
Change from SM010014520 to SD002000080
20101012
L43
2
1
+1.1VS

330U_D2_2.5VY_R9M

10U_0603_6.3V6M

C748

C740

1U_0402_6.3V6K

1U_0402_6.3V6K

C747

C738

C739
C751

1U_0402_6.3V6K

L7
L9

VDDIO_GBE_S_1
VDDIO_GBE_S_2

M6
P8

+VDDAN_11_USB C11
D11

+VDDCR_11_USB

46.5mA
VDDPL_33_SYS
VDDPL_11_SYS_S
VDDPL_33_USB_S

VDDAN_11_USB_S_1
VDDAN_11_USB_S_2

VDDAN_33_HWM_S
VDDXL_33_S

88.6mA

M21

+VDDPL33

65.3mA
L22

+VDDPL11

16.1mA
F19

L47
2
1
FBMA-L11-201209-221LMA30T_0805

+1.1VALW

0_0805, no bead needed for this rail


2010/07/04

+AVDD_USB

11.4mA
D6

+VDDAN33_HWM

L49

+VDDXL_33_S

L20

C769

10U_0603_6.3V6M

+1.1VALW

C768

+VDDIO_AZ

58mA
A11
B11

0.1U_0402_16V7K

VDDCR_11_USB_S_1
VDDCR_11_USB_S_2

15.3mA
M8

+3VALW

0.1U_0402_16V7K

VDDIO_AZ_S

165.2mA

C759

F26
G26

2.2U_0603_6.3V6K

VDDCR_11_S_1
VDDCR_11_S_2

C767

VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12

A21
D21
B21
K10
L10
J9
T6
T8

C761

A18
A19
A20
B18
B19
B20
C18
C20
D18
D19
D20
E19

49.5mA
VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8

1U_0402_6.3V6K

0.1U_0402_16V7K

C766

534.5mA

0.1U_0402_16V7K

C770

FBMA-L11-160808-221LMT_2P

+1.1VS

M10

VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2

PLL

change from SM01000CB00 to SD013000080


20101012
L48
2
1
+1.1VALW

C771

C765

1U_0402_6.3V6K

2.2U_0603_6.3V6K

C764

1U_0402_6.3V6K

10U_0603_6.3V6M

C763

10U_0603_6.3V6M

C762

VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7

USB I/O

+AVDD_USB

VDDPL_33_SATA

AJ20
AF18
AH20
AG19
AE18
AD18
AE16

CORE S5

FBMA-L11-201209-221LMA30T_0805

+1.1VS

V1

C758

1354.2mA

Change from SM010014520 to SD002000080


20101012
L46
2
1
+3VALW

15.5mA
+VDDPL_33_SATA AD14
+AVDD_SATA

VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8

C760

2.2U_0603_6.3V6K

C757

U26
V22
V26
V27
V28
V29
W22
W26

1U_0402_6.3V6K

+PCIE_VDDAN
0.1U_0402_16V7K

C753
2

0.1U_0402_16V7K

C756

1U_0402_6.3V6K

C754

2
1
FBMA-L11-201209-221LMA30T_0805

C755

L45

22U_0805_6.3V6M

+1.1VS

1115.6mA

3.3V_S5 I/O

VDDPL_33_PCIE

GBE LAN

AE28

SERIAL ATA

Change from SM010014520 to SD002000080


20101012

+VDDPL33_PCIE

+VDDAN_11_CLK

K28
K29
J28
K26
J21
J20
K21
J22

C750

VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8

VDDIO_33_GBE_S

PCI EXPRESS

2
1
FBMA-L11-160808-221LMT_2P

+3VS

382.9mA

22.5mA
L44

0.1U_0402_16V7K

VDDIO_18_FC_1
VDDIO_18_FC_2
VDDIO_18_FC_3
VDDIO_18_FC_4

2.2U_0603_6.3V6K

AF22
AE25
AF24
AC22

5mA

21807-A11-HUDSON-M1_FCBGA605

2.2U_0603_6.3V6K

0.16mA

C772

C746

0.1U_0402_16V7K

0.1U_0402_16V7K

C745

C744

4.7U_0603_6.3V6K

1
R633
2

FLASH I/O

N13
R15
N17
U13
U17
V12
V18
W12
W18

0.1U_0402_16V7K

979.4mA
VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9

C749

VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10
VDDIO_33_PCIGP_11
VDDIO_33_PCIGP_12

0.1U_0402_16V7K

0.1U_0402_16V7K

C737

C736

C735

C1007

0.1U_0402_16V7K

POWER

U26C
AH1
V6
Y19
AE5
AC21
AA2
AB4
AC8
AA7
AA9
AF7
AA19

+VDDIO_18_FC

2
0_0603_5%

0_0402_5%

C1006

0.1U_0402_16V7K

CLKGEN I/O

R632
1

GPIO I/F implemented: tied to +1.8V_S0


GPIO I/F not implemented: tied to
+1.8V_S0 or 0 ohm to ground

+1.8VS

10U_0603_6.3V6M

42mA
2

CORE S0

PCI/GPIO I/O

10U_0603_6.3V6M

+3VS

0.1U_0402_16V7K

ME limitation, change one 22u_0805 to two 10u_0603


20101006

+3VS

FBMA-L11-160808-221LMT_2P

Change from SM010014520 to SD002000080


20101012

L53
2
1
FBMA-L11-160808-221LMT_2P
HWM@

2 2.2U_0603_6.3V6K
HWM@ C781

C780 1
4

L53
+VDDPL33
L55
+3VS

2
1
FBMA-L11-160808-221LMT_2P
C783 1

2 2.2U_0603_6.3V6K

C775

C778

C776

+3VALW

1
R634

0_0603_5%

C779
2.2U_0603_6.3V6K

For 3V AZ device

Compal Electronics, Inc.

Compal Secret Data


2010/06/30

Issued Date

SD013000080

Security Classification

0_0603_5%

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

nonHWM@

+VDDIO_AZ

+VDDAN33_HWM
+3VALW

C782

L52
2
1
FBMA-L11-160808-221LMT_2P

2.2U_0603_6.3V6K

+VDDPL11
+1.1VALW

0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K

2 2.2U_0603_6.3V6K

C774

C777 1

1U_0402_6.3V6K

2
1
FBMA-L11-160808-221LMT_2P

L50
2
1
FBMA-L11-201209-221LMA30T_0805
C773

+3VS

+1.1VS

0.1U_0402_16V7K

L51

22U_0805_6.3V6M

+AVDD_SATA
+VDDPL_33_SATA

Title

FCH PWR
Size Document Number
Custom
Date:

Rev
1.0

LA6755P/7P

Tuesday, November 30, 2010

Sheet
E

16

of

48

U26D

VSSXL

P21
P20
M22
M24
M26
P22
P24
P26
T20
T22
T24
V20
J23

VSSIO_PCIECLK_1
VSSIO_PCIECLK_2
VSSIO_PCIECLK_3
VSSIO_PCIECLK_4
VSSIO_PCIECLK_5
VSSIO_PCIECLK_6
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_11
VSSIO_PCIECLK_12
VSSIO_PCIECLK_13

VSSPL_SYS

LPC_CLK0 CLK_PCI_DB

ALLOW PCIE
GEN2

USE
DEBUG
STRAP

Reserved

internal EC
ENABLE

Internal
CLKGEN
Mode

DEFAULT
DEFAULT

IGNORE
DEBUG
STRAP

Internal

DEFAULT

DEFAULT

External
CLKGEN
Mode

DEFAULT

+3VS +3VALW +3VALW

R805
10K_0402_5%
2
1

+3VS

R638
10K_0402_5%
2
1

+3VS

internal EC
DISABLE

CLKGEN Mode

R639
10K_0402_5%
2
1

FORCE PCIE
GEN1

PULL
LOW

(13)
PCI_CLK1
(13)
PCI_CLK3
(13)
PCI_CLK4
(13)
LPCCLK0
(13) CLK_PCI_DB_R

R806
10K_0402_5%
2
1

VSSAN_HWM

M19

PCI_CLK4

R643
10K_0402_5%
2
1

EFUSE

PCI_CLK3

R642
10K_0402_5%
2
1

Y4
D8

PULL
HIGH

Check Internal PU/PD

PCI_CLK1

R637
10K_0402_5%
2
1

VSSIO_USB_1
VSSIO_USB_2
VSSIO_USB_3
VSSIO_USB_4
VSSIO_USB_5
VSSIO_USB_6
VSSIO_USB_7
VSSIO_USB_8
VSSIO_USB_9
VSSIO_USB_10
VSSIO_USB_11
VSSIO_USB_12
VSSIO_USB_13
VSSIO_USB_14
VSSIO_USB_15
VSSIO_USB_16
VSSIO_USB_17
VSSIO_USB_18
VSSIO_USB_19
VSSIO_USB_20
VSSIO_USB_21
VSSIO_USB_22
VSSIO_USB_23
VSSIO_USB_24
VSSIO_USB_25
VSSIO_USB_26
VSSIO_USB_27
VSSIO_USB_28

REQUIRED STRAPS

AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8

R636
10K_0402_5%
2
1

A9
B10
K11
B9
D10
D12
D14
D17
E9
F9
F12
F14
F16
C9
G11
F18
D9
H12
H14
H16
H18
J11
J19
K12
K14
K16
K18
H19

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52

GND

VSSIO_SATA_1
VSSIO_SATA_2
VSSIO_SATA_3
VSSIO_SATA_4
VSSIO_SATA_5
VSSIO_SATA_6
VSSIO_SATA_7
VSSIO_SATA_8
VSSIO_SATA_9
VSSIO_SATA_10
VSSIO_SATA_11
VSSIO_SATA_12
VSSIO_SATA_13
VSSIO_SATA_14
VSSIO_SATA_15
VSSIO_SATA_16
VSSIO_SATA_17
VSSIO_SATA_18
VSSIO_SATA_19

R640
10K_0402_5%
2
1

Y14
Y16
AB16
AC14
AE12
AE14
AF9
AF11
AF13
AF16
AG8
AH7
AH11
AH13
AH16
AJ7
AJ11
AJ13
AJ16

R641
10K_0402_5%
2
1

M20

H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20

DEBUG STRAPS
FCH M1 HAS 15K INTERNAL PU FOR PCI_AD[27:23]

ILA AUTORUN Selects


Disabled
FC PLL

Disable I2C
ROM

DEFAULT

DEFAULT

DEFAULT

Required Setting

DEFAULT

(13)
(13)
(13)
(13)
(13)

PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23

21807-A11-HUDSON-M1_FCBGA605

PULL
LOW

BYPASS
PCI PLL

ILA
AUTORUN
Enabled

FC PLL
bypassed

Getting Value
from I2C EPROM

Reserved

Check AD29,AD28 strap function

Issued Date

2010/06/30

Deciphered Date

Compal Electronics, Inc.


2012/06/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

check default
Compal Secret Data

Security Classification

R648
2.2K_0402_5%
2
1

DEFAULT

PCI_AD23
Enable ROM Straps

PCI_AD24

R647
2.2K_0402_5%
2
1

USE internal
PLL generated
PLL CLK

PCI_AD25

R646
2.2K_0402_5%
2
1

PULL
HIGH

PCI_AD26

R645
2.2K_0402_5%
2
1

PCI_AD27

R644
2.2K_0402_5%
2
1

VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
VSSIO_PCIECLK_17
VSSIO_PCIECLK_18
VSSIO_PCIECLK_19
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
VSSIO_PCIECLK_25
VSSIO_PCIECLK_26
VSSIO_PCIECLK_27

FCH-VSS/Strap
Size
B
Date:

Document Number

Rev
1.0

LA6755P/7P
Tuesday, November 30, 2010

Sheet
1

17

of

48

PCIE_CTX_GRX_P[3..0]

(6) PCIE_CTX_GRX_P[3..0]

PCIE_CRX_GTX_P[3..0]

U8A

PCIE_CTX_GRX_N[3..0]

(6) PCIE_CTX_GRX_N[3..0]

PCIE_CRX_GTX_P[3..0] (6)

PCIE_CRX_GTX_N[3..0]

U8F

PCIE_CRX_GTX_N[3..0] (6)
LVDS CONTROL

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0

PCIE_TX0P
PCIE_TX0N

AH30 PCIE_CRX_C_GTX_P0 0.1U_0402_10V7K


AG31 PCIE_CRX_C_GTX_N0 0.1U_0402_10V7K

2
2

1 C273 PX@
1 C272 PX@

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

AF30
AE31

PCIE_RX0P
PCIE_RX0N

PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1

AE29
AD28

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

AG29 PCIE_CRX_C_GTX_P1 0.1U_0402_10V7K


AF28 PCIE_CRX_C_GTX_N1 0.1U_0402_10V7K

2
2

1 C274 PX@
1 C275 PX@

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2

AD30
AC31

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

AF27 PCIE_CRX_C_GTX_P2 0.1U_0402_10V7K


AF26 PCIE_CRX_C_GTX_N2 0.1U_0402_10V7K

2
2

1 C276 PX@
1 C277 PX@

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3

AC29
AB28

PCIE_TX3P
PCIE_TX3N

AD27 PCIE_CRX_C_GTX_P3 0.1U_0402_10V7K


AD26 PCIE_CRX_C_GTX_N3 0.1U_0402_10V7K

2
2

1 C278 PX@
1 C279 PX@

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

PCIE_RX3P
PCIE_RX3N

AB30
AA31

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

AC25
AB25

AA29
Y28

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

Y23
Y24

Y30
W31

PCIE_RX6P
PCIE_RX6N

PCIE_TX6P
PCIE_TX6N

AB27
AB26

W29
V28

PCIE_RX7P
PCIE_RX7N

PCIE_TX7P
PCIE_TX7N

Y27
Y26

V30
U31

PCIE_RX8P
PCIE_RX8N

PCIE_TX8P
PCIE_TX8N

W24
W23

U29
T28

PCIE_RX9P
PCIE_RX9N

PCIE_TX9P
PCIE_TX9N

V27
U26

T30
R31

PCIE_RX10P
PCIE_RX10N

PCIE_TX10P
PCIE_TX10N

U24
U23

R29
P28

PCIE_RX11P
PCIE_RX11N

PCIE_TX11P
PCIE_TX11N

T26
T27

P30
N31

PCIE_RX12P
PCIE_RX12N

PCIE_TX12P
PCIE_TX12N

T24
T23

N29
M28

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

P27
P26

M30
L31

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

P24
P23

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

M27
N26

VARY_BL
DIGON

AB11
AB12

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

AH20
AJ19

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

AL21
AK20

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

AH22
AJ21

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

AL23
AK22

TXOUT_U3P
TXOUT_U3N

AK24
AJ23

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

AL15
AK14

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

AH16
AJ15

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

AL17
AK16

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

AH18
AJ17

TXOUT_L3P
TXOUT_L3N

AL19
AK18

LVDS
B

0.1U_0402_16V4Z
2

PX@
C1003
1

+3VGS

PX_RST#

(13)

PE_GPIO0

CLK_PCIE_VGA
CLK_PCIE_VGA#
R936
1

CALIBRATION

2 R299 PX@
1
10K_0402_5%

N10

GPU_RST#

AL27

PWRGOOD

PCIE_CALRP

Y22 1.27K_0402_1% 1 PX@

2 R298

PCIE_CALRN

AA22

2K_0402_5% 1 PX@

2 R300

1 @
R956
+1.0VGS

PERSTB

GPU_RST#

R957
100K_0402_5%
PX@

PX@

Issued Date

2
0_0603_5%

update for PX function


20100811

Compal Electronics, Inc.

Compal Secret Data

Security Classification
216-0774207-A11ROB_FCBGA631

Y
A

U48
4

NC7SZ08P5X_NL_SC70-5

20100728
0_0402_5%
@
2

update for PX function


20100811

PCIE_REFCLKP
PCIE_REFCLKN

(20,40,43) VGA_PWRGD

AK30
AK32

PX@

CLOCK
(13) CLK_PCIE_VGA
(13) CLK_PCIE_VGA#

(13)

L29
K30

216-0774207-A11ROB_FCBGA631
PX@

PCI EXPRESS INTERFACE

LVTMDP

2010/06/30

Deciphered Date

2012/06/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

RobsonXT-S3 PCIE/LVDS
Size
B
Date:

Document Number

Rev
1.0

LA6755P/7P
Tuesday, November 30, 2010

Sheet
1

18

of

48

Transmitter Power Saving Enable


GPIO0 0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)

TX_DEEMPH_EN

PCI Express Transmitter De-emphasis Enable


GPIO1 0: Tx de-emphasis diabled for mobile mode
1: Tx de-emphasis enabled (Defailt setting for desktop)

AE8
AD9
AC10
AD7
AC8
AC7
AB9
AB8
AB7
AB4
AB2
Y8
Y7

0.1U_0402_10V6K

1U_0402_6.3V4Z
C306
PX@

C304
PX@

10U_0603_6.3V6M
C305
@

150mA
1

(24)
(24)
(24)

VRAM_ID2
VRAM_ID1
VRAM_ID0

TXCAP_DPA3P
TXCAM_DPA3N
DVCLK
DVCNTL_0
DVCNTL_1
DVCNTL_2

DVO

TX0P_DPA2P
TX0M_DPA2N

DPA

TX1P_DPA1P
TX1M_DPA1N

DVDATA_12
DVDATA_11
DVDATA_10
DVDATA_9
DVDATA_8
DVDATA_7
DVDATA_6
DVDATA_5
DVDATA_4
DVDATA_3
DVDATA_2
DVDATA_1
DVDATA_0

TX2P_DPA0P
TX2M_DPA0N
TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N

DPB

TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N

+1.0VGS

+DPC_VDD18

W6
V6

+DPC_VDD18

AC6
AC5

+DPC_VDD10

AA5
AA6

+DPC_VDD10

C307
PX@

0.1U_0402_10V6K

110mA
1U_0402_6.3V4Z
C309
PX@

PX@
2
1
BLM15BD121SN1D_0402

10U_0603_6.3V6M
C308
@

L9

Internal pull down

DPC_VDD18#1
DPC_VDD18#2

TX0P_DPC2P
TX0M_DPC2N

DPC_VDD10#1
DPC_VDD10#2

DPC_VSSR#1
DPC_VSSR#2
DPC_VSSR#3
DPC_VSSR#4
DPC_VSSR#5

TX2P_DPC0P
TX2M_DPC0N
DPC_CALR

PIN

TX_PWRS_ENB

GPIO0

PCIE FULL TX OUTPUT SWING

AK3
AK1

TX_DEEMPH_EN

GPIO1

PCIE TRANSMITTER DE-EMPHASIS ENABLED

AK5
AM3

RSVD

GPIO2

0 : 2.5GT/s ; 1 : 5.0GT/s, internal PD.

AK6
AM5

RSVD

GPIO8

RESERVED

AJ7
AH6

BIF_VGA DIS

GPIO9

VGA ENABLED

AK8
AL7

RSVD

GPIO21

RESERVED

BIOS_ROM_EN

GPIO_22_ROMCSB

ENABLE EXTERNAL BIOS ROM

ROMIDCFG(2:0)

GPIO[13:11]

SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

000

V2SYNC

IGNORE VIP DEVICE STRAPS

V4
U5
W3
V2

VIP_DEVICE_STRAP_ENA
RSVD

H2SYNC

AA3
Y2

RSVD

GENERICC

AUD[1]

HSYNC

AUD[0]

VSYNC

J8

R305 1 PX@
2
150_0402_1%

R321
R322
R323
R324

2
2
2
2

10K_0402_5% GPIO24_TRSTB
GPIO25_TDI
10K_0402_5%
GPIO27_TMS
10K_0402_5%
10K_0402_5%
GPIO26_TCK
R326 2 PX@

GPIO24_TRSTB
L6
GPIO25_TDI
L5
GPIO26_TCK
L3
GPIO27_TMS
L1
T64
GPIO28_TDO
K4
1 10K_0402_5% TEST_EN
K7
T65
AF24

AB13
W8
W9
W7
AD10

R905 PX@
1
2
4.7K_0402_5%
(20)
+1.8VGS

AC14
AB16

PX_EN

R2
R2B
G2
G2B

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
TESTEN
TESTEN_LEGACY
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4

B2
B2B
C
Y
COMP

+1.0VGS

0.1U_0402_10V6K

1U_0402_6.3V4Z
C325
PX@

C323
PX@

10U_0603_6.3V6M
C324
PX@

H2SYNC
V2SYNC
VDD2DI
VSS2DI

HPD1
PX_EN

0.60 V level, Please


VREFG Divider ans
cap close to ASIC

+1.8VGS
R329 2 PX@

1 499_0402_1% +VREFG_GPU

DDC/AUX
PLL/CLOCK
AF14
AE14

+DPLL_PVDD

XTALIN
Voltage Swing: 1.8 V
PX@
PX@

0.1U_0402_16V4Z

1U_0402_6.3V4Z
C336
@

C334
@

10U_0603_6.3V6M
C335
@

2 R332
2 R333

XTALIN
XTALOUT

AM28
AK28

1 0_0402_5% AC22
1 0_0402_5% AB22

DPLL_PVDD
DPLL_PVSS

DDC1CLK
DDC1DATA
AUX1P
AUX1N

DPLL_VDDC

DDC2CLK
DDC2DATA

XTALIN
XTALOUT

AUX2P
AUX2N

XO_IN
XO_IN2

DDCCLK_AUX3P
DDCDATA_AUX3N
DDCCLK_AUX5P
DDCDATA_AUX5N

Chnge from SM010030010 to SD013000080


since EVT 20101012
+1.8VGS
+TSVDD
L17 PX@
20mA
2
1
BLM18AG121SN1D_0603
1
1
1

AD14

+DPLL_VDDC

0.1U_0402_10V6K

1U_0402_6.3V4Z
C332
PX@

C330
PX@

VREFG
R2SET

125mA
10U_0603_6.3V6M
C331
PX@

2
1
BLM15BD121SN1D_0402

A2VSSQ

2 PX@
1
R331
249_0402_1%
2
1
C322
0.1U_0402_10V6K
PX@

+DPLL_VDDC
L16 PX@

A2VDDQ

AC16

GPU_THERMAL_D+
GPU_THERMAL_DR334
XTALOUT

PX@
R337
1M_0603_5%

XTALIN

+3VGS 1 PX@
+TSVDD

2.61K_0402_5%
2 TS_FDO

T4
T2
R5
AD17
AC17

DPLUS
DMINUS

1U_0402_6.3V4Z
C312
PX@

10U_0603_6.3V6M

THERMAL

DDC6CLK
DDC6DATA

PX@
1

PX@
1

110mA

AL11
AJ11
AK10
AL9
AH12
AM10
AJ9

C338
18P_0402_50V8J
PX@

R309
R310
R311
R308

2 PX@
2 PX@
@
2
@
2

GPU_GPIO8
GPU_GPIO9

R313
R314

2
2

GPU_GPIO11 R315
GPU_GPIO12 R316
GPU_GPIO13 R317

2 PX@
@
2
@
2

1 10K_0402_5%
1 10K_0402_5%
1 10K_0402_5%

+3VGS
+1.8VGS
PX@
1

2mA

AL13
AJ13
AD19
AC19

+VDD2DI

AE20

+A2VDD

AE17

+A2VDDQ

+A2VDD

AE19

PX@
1

100mA
R330 1 PX@

Change footprint
20100812

L12
2
BLM15BD121SN1D_0402
VGA_SMB_CK2_R

EC_SMB_CK2

(5,29,31)

EC_SMB_DA2

(5,29,31)

2N7002KDWH_SOT363-6
Q64A
PX@

2
715_0402_1%

AE6
AE5

AD2
AD4

+3VGS
L13
2
BLM15BD121SN1D_0402

VGA_SMB_DA2_R

2N7002KDWH_SOT363-6
Q64B
PX@

+3VGS

AC11
AC13

+A2VDDQ

AD13
AD11
AD20
AC20
AE16
AD16

Need to change back to 1402-1 after BIOS confirm!!!

+1.8VGS
PX@
1

130mA
1

L15
C329
0.1U_0402_16V4Z
PX@

2
BLM15BD121SN1D_0402

VGA Thermal Sensor


ADM1032 Closed to GPU

U9
1

AC1
AC3

GPU_THERMAL_D+

PX@ 1
2
C333
2200P_0402_50V7K
GPU_THERMAL_D-

+3VGS

TS_FDO
TSVDD
TSVSS

1 R335
2
4.7K_0402_5%
PX@

VDD

SCLK

D+

SDATA

D-

ALERT#

THERM#

GND

VGA_SMB_CK2_R

VGA_SMB_DA2_R

6
THM_ALERT#

EMC1402-2-ACZL-TR MSOP 8P
PX@

2 R336
1
4.7K_0402_5%

+3VGS

PX@

EMC1412-A (SA00003YA00)
Address 1111_100xb
S IC EMC1412-A-ACZL-TR MSOP 8P SENSOR

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
PX@

2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SD028100280
20100722 for future ASIC

Title
Size
C
Date:

@
@

1 10K_0402_5%
1 10K_0402_5%
1 10K_0402_5%
1 10K_0402_5%
20100728
1 10K_0402_5%
1 10K_0402_5%

L11
2
BLM15BD121SN1D_0402

+VDD2DI

10K_0402_5%

+3VGS

GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
GPU_GPIO5

216-0774207-A11ROB_FCBGA631

27MHZ_16PF_X5H027000FG1H
C337
18P_0402_50V8J
PX@

11

GPIO8

STRAPS

R334
Y3

GPIO2

+1.8VGS

AM12
AK12

AG13

GENERICC

+VDD1DI

DAC2

A2VDD

75mA

H2SYNC

+1.8VGS
L10
2
BLM15BD121SN1D_0402

+VDD1DI

+DPLL_PVDD

L14 PX@
2
1
BLM15BD121SN1D_0402

0
AUD[1] AUD[0]
0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected
1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI

1
1
1
1

1U_0402_6.3V4Z
C315
PX@

PX@
PX@
PX@
PX@

+AVDD

10U_0603_6.3V6M

(14) PEG_CLKREQ#

+3VGS

AE23
AD23

2 499_0402_1%

1U_0402_6.3V4Z
C318
PX@

GPU_VID1

VDD1DI
VSS1DI

R312 1 PX@

AG24
AE22

PX@
1

65mA

10U_0603_6.3V6M

(43)

2 10K_0402_5%

AD22

+AVDD

1 10K_0402_5%
1 10K_0402_5%

1U_0402_6.3V4Z
C321
PX@

THM_ALERT#
R319 1 PX@

AVDD
AVSSQ

R945 2 @
R946 2 @

10U_0603_6.3V6M

T63

For HDMI Audio strap

AH26
AJ27

1U_0402_6.3V4Z
C328
PX@

GPU_VID0

RSET

AH24
AG25

10U_0603_6.3V6M

(43)

HSYNC
VSYNC

C310
PX@

GPU_GPIO11
GPU_GPIO12
GPU_GPIO13

B
BB

DAC1

GPIO21

+3VGS

0.1U_0402_10V6K
C311
PX@

VGA_ENBKL
GPU_GPIO8
GPU_GPIO9

AL25
AJ25

C313
PX@

GPU_GPIO5

RB751V_SOD323

G
GB

0.1U_0402_10V6K
C314
PX@

@
D3 1

ACIN

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB

C316
PX@

U6
U10
T10
U8
U7
T9
T8
T7
P10
P4
P2
N6
N5
N3
Y9
N1
M4
R6
W10
M2
P8
P7
N8
N7

ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL
RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND
NOT CONFLICT DURING RESET If we meet some issue on bring up, we can check this item during reset.

AM26
AK26

0.1U_0402_10V6K
C317
PX@

GPU_GPIO0
GPU_GPIO1
GPU_GPIO2

(31,38)

R
RB

GENERAL PURPOSE I/O

VGA_ENBKL

AMD RESERVED CONFIGURATION STRAPS

SCL
SDA

C319
PX@

2 10K_0402_5%

R1
R3

0.1U_0402_10V6K
C320
PX@

R826 1

VGA_SMB_CK2_R
VGA_SMB_DA2_R

DESCRIPTION OF DEFAULT SETTINGS

Y4
W5

C326
PX@

VGA_SMB_CK2_R
VGA_SMB_DA2_R

2 4.7K_0402_5%
2 4.7K_0402_5%

RECOMMENDED
SETTINGS

STRAPS

AH3
AH1

0.1U_0402_10V6K
C327
PX@

PX@

R306 1
R307 1

RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE

AG3
AG5

I2C
PX@
PX@

TXCCP_DPC3P
TXCCM_DPC3N

TX1P_DPC1P
TX1M_DPC1N
U1
W1
U3
Y6
AA1

AF2
AF4

DPC

DPC_PVDD
DPC_PVSS

+3VGS

CONFIGURATION STRAPS

Y11
AE9
L9
N9

+DPC_VDD18

L8 PX@
2
1
BLM15BD121SN1D_0402

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE


GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

change from SM010009U00 to SD028000080


20101012
+1.8VGS

U8B

TX_PWRS_ENB

RobsonXT-S3 Main Generic/MSIC


Document Number
Rev
LA6755P/7P
1.0
Tuesday, November 30, 2010
1

Sheet

19

of

48

update for BACO circuit


20100930
+3VS +3VGS

1
5

2
1
@ C987
0.1U_0402_10V6K

update for BACO circuit


20100930

1
+3VGS

BACO@
R338
2
1
10K_0402_5%
1
Change footprint
20100812

D29 BACO@
1

Q67
2N7002H_SOT23-3
BACO@
Change footprint
20100812

PE_GPIO1

PE_GPIO1 (13,21,43)

RB751V_SOD323
C988
1U_0603_10V4Z
@

Need to pop for BACO function


Should unpop for PX3.0
20100728

Change Part number to SB000007600 (3414)


201009028

PX_MODE (21,43)

BACO@

BACO@

Q69
BSS138_NL_SOT23-3

2
R888
0_0402_5%
@

Q70
BSS138_NL_SOT23-3

+1.0VGS

+BIF_VDDC
D

BOM structure update for BACO circuit


20100928

2
0.1U_0402_10V6K

+VGA_CORE

Q66
2
2N7002H_SOT23-3 G
BACO@

PX_MODE_AND
1
NC7SZ08P5X_NL_SC70-5 A
U44
BACO@

2
G

RUNPWROK

2
R904 BACO@
0_0402_5%

BACO@
R903
20K_0402_5%

@
C986 1

Y
G

@ U46
SN74LVC1G07DCKR_SC70-5

RUNPWROK

VDDC_ON
1.0V_ON

Need to pop for BACO function


Should unpop for PX3.0
20101123

NC

BACO@
R339
2
1
10K_0402_5%
1

update for BACO circuit


20100930
+3VGS

Change footprint
20100812

PX_MODE
1
NC7SZ08P5X_NL_SC70-5 A
BACO@ U10

Q68
2N7002H_SOT23-3
BACO@

C989
0.1U_0402_10V6K
@

0.1U_0402_10V6K

C339 BACO@

PX_EN: High >>> BACO mode


Low >>> Normal Operation

1
2
0_0402_5%
@

+5VS

2
G

PX_EN

R906

(19)

(18,40,43) VGA_PWRGD

R907
10K_0402_5%
BACO@

R340
10K_0402_5%
@
PX_MODE_AND

+5VS
+3VGS

3
BACO@

Q72
BSS138_NL_SOT23-3
S

BACO@ C343

Q71
BSS138_NL_SOT23-3
+VGA_CORE
1

2
R342
0_0402_5%
PX3@

2
G

VDDC_ON

2
1
R917
0_0402_5% 1

BACO@

0.1U_0402_10V6K

BACO@

2
G

1.0V_ON

20100728

Need to pop for BACO function


Should unpop for PX3.0
20100728

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/06/30

Deciphered Date

2012/06/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

RobsonXT-S3 BACO
Size
B
Date:

Document Number

Rev
1.0

LA6755P/7P
Tuesday, November 30, 2010

Sheet
1

20

of

48

+VGA_PCIE TO +1.0VGS

+3.3VS TO +3.3VGS

+1.0VS

+1.0VGS
@

PE_GPIO1# 1
R878

2
0_0402_5%
D

1
2
39K_0402_5%
Q120
2N7002H_SOT23-3
PX@

2
G

Change footprint
20100812

PX@

For VGA PWR sequence


20100928

PX@
R856

R877
470_0603_5%
@

For VGA power sequence


20100816

R839
20K_0402_5%
PX@

PE_GPIO1#

+5VS

2
G
Q124
2N7002_SOT23
@

C985

2
1

@
Change footprint
20100812

10U_0805_10V4Z

PX@
C983

PX@

C351
0.1U_0603_25V7K
PX@

@
2
1 R879
2
G
0_0402_5%
Q125
2N7002_SOT23
@

Change footprint
20100812

C999
10U_0805_10V4Z
2 PX@

PE_GPIO1#

Change footprint
20100812

20K_0402_5%
Q121
2N7002H_SOT23-3
PX@

PX@ U47
DMN3030LSS-13_SOP8L-8
8
1
7
2
6
3
5

R944
0_0402_5%
@

PX@
R857

2
Q65
PX@
AP2301GN-HF_SOT23-3

R876
470_0603_5%
@

C982

PX@
R840
51K_0402_5%

1U_0603_10V4Z

10U_0805_10V4Z

J4

2MM

2
G

Change from SB00000GV00 to SB548000210


20101125
Change footprint
20100917

J2

PX@

2MM

For VGA power sequence


20100816

PE_GPIO1

2
D

C984

+3VGS

1U_0603_10V4Z

+3VS

+5VALW

C976
0.1U_0603_25V7K
PX@

20100728
C

+1.5V

+1.5VGS
J3

+1.8VGS
@

+1.5V TO +1.5VGS

+1.8VS TO +1.8VGS

Change from SB00000GV00 to SB548000210


J5
20101125
Change footprint
U13
20100812
PX@
DMN3030LSS-13_SOP8L-8
8
1
7
2
1
1
1
6
3
C348
C349
C350
5
10U_0805_10V4Z
10U_0805_10V4Z
1U_0603_10V4Z
2 PX@
2 PX@
2 PX@

2MM

R343
470_0603_5%
@

+VSB

Q74
2N7002H_SOT23-3
PX@

C344
0.1U_0603_25V7K
2 PX@

PE_GPIO1#

Change footprint
20100812

PE_GPIO1# 1 R830
2
0_0402_5%
PX3@

2
G

2
1 R833
2 PE_GPIO1#
G
0_0402_5%
Q76
@
2N7002_SOT23
@

For VGA power sequence


20100816
PX@
R352
1
2
47K_0402_5%
R354
Q78
0_0402_5%
2N7002H_SOT23-3
@
PX@

R346
0_0402_5%
@

R350
300K_0402_5%
PX@

2
G
3

PX_MODE# 1 R829
2
0_0402_5%
BACO@

For VGA power sequence


20100816

2
1 R827
2 PX_MODE#
G
0_0402_5%
Q73
@
2N7002_SOT23 1 R828
2 PE_GPIO1#
@
0_0402_5%
@

PX@
R345 2
1
150K_0402_5%

R348
470_0603_5%
@

+VSB

20100728
R344
20K_0402_5%
PX@

Need to pop for BACO function


Should be unpop for PX3.0
20100728

2
1 1
@ JUMP_43X79 Change from SB00000GV00 to SB548000210
20101125
Change footprint
20100812
U11
PX@
DMN3030LSS-13_SOP8L-8
8
1
7
2
1
1
1
C341
C342
6
3
C340
10U_0805_10V4Z
1U_0603_10V4Z
5
PX@
PX@
10U_0805_10V4Z
2 PX@
2
2

+1.8VS

C352
0.1U_0603_25V7K
PX@

Change footprint
20100812

+3VALW

Update design
20101001
+3VALW

BACO@
R924
100K_0402_5%

BACO@
R925
100K_0402_5%

PX_MODE#
D

2
G
3

(20,43) PX_MODE

IN

1 2

2
2

(13,20,43) PE_GPIO1

OUT

Q123
DTC124EKAT146_SC59-3
PX@

GND

PE_GPIO1#

PX@
R875
100K_0402_5%

Q127
2N7002H_SOT23-3
BACO@
Change footprint
20100812

BOM structure update


20101001

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/06/30

Issued Date

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

RobsonXT-S3 DC Interface
Size
Document Number
Custom

Rev
1.0

LA6755P/7P

Date: Tuesday, November 30, 2010

Sheet
1

21

of

48

change from SM010032020 to SD013000080


20101012

DPA_VDD18#1
DPA_VDD18#2

AG20
AG21

DPE_VDD10#1
DPE_VDD10#2

DPA_VDD10#1
DPA_VDD10#2

AF6
AF7

AG14
AH14
AM14
AM16
AM18

DPE_VSSR#1
DPE_VSSR#2
DPE_VSSR#3
DPE_VSSR#4
DPE_VSSR#5

DPA_VSSR#1
DPA_VSSR#2
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#5

AE1
AE3
AG1
AG6
AH5

AF16
AG17

DPF_VDD18#1
DPF_VDD18#2

DPB_VDD18#1
DPB_VDD18#2

AF22
AG22

DPF_VDD10#1
DPF_VDD10#2

DPB_VDD10#1
DPB_VDD10#2

AF8
AF9

AF23
AG23
AM20
AM22
AM24

DPF_VSSR#1
DPF_VSSR#2
DPF_VSSR#3
DPF_VSSR#4
DPF_VSSR#5

DPB_VSSR#1
DPB_VSSR#2
DPB_VSSR#3
DPB_VSSR#4
DPB_VSSR#5

AF10
AG9
AH8
AM6
AM8

AF17

DPEF_CALR

DPAB_CALR

AE10

110mA

+DPEF_VDD18
C

total:220mA

+DPAB_VDD10
1

PX@ L19
+1.8VGS
2
1
MBK1608121YZF_0603

+1.0VGS
PX@
L21
1
2
MBK1608121YZF_0603

+DPAB_VDD18

130mA

+DPEF_VDD10

10U_0603_6.3V6M

DPE_VDD18#1
DPE_VDD18#2

+DPEF_VDD10

AE11
AF11

1U_0402_6.3V4Z
C359
PX@

130mA

0.1U_0402_10V6K
C358
PX@

C357
PX@

DP A/B POWER

10U_0603_6.3V6M

DP E/F POWER
AG15
AG16

1U_0402_6.3V4Z
C364
PX@

U8G

total:300mA

0.1U_0402_10V6K
C363
PX@

+DPAB_VDD18
1

0.1U_0402_10V6K

+DPEF_VDD18

C362
PX@

total:240mA@LVDS
total:220mA@DP
C356
PX@

PX@
L20 2
1
MBK1608121YZF_0603

1U_0402_6.3V4Z
C361
PX@

+1.0VGS

0.1U_0402_10V6K

1U_0402_6.3V4Z
C355
PX@

C353
PX@

change from SM010032020 to SD013000080


20101012

total:440mA@LVDS
total:300mA@DP
10U_0603_6.3V6M
C354
PX@

PX@
L18 2
1
MBK1608121YZF_0603

10U_0603_6.3V6M
C360
PX@

+1.8VGS

AE13
AF13

+DPAB_VDD10

110mA

PX@
R355 2

1 150_0402_1%

+DPEF_VDD18

20mA
AG18
AF19

20mA
DPE_PVDD
DPE_PVSS

DP PLL POWER

DPA_PVDD
DPA_PVSS

R356 1 PX@

2 150_0402_1%
+DPAB_VDD18

AG8
AG7

+DPEF_VDD18

20mA
AG19
AF20

20mA
DPF_PVDD
DPF_PVSS

DPB_PVDD
DPB_PVSS

+DPAB_VDD18

AG10
AG11

216-0774207-A11ROB_FCBGA631
PX@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/06/30

Deciphered Date

2012/06/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

RobsonXT-S3 DP PWR
Size
B
Date:

Document Number

Rev
1.0

LA6755P/7P
Tuesday, November 30, 2010

Sheet
1

22

of

48

+1.5VGS

+PCIE_VDDR

PX@
0.1U_0402_10V6K

C430
PX@

C429
PX@
PX@
L25 1
2
BLM15BD121SN1D_0402

V12
Y12
U12
AA11
AA12
V11
U11

VDDR4#1
VDDR4#2
VDDR4#3
NC#1
NC#2
NC#3
NC#4

POWER

1U_0402_6.3V4Z

170mA
1

L17

0.1U_0402_10V6K

C449
PX@

1U_0402_6.3V4Z

C447
PX@

C446
PX@

10U_0603_6.3V6M

MEM CLK
1

L16

+1.8VGS

AM30
+MPV18

75mA L8

+SPV18

75mA H7

+SPV10

120mAH8

10U_0603_6.3V6M

1U_0402_6.3V4Z
C388
PX@

C385
PX@

10U_0603_6.3V6M

AA27
AB24
AB32
AC24
AC26
AC27
AD25
AD32
AE27
AF32
AG27
AH32
K28
K32
L27
M32
N25
N27
P25
P32
R27
T25
T32
U25
U27
V32
W25
W26
W27
Y25
Y32

+1.0VGS

1U_0402_6.3V4Z
C384
PX@

1U_0402_6.3V4Z
C383
PX@

C398
PX@

1U_0402_6.3V4Z
C399
PX@

U8E

+VGA_CORE

22U_0805_6.3V6M

22U_0805_6.3V6M
PX@ C426

10U_0603_6.3V6M
PX@ C425

PX@ C423

10U_0603_6.3V6M
PX@ C424

1U_0402_6.3V4Z

1U_0402_6.3V4Z
PX@ C420

1U_0402_6.3V4Z
PX@ C419

11.8A(RMS)/12.9A(Peak)

delete 5 capacitors for new CRB reference


20100722

New Ref circuit


20100722

NC_VDDRHA
+BIF_VDDC

NC_VSSRHA
1

PLL

For Seymour, PCIE_PVDD is PCIE_VDDR.

1U_0402_6.3V4Z
PX@ C416

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

AA15
N15
N17
R13
R16
R18
Y21
T12
T15
T17
T20
U13
U16
U18
V21
V15
V17
V20
Y13
Y16
Y18
M11
M12

1920mA

1U_0402_6.3V4Z
PX@ C415

AA17
AA18
AB17
AB18

change from SM010009U00 to SD028000080


20101012

VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23

CORE

I/O

60mA

L24 1
2
BLM15BD121SN1D_0402

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

PCIE_PVDD
BIF_VDDC#1
BIF_VDDC#2

R21
U21

NC_MPV18

C452
PX@

AA20
AA21
AB20
AB21

L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22

1U_0402_6.3V4Z

LEVEL
TRANSLATION

17mA

AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26

PX@ C413

1U_0402_6.3V4Z

1U_0402_6.3V4Z
C411
PX@

10U_0603_6.3V6M
C410
PX@

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

+3VGS

C409
PX@

0.1U_0402_10V6K

C408
PX@

1U_0402_6.3V4Z

C404
PX@

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8

C451
PX@

+VDDC_CT

110mA
C405
PX@

PX@
L23 1
2
BLM15BD121SN1D_0402

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17

1U_0402_6.3V4Z

change from SM010009U00 to SD028000080


20101012

10U_0603_6.3V6M

+1.8VGS

H13
H16
H19
J10
J23
J24
J9
K10
K23
K24
K9
L11
L12
L13
L20
L21
L22

0.1U_0402_10V6K
C387
PX@

PCIE

1U_0402_6.3V4Z
PX@ C414

MEM I/O

change from SM010032020 to SD013000080


20101012
+1.8VGS
PX@
2
1 L22
MBK1608121YZF_0603

504mA

U8D

1U_0402_6.3V4Z
PX@ C418

1U_0402_6.3V4Z
C380
PX@

1U_0402_6.3V4Z
C403
PX@

1U_0402_6.3V4Z
PX@ C417

0.1U_0402_10V6K

0.1U_0402_10V6K
C392
PX@

0.1U_0402_10V6K
C381
PX@

0.1U_0402_10V6K
C391
PX@

0.1U_0402_10V6K
C390
PX@

1U_0402_6.3V4Z
C389
PX@

1U_0402_6.3V4Z
C374
PX@

1U_0402_6.3V4Z
C373
PX@

1U_0402_6.3V4Z
C372
PX@

1U_0402_6.3V4Z
C371
PX@

10U_0603_6.3V6M
C370
PX@

22U_0805_6.3V6M
C369
PX@

C365
PX@

22U_0805_6.3V6M
C366
PX@

2.3A(RMS)/2.8A(Peak)
1

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8

M13
M15
M16
M17
M18
M20
M21
N20

+VGA_CORE
PX@
1
2 L27
0_0603_5%

+VDDCI

2A(RMS)/3A(Peak)

10U_0603_6.3V6M

ISOLATED
CORE I/O

1U_0402_6.3V4Z
C466
PX@

SPVSS

1U_0402_6.3V4Z
C461
PX@

SPV10

C459
PX@

SPV18

1U_0402_6.3V4Z
C460
PX@

0.1U_0402_10V6K

1U_0402_6.3V4Z
C458
PX@

+1.0VGS
PX@
L28 1
2
BLM15BD121SN1D_0402

10U_0603_6.3V6M
C457
PX@

J7

C456
PX@

0.1U_0402_10V6K

C455
PX@

1U_0402_6.3V4Z

C453
PX@

C454
PX@

L26 1
2
BLM15BD121SN1D_0402

10U_0603_6.3V6M

PX@

M6
N11
N12
N13
N16
N18
N21
P6
P9
R12
R15
R17
R20
T13
T16
T18
T21
T6
U15
U17
U20
U9
V13
V16
V18
Y10
Y15
Y17
Y20
R11
T11

change from SM01000BZ00 to SD013000080


20100722

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31

GND#56
GND#57
GND#58
GND#59
GND#60
GND#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86

GND

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

A3
A30
AA13
AA16
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6

A32
AM1
AM32

216-0774207-A11ROB_FCBGA631

216-0774207-A11ROB_FCBGA631

dist.

0.1u

1u

10u

1.5VGS

VDDR1

10

10

1.8VGS

PCIE_VDDR

VGA_core

PCIE_VDDC

VDDC

25

VDDCI

C1005

Source

330U_D2E_2.5VM_R9M

+VGA_COREP

reserve a 330u capacitor for PWR rwquest


20100920

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

RobsonXT-S3 PWR/GND
Size
C
Date:

Document Number

Rev
1.0

LA6755P/7P
Tuesday, November 30, 2010
1

Sheet

23

of

48

U8C
M_DA[63..0]

(25) M_DA[63..0]

GDDR5/DDR3
M_DQM[7..0]

(25) M_DQM[7..0]

M_DQS[7..0]

(25) M_DQS[7..0]

M_DQS#[7..0]

(25) M_DQS#[7..0]

+1.5VGS

+1.5VGS

R365
40.2_0402_1%
PX@

R363
40.2_0402_1%
PX@

C467
0.1U_0402_16V4Z
PX@

R367
100_0402_1%
PX@
2

R364
100_0402_1%
PX@

MVREFSA

MVREFDA
1

C468
0.1U_0402_16V4Z
PX@

(25) DRAM_RST#

R371
10K_0402_5%
PX@
1

R882
0_0402_5%
@

R366 PX@
1
2
0_0402_5%

R369 PX@
1
2
51_0402_5%
1

DRAM_RST#_R
C469
120P_0402_50V8J
PX@
+1.5VGS

+1.5VGS

K27
J29
H30
H32
G29
F28
F32
F30
C30
F27
A28
C28
E27
G26
D26
F25
A25
C25
E25
D24
E23
F23
D22
F21
E21
D20
F19
A19
D18
F17
A17
C17
E17
D16
F15
A15
D14
F13
A13
C13
E11
A11
C11
F11
A9
C9
F9
D8
E7
A7
C7
F7
A5
E5
C3
E1
G7
G6
G1
G3
J6
J1
J3
J5

DQA0_0/DQA_0
DQA0_1/DQA_1
DQA0_2/DQA_2
DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5
DQA0_6/DQA_6
DQA0_7/DQA_7
DQA0_8/DQA_8
DQA0_9/DQA_9
DQA0_10/DQA_10
DQA0_11/DQA_11
DQA0_12/DQA_12
DQA0_13/DQA_13
DQA0_14/DQA_14
DQA0_15/DQA_15
DQA0_16/DQA_16
DQA0_17/DQA_17
DQA0_18/DQA_18
DQA0_19/DQA_19
DQA0_20/DQA_20
DQA0_21/DQA_21
DQA0_22/DQA_22
DQA0_23/DQA_23
DQA0_24/DQA_24
DQA0_25/DQA_25
DQA0_26/DQA_26
DQA0_27/DQA_27
DQA0_28/DQA_28
DQA0_29/DQA_29
DQA0_30/DQA_30
DQA0_31/DQA_31
DQA1_0/DQA_32
DQA1_1/DQA_33
DQA1_2/DQA_34
DQA1_3/DQA_35
DQA1_4/DQA_36
DQA1_5/DQA_37
DQA1_6/DQA_38
DQA1_7/DQA_39
DQA1_8/DQA_40
DQA1_9/DQA_41
DQA1_10/DQA_42
DQA1_11/DQA_43
DQA1_12/DQA_44
DQA1_13/DQA_45
DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49
DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52
DQA1_21/DQA_53
DQA1_22/DQA_54
DQA1_23/DQA_55
DQA1_24/DQA_56
DQA1_25/DQA_57
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
DQA1_29/DQA_61
DQA1_30/DQA_62
DQA1_31/DQA_63

MVREFDA
MVREFSA

K26
J26

R368 1 PX@
R370 1 PX@

check!

GDDR5/DDR3

M_DA0
M_DA1
M_DA2
M_DA3
M_DA4
M_DA5
M_DA6
M_DA7
M_DA8
M_DA9
M_DA10
M_DA11
M_DA12
M_DA13
M_DA14
M_DA15
M_DA16
M_DA17
M_DA18
M_DA19
M_DA20
M_DA21
M_DA22
M_DA23
M_DA24
M_DA25
M_DA26
M_DA27
M_DA28
M_DA29
M_DA30
M_DA31
M_DA32
M_DA33
M_DA34
M_DA35
M_DA36
M_DA37
M_DA38
M_DA39
M_DA40
M_DA41
M_DA42
M_DA43
M_DA44
M_DA45
M_DA46
M_DA47
M_DA48
M_DA49
M_DA50
M_DA51
M_DA52
M_DA53
M_DA54
M_DA55
M_DA56
M_DA57
M_DA58
M_DA59
M_DA60
M_DA61
M_DA62
M_DA63

2 243_0402_1% J25
2 243_0402_1% K25

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA0_6
MAA0_7/MAA0_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_13/BA2
MAA1_6/MAA_14/BA0
MAA1_7/MAA_15/BA1

K17
J20
H23
G23
G24
H24
J19
K19
J14
K14
J11
J13
H11
G11
J16
L15

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_BA2
M_BA0
M_BA1

WCKA0_0/DQMA_0
WCKA0B_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0B_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1B_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1B_1/DQMA_7

E32
E30
A21
C21
E13
D12
E3
F4

M_DQM0
M_DQM1
M_DQM2
M_DQM3
M_DQM4
M_DQM5
M_DQM6
M_DQM7

EDCA0_0/RDQSA_0
EDCA0_1/RDQSA_1
EDCA0_2/RDQSA_2
EDCA0_3/RDQSA_3
EDCA1_0/RDQSA_4
EDCA1_1/RDQSA_5
EDCA1_2/RDQSA_6
EDCA1_3/RDQSA_7

H28
C27
A23
E19
E15
D10
D6
G5

M_DQS0
M_DQS1
M_DQS2
M_DQS3
M_DQS4
M_DQS5
M_DQS6
M_DQS7

DDBIA0_0/WDQSA_0
DDBIA0_1/WDQSA_1
DDBIA0_2/WDQSA_2
DDBIA0_3/WDQSA_3
DDBIA1_0/WDQSA_4
DDBIA1_1/WDQSA_5
DDBIA1_2/WDQSA_6
DDBIA1_3/WDQSA_7

H27
A27
C23
C19
C15
E9
C5
H4

M_DQS#0
M_DQS#1
M_DQS#2
M_DQS#3
M_DQS#4
M_DQS#5
M_DQS#6
M_DQS#7

ADBIA0/ODTA0
ADBIA1/ODTA1

L18
K16

VRAM_ODT0
VRAM_ODT1

CLKA0
CLKA0B

H26
H25

M_CLK0
M_CLK#0

CLKA1
CLKA1B

G9
H9

M_CLK1
M_CLK#1

RASA0B
RASA1B

G22
G17

M_RAS#0
M_RAS#1

CASA0B
CASA1B

G19
G16

M_CAS#0
M_CAS#1

CSA0B_0
CSA0B_1

H22
J22

M_CS#0

CSA1B_0
CSA1B_1

G13
K13

M_CS#1

MVREFDA
MVREFSA

CKEA0
CKEA1

K20
J17

M_CKE0
M_CKE1

MEM_CALRN0
MEM_CALRP0

WEA0B
WEA1B

G25
H10

M_WE#0
M_WE#1

MAA1_8
MAA0_8

G14
G20

M_MA13

MEMORY INTERFACE

M_MA[13..0]

(25) M_MA[13..0]

+1.8VGS

GDDR5
DRAM_RST#_R
R372 1
R373 1

@
@

2 51.1_0402_1%
2 51.1_0402_1%

@ C470
1
2
1
2

0.1U_0402_16V4Z
0.1U_0402_16V4Z

L10

DRAM_RST

K8
L7

CLKTESTA
CLKTESTB

R357
R358
R359
R360
R361
R362

1
1
1
1
1
1

X76@ 2
X76@ 2
X76@ 2
X76@ 2
X76@ 2
X76@ 2

VRAM_ID0

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

VRAM_ID0 (19)

VRAM_ID1

VRAM_ID1 (19)

VRAM_ID2

VRAM_ID2 (19)

Vendor
M_BA2
M_BA0
M_BA1

(25)
(25)
(25)

VRAM_ID0 VRAM_ID1 VRAM_ID2

Hynix 512MB
PN:SA000032460

Hynix 1GB
PN:SA00003VS20

Samsung 512MB
PN:SA000035700

Samsung 1GB
PN:SA00003MQ20

ZZZ

ZZZ

Hynix

Samsung

H1G@
X7624938L01

VRAM_ODT0 (25)
VRAM_ODT1 (25)

S1G@
X7624938L02

0706 update

M_CLK0 (25)
M_CLK#0 (25)

update X76 PN

M_CLK1 (25)
M_CLK#1 (25)

ZZZ

ZZZ

M_RAS#0 (25)
M_RAS#1 (25)

M_CAS#0 (25)
M_CAS#1 (25)
M_CS#0

(25)

M_CS#1

(25)

Hynix

H512@
X7624938L03

Samsung

S512@
X7624938L04

M_CKE0 (25)
M_CKE1 (25)
M_WE#0 (25)
M_WE#1 (25)

@ C471

Route 50ohms single-ended/100ohm diff and keep short


debug only, for clock observation,if not need, DNI.

216-0774207-A11ROB_FCBGA631

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/06/30

Deciphered Date

2012/06/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

RobsonXT-S3 MEM Interface


Size
B
Date:

Document Number

Rev
1.0

LA6755P/7P
Tuesday, November 30, 2010

Sheet
1

24

of

48

M_DA[63..0]

(24) M_DA[63..0]

M_MA[13..0]

(24) M_DQS#[7..0]

M_DQM[7..0]
M_DQS[7..0]
M_DQS#[7..0]

U19

M9
H2

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

M_BA0
M_BA1
M_BA2

M3
N9
M4

(24)
(24)
(24)

M_BA0
M_BA1
M_BA2

(24)
(24)
(24)

M_CLK0
M_CLK#0
M_CKE0

M_CLK0
J8
M_CLK#0 K8
M_CKE0 K10

(24) VRAM_ODT0
(24)
M_CS#0
(24)
M_RAS#0
(24)
M_CAS#0
(24)
M_WE#0

VRAM_ODT0K2
M_CS#0
L3
M_RAS#0 J4
M_CAS#0 K4
M_WE#0
L4

M_DQS2
M_DQS0

F4
C8

M_DQM2
M_DQM0

E8
D4

M_DQS#2
M_DQS#0

G4
B8

T3

(24) DRAM_RST#

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E4
F8
F3
F9
H4
H9
G3
H8

M_DA19
M_DA20
M_DA21
M_DA18
M_DA23
M_DA17
M_DA22
M_DA16

D8
C4
C9
C3
A8
A3
B9
A4

M_DA0
M_DA4
M_DA6
M_DA7
M_DA3
M_DA1
M_DA2
M_DA5

VREFC_A2
VREFD_Q2

+1.5VGS

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET

B3
D10
G8
K3
K9
N2
N10
R2
R10

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

M_BA0
M_BA1
M_BA2

M3
N9
M4

M_CLK0
M_CLK#0
M_CKE0

J8
K8
K10

+1.5VGS

A2
A9
C2
C10
D3
E10
F2
H3
H10

VRAM_ODT0 K2
M_CS#0
L3
M_RAS#0
J4
M_CAS#0
K4
M_WE#0
L4
M_DQS3
M_DQS1

F4
C8

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

M_DQM3
M_DQM1

E8
D4

M_DQS#3
M_DQS#1

G4
B8

DRAM_RST# T3
L9

U18

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E4
F8
F3
F9
H4
H9
G3
H8

M_DA26
M_DA28
M_DA27
M_DA30
M_DA24
M_DA29
M_DA25
M_DA31

D8
C4
C9
C3
A8
A3
B9
A4

M_DA14
M_DA10
M_DA15
M_DA11
M_DA12
M_DA8
M_DA13
M_DA9

VREFC_A3
VREFD_Q3

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

M_BA0
M_BA1
M_BA2

B3
D10
G8
K3
K9
N2
N10
R2
R10

M_CLK1
J8
M_CLK#1 K8
M_CKE1 K10

A2
A9
C2
C10
D3
E10
F2
H3
H10

(24) VRAM_ODT1
(24)
M_CS#1
(24)
M_RAS#1
(24)
M_CAS#1
(24)
M_WE#1

VRAM_ODT1K2
M_CS#1
L3
M_RAS#1 J4
M_CAS#1 K4
M_WE#1
L4

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

A1
A11
T1
T11

NC
NC
NC
NC

PX@
R375
243_0402_1%

B2
B10
D2
D9
E3
E9
F10
G2
G10

M_DQS4
M_DQS5

F4
C8

M_DQM4
M_DQM5

E8
D4

M_DQS#4
M_DQS#5

G4
B8

J2
L2
J10
L10
A1
A11
T1
T11

100-BALL
SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA
X76@

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

ODT/ODT0
CS
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET

L9

M_DA35
M_DA34
M_DA36
M_DA37
M_DA32
M_DA38
M_DA33
M_DA39

D8
C4
C9
C3
A8
A3
B9
A4

M_DA47
M_DA42
M_DA46
M_DA41
M_DA45
M_DA40
M_DA43
M_DA44

B3
D10
G8
K3
K9
N2
N10
R2
R10

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

DRAM_RST# T3

E4
F8
F3
F9
H4
H9
G3
H8

VREFC_A4
VREFD_Q4

ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC
NC
NC
NC

PX@
R376
243_0402_1%

B2
B10
D2
D9
E3
E9
F10
G2
G10

+1.5VGS

M9
H2

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13

+1.5VGS

BA0
BA1
BA2

J2
L2
J10
L10

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

A1
A11
T1
T11

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

M_BA0
M_BA1
M_BA2

M3
N9
M4

M_CLK1
M_CLK#1
M_CKE1

J8
K8
K10

+1.5VGS

A2
A9
C2
C10
D3
E10
F2
H3
H10

VRAM_ODT1 K2
M_CS#1
L3
M_RAS#1
J4
M_CAS#1
K4
M_WE#1
L4
M_DQS6
M_DQS7

F4
C8

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

M_DQM6
M_DQM7

E8
D4

M_DQS#6
M_DQS#7

G4
B8

DRAM_RST# T3
L9
PX@
R377
243_0402_1%

B2
B10
D2
D9
E3
E9
F10
G2
G10

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC
NC
NC
NC

100-BALL
SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA
X76@

+1.5VGS

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M3
N9
M4

M_CLK1
M_CLK#1
M_CKE1

(24)
(24)
(24)

+1.5VGS

U21

VREFCA
VREFDQ

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

+1.5VGS

BA0
BA1
BA2

J2
L2
J10
L10

M9
H2

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13

ZQ/ZQ0

PX@
R374
243_0402_1%

M9
H2

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13

L9

U20

VREFCA
VREFDQ

VREFC_A1
VREFD_Q1

J2
L2
J10
L10
A1
A11
T1
T11

100-BALL
SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA
X76@

+1.5VGS

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

M_DA54
M_DA52
M_DA53
M_DA48
M_DA51
M_DA49
M_DA55
M_DA50

E4
F8
F3
F9
H4
H9
G3
H8

M_DA57
M_DA58
M_DA60
M_DA61
M_DA63
M_DA62
M_DA56
M_DA59

D8
C4
C9
C3
A8
A3
B9
A4

+1.5VGS

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

B3
D10
G8
K3
K9
N2
N10
R2
R10

+1.5VGS

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

(24) M_DQS[7..0]

+1.5VGS

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

(24) M_DQM[7..0]

(24) M_MA[13..0]

NC
NC
NC
NC

B2
B10
D2
D9
E3
E9
F10
G2
G10

100-BALL
SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA
X76@

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

PX@ 2
56_0402_1%

M_CLK#1 1
R397

PX@ 2
56_0402_1%

1 PX@
C507
0.01U_0402_16V7K

10U_0603_6.3V6M
1
C488
PX@

C489
PX@

10U_0603_6.3V6M
1
1

10U_0603_6.3V6M
1
1

PX@ 2
56_0402_1%

M_CLK#0 1
R396

PX@ 2
56_0402_1%

R385
2
1
4.99K_0402_1%
C479

0.1U_0402_10V6K

R393
2
1
4.99K_0402_1%

VREFD_Q4
PX@

PX@

C490
@

C491
PX@

2
10U_0603_6.3V6M

C480
PX@

+1.5VGS

1U_0402_6.3V4Z
1
1

C481
PX@

C492
PX@

2
2
2
10U_0603_6.3V6M10U_0603_6.3V6M

C482
@

1U_0402_6.3V4Z
M_CLK0 1
R394

+1.5VGS
+1.5VGS

C478

VREFC_A4
PX@

PX@

0.1U_0402_10V6K

C477

R392
2
1
4.99K_0402_1%

PX@

PX@

0.1U_0402_10V6K

PX@

VREFD_Q3
R391
2
1
4.99K_0402_1%

C476

PX@

VREFC_A3
PX@

PX@

0.1U_0402_10V6K

R384
2
1
4.99K_0402_1%

R383
2
1
4.99K_0402_1%

R382
2
1
4.99K_0402_1%

C475

PX@

VREFD_Q2
PX@

PX@

0.1U_0402_10V6K

R389
2
1
4.99K_0402_1%

PX@

VREFC_A2
PX@

PX@

C474

0.1U_0402_10V6K

PX@
C473

PX@

0.1U_0402_10V6K

VREFC_A1
R387
2
1
4.99K_0402_1%

C472

0.1U_0402_10V6K

R386
2
1
4.99K_0402_1%

M_CLK1
1
R395

PX@

PX@

R390
2
1
4.99K_0402_1%

PX@

VREFD_Q1
PX@

R381
2
1
4.99K_0402_1%

PX@

R388
2
1
4.99K_0402_1%

PX@

R380
2
1
4.99K_0402_1%

R379
2
1
4.99K_0402_1%

R378
2
1
4.99K_0402_1%

C483
PX@

1U_0402_6.3V4Z
1
1

C493
PX@

1U_0402_6.3V4Z

C494
@

1U_0402_6.3V4Z
1
1

C495
PX@

1U_0402_6.3V4Z

C496
PX@

1U_0402_6.3V4Z
1
1

C497
PX@

1U_0402_6.3V4Z

C498
@

1U_0402_6.3V4Z
1
1

C499
PX@

1U_0402_6.3V4Z

1U_0402_6.3V4Z
1
1
C500
PX@

C501
PX@

1U_0402_6.3V4Z

C484
@

1U_0402_6.3V4Z
1
1

C485
PX@

1U_0402_6.3V4Z

C486
PX@

1U_0402_6.3V4Z
1
1

C502
PX@

1U_0402_6.3V4Z

1U_0402_6.3V4Z
1
1

C503
PX@

C504
PX@

1U_0402_6.3V4Z

C505
PX@

1U_0402_6.3V4Z
1
1

C487
PX@

1U_0402_6.3V4Z

1 PX@
C506
0.01U_0402_16V7K
2

VRAM P/N :
Hynix : SA000041S10 (S IC D3 64MX16 H5TQ1G63BFR-11C FBGA C38! )
update VRAM PN

Issued Date

0619 update

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Samsung : SA000041T10 (S IC D3 64MX16 K4W1G1646E-HC11 FBGA C38! )

2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

RobsonXT-S3 VRAM
Size
C
Date:

Document Number

Rev
1.0

LA6755P/7P
Tuesday, November 30, 2010
1

Sheet

25

of

48

+1.7_VDDCT
+1.7_LX

+3V_LAN

Atheros request can't disable LAN power

Close to Pin40

Pin

+1.7_LX
2
4.7UH_SIA4012-4R7M_20%

1
L56

1000P_0402_50V7K

JUMP_43X79

C786

C785

C784

10U_0805_10V4Z

+1.7_VDDCT

J6

0.1U_0402_16V4Z

+3VALW

Power On strapping
Description

Chip Default

H:Over Clock Enable

LED0

L:Over Clock Disable

Note:
Place Close to LAN chip
L56 DCR< 0.15 ohm
Rate current of L33 > 1A

H:SWR Switch mode regulator Select


LED2

AR8151 Pin23=LED2.

--

AR8152, Pin23 is CLKREQ

U29

8152@

no overclocking
PD 5.1K
R650
5.1K_0402_5%
1
2

S IC AR8152-AL1E QFN 40P E-LAN CTRL


LED0,1,2 intel Pull UP

(13) PCIE_FTX_C_DRX_N0

36

RX_N

(13) PCIE_FTX_C_DRX_P0

35

RX_P

(13) CLK_PCIE_LAN#
(13) CLK_PCIE_LAN

32
33

REFCLK_N
REFCLK_P

CLKREQ_LAN#_R
0.1U_0402_16V4Z
1
2
C796 8152@

+1.1_AVDDL
+1.1_AVDDL

C806
0.1U_0402_16V4Z

10

28
27

TEST_RST
TESTMODE

VDD33

7
8

LX
XTLO
XTLI
VDDCT

CLKREQ#
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL_REG

+1.7_VDDCT

+1.7_VDDCT

+1.1_DVDDL C797 1
C798 1
C800 1

AVDDH
AVDDH
AVDDH_REG

16
22
9

+2.7_AVDDH
+2.7_AVDDH

1
GND

LAN_XTALO

Near
Pin6

Y6

1
24
37

LAN_XTALI

C791

40

DVDDL
DVDDL_REG

AR8151-AL1A_QFN40_5X5
GIGA@

+3V_LAN

2 2.37K_0402_1%

C791 & C792 Close pin1 < 200mil


C794 & 795 Close pin < 400mil

+1.7_LX
+1.7_LX

41

1 R654

+3V_LAN

C807

RBIAS

27P_0402_50V8J

Near
Near
Near
Near
Pin13 Pin19 Pin31 Pin34

C805

1U_0402_6.3V4Z

C804

0.1U_0402_16V4Z

C803

0.1U_0402_16V4Z

GIGA@

SMCLK
SMDATA

13
19
31
34
6

+1.1_AVDDL

0.1U_0402_16V4Z

C802

GIGA@
C801

0.1U_0402_16V4Z

W AKE#

25
26

Near
Pin9

2 0.1U_0402_16V4Z
2 1U_0402_6.3V4Z
2 0.1U_0402_16V4Z

Near

Near
Pin22

C799
0.1U_0402_16V4Z
B

Pin37

Place Close to LAN chip

Near
Pin16

MDI0+

R658 1

MDI0-

R659 1

MDI1+

R660 1

MDI1-

R661 1

MDI2+

R662 1
GIGA@
R663 1
GIGA@
R664 1
GIGA@
R665 1
GIGA@

25MHZ_20PF_7A25000012

27P_0402_50V8J

(14) LAN_CLKREQ#

PERST#

LAN_CLKREQ#

(27)
(27)
(27)
(27)
(27)
(27)
(27)
(27)

C810 GIGA@

LAN_XTALO
LAN_XTALI
R657
1 GIGA@ 2
0_0402_5%

LAN_RBIAS

MDI0MDI0+
MDI1MDI1+
MDI2MDI2+
MDI3MDI3+

R651
1 8152@ 2
0_0402_5%

0.1U_0402_16V4Z

@
LAN_CLKREQ#
1 R926
2
10K_0402_5%

MDI0MDI0+
MDI1MDI1+
MDI2MDI2+
MDI3MDI3+

C809

+3VALW

12
11
15
14
18
17
21
20

0.1U_0402_16V4Z

(31) LAN_WAKE#

TRXN0
TRXP0
TRXN1
TRXP1
TRXN2
TRXP2
TRXN3
TRXP3

ACTIVITY (27)
LAN_LINK# (27)

C808

PCIE_WAKE#

38
39
23

0.1U_0402_16V4Z

2 0_0402_5%

C816

C815

R652 1

8151-AL1A

LED_0
LED_1
LED_2

1U_0402_6.3V4Z

PLT_RST#

(13,30,31) PLT_RST#
(14,30) FCH_PCIE_WAKE#

Atheros

10U_0805_10V4Z

TX_P

10U_0805_10V4Z
C795

TX_N

2 0.1U_0402_16V7K PCIE_FRX_DTX_P0_C 30

C794

2 0.1U_0402_16V7K PCIE_FRX_DTX_N0_C 29

C7901

1U_0402_6.3V4Z

C7891

(13) PCIE_FRX_DTX_P0

C792

(13) PCIE_FRX_DTX_N0

0.1U_0402_16V4Z

U29

Place Close to Chip

MDI2MDI3+
MDI3-

49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2

@ C811 1000P_0402_50V7K

2 C812 0.1U_0402_16V4Z

2 C814 0.1U_0402_16V4Z

2 C818 0.1U_0402_16V4Z
GIGA@
@ C819 1000P_0402_50V7K

2 C820 0.1U_0402_16V4Z
GIGA@

@ C813 1000P_0402_50V7K

@ C817 1000P_0402_50V7K

8152 no mount MDI3+,MDI3-,MDI2-,MDI2+ resister and cap


Configure
Pin4
AR8152

VDDCT_REG

AR8151

CLKREQn

R657

C796

*
*
5

Configure
Pin23
CLKREQn

R651

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LED[2]
4

Title

LAN-AR8151/8152
Size Document Number
Custom
Date:

Rev
1.0

LA6755P/7P

Tuesday, November 30, 2010

Sheet
1

26

of

48

R916
+1.7_VDDCT

1
0_0603_5%
@ C996
1U_0402_6.3V4Z

Place Close to T88


D

MDI1-

T88

MDI1+
D1 @

(26)
(26)

MDI1+
MDI1-

(26)
(26)

MDI0+
MDI0-

MDI1+
MDI1-

1
2
3
4
5
6
7
8

MDI0+
MDI0-

RX+
RXCT
NC
NC
CT
TX+
TX-

16
15
14
13
12
11
10
9

MDO1+
MDO1MCT0
MCT1
MDO0+
MDO0@
C1013
22U_1206_10V7K

GND
350uH_NS0013LF

R666

1 75_0402_5%

R667

1 75_0402_5%

@
C1012
22U_1206_10V7K

Reserve gas tube for EMI go rural solution


20101006

5
4
3
2
1

5
4
3
2
1

11

6
7
8
9
10

6
7
8
9
10

TCLAMP3302N.TCT_SLP2626P10-10

RD+
RDCT
NC
NC
CT
TD+
TD-

T97
MDI0-

(26)
(26)

MDI2+
MDI2-

(26)
(26)

MDI3+
MDI3-

MDI2+
MDI2-

1
2
3
4
5
6
7
8

MDI0+

Reserve D1 for EMI go rural solution


20101006

MDI3+
MDI3-

GIGA@

RD+
RDCT
NC
NC
CT
TD+
TD-

RX+
RXCT
NC
NC
CT
TX+
TX-

16
15
14
13
12
11
10
9

MDO2+
MDO2MCT2

R668 2 GIGA@ 1 75_0402_5%

MCT3
MDO3+
MDO3-

R669 2 GIGA@ 1 75_0402_5%


C822

GIGA@

1000P_1206_2KV7K

0.1U_0402_16V4Z

C993

GIGA@
C992

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1
C991

C990

0.1U_0402_16V4Z

350uH_NS0013LF

RJ45 Conn.

Place close to TCT pin

JRJ1
(26)

LAN_LINK#

R671

@
C994
470P_0402_50V7K

1 220_0402_5%

LAN_LINK_LED#_R

+3V_LAN

12

Green LED-

11

Green LED+

MDO3-

MDO3+

PR4+

MDO1-

PR2-

MDO2-

PR3-

MDO2+

PR3+

MDO1+

PR2+

MDO0-

PR1-

MDO0+

PR1+

10
(26)

R670

ACTIVITY

@
C995
470P_0402_50V7K

1 220_0402_5%

ACTIVITY_R

SHLD2

16

SHLD1

15

SHLD2

14

SHLD1

13

PR4-

Yellow LEDYellow LED+


LIYO_101007-08203-033
ME@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/06/30

Issued Date

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

LAN_Transformer
Size
Document Number
Custom
Date:

Rev
1.0

LA6755P/7P

Tuesday, November 30, 2010

Sheet
1

27

of

48

CX20671
High Definition Audio Codec SoC
With Integrated Class-D Stereo
Amplifier.
An integrated 5 V to 3.3 V Low-dropout
voltage regulator (LDO).
An integrated 3.3 V to 1.8V Low-dropout
voltage regulator (LDO).

HDA_RST_AUDIO#

EMI

HDA_SYNC_AUDIO
HDA_SDOUT_AUDIO
1 R672
2
0_0402_5%

HDA_BITCLK_AUDIO

1
22P_0402_50V8J
C826

1
22P_0402_50V8J
C825

1
22P_0402_50V8J
C824

22P_0402_50V8J
C823

2
D

Cheange to pop for PVT for EMI solution


20101006

+LDO_OUT_3.3V_R

+LDO_OUT_3.3V
0.1U_0402_16V4Z

C834

10U_0805_10V4Z
C835

C832

0.1U_0402_16V4Z

1U_0603_10V4Z
C833

C830

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C827

10U_0805_10V4Z
C831

0_0402_5%
R674
To support Wake-on-Jack or Wake-on-Ring, the CODEC
VAUX_3.3 & VDD_IO pins must be powerd by a rail that
is not removed unless AC power is removed.
*DSH page42 has more detail.

Reserve for ESD

R673
2

+3VALW

+VAUX_3.3

0_0402_5%

0.1U_0402_16V4Z
C829

+3VS

10U_0805_10V4Z
C828

+3VS

AVDD_3.3 pinis output of


internal LDO. NOT connect
to external supply.
Layout Note:Path from +5VS to LPW R_5.0
RPW R_5.0 must be very low
resistance (<0.01 ohms)

For 20671-21Z update


20100928

+3VS
2

R676

(31)
(31)

EAPD
EC_MUTE#

0_0402_5%

1
2

0_0402_5%

10

2 R688
1
R689

38
37

PORTB_R
PORTB_L
B_BIAS

SPK_L2+
SPK_L1-

11
13

SPK_R2+
SPK_R1-

16
14

12
15
17
36

MIC_INR
MIC_INL

35
34
33

1 R678

2 @

2 5.11K_0402_1%

R681
R683

1
1

2 10K_0402_1%
2 39.2K_0402_1%

R684
R685

GPIO0/EAPD#
GPIO1/SPK_MUTE#

DMIC_CLK
DMIC_1/2

NC
NC
NC

LEFT+
LEFTRIGHT+
RIGHT-

AVEE
FLY_P
FLY_N

+MICBIASC

C847 1
C848 1

41

+VAUX_3.3
MIC_JD (34)
PLUG_IN (34)

2 2.2U_0603_6.3V4Z
2 2.2U_0603_6.3V4Z

2.2K_0402_5%
2.2K_0402_5%
100_0402_1%

R687

100_0402_1%

EXT_MIC_R (34)
EXT_MIC_L (34)

R690
R691

24
25
39

Changed from 5.1ohm to 15ohm


for "zi zi"noise.

1
C852

2
1U_0603_10V4Z

CX20671-21Z_QFN40_6X6

1
1

15_0402_5%
15_0402_5%

2
2

External MIC

HP_OUTR (34)
HP_OUTL (34)

Headphone

+MICBIASB
1

Change Part number to SA00003K410 (20671-21Z)


20100928

Sense resistors must be


connected same power
that is used for VAUX_3.3

+MICBIASC

R686

23
22

21
19
20

Port C
Port A

Internal MIC

+MICBIASB

32
31
30

R680

PC_BEEP
C_BIAS
PORTC_R
PORTC_L

+5VS

0.1_1206_1%

10U_0805_10V4Z

10U_0805_10V4Z
C843

Please bypass caps very close to device.

GND

Internal SPEAKER

0.1U_0402_16V4Z
C842

C840

C846

27
28
26

29

SENSE_A

0.1U_0402_16V4Z
C841

0.1U_0402_16V4Z

C838

BIT_CLK
SYNC
SDATA_IN
SDATA_OUT

LPWR_5.0
RPWR_5.0
CLASS-D_REF

PORTA_R
PORTA_L
40
1

2 0_0805_5%

10U_0805_10V4Z

PC_BEEP

0.1U_0402_16V4Z

5
8
6
4

RESET#

FILT_1.65

HDA_BITCLK_AUDIO
HDA_SYNC_AUDIO
HDA_SDOUT_AUDIO

EAPD active low


0=power down ex AMP
1=power up ex AMP

U31

HDA_RST_AUDIO#

2 33_0402_5%

R959
0_0402_5%
EMI reserved
20100816

+ClassD_5VS

C853

R682 1

0.1U_0402_16V4Z
C854

(14) HDA_BITCLK_AUDIO
(14) HDA_SYNC_AUDIO
(14) HDA_SDIN0
(14) HDA_SDOUT_AUDIO

AVDD_3.3
AVDD_5V
AVDD_HP

(14) HDA_RST_AUDIO#

FILT_1.8
VDD_IO
VAUX_3.3
DVDD_3.3

10U_0805_10V4Z
C839

10 mils

R679

1 R963
+5VS

10K only needed if supply to VAUX_3.3


is removed during system re-start.

@
C977
100P_0402_50V8J

3
7
2
18

HDA_RST_AUDIO#

0.1U_0402_16V4Z

C836

R677

10U_0805_10V4Z
C845

0_0402_5%

10K_0402_5%
C844

+3VALW

0.1U_0402_16V4Z

@
R855
4.7K_0402_5%

0_0402_5%

1U_0603_10V4Z
C837

+3VS

change from SE070104Z80 to SD028000080 for EMI request


20101011

MIC1
1
2

C850
1
2
0.1U_0402_16V4Z
R692
1

2
0_0402_5%

R693
1

R695
4.7K_0402_5%
C849
1
2
0.1U_0402_16V4Z

C856 1

2 2.2U_0603_6.3V4Z

MIC_INR

GNDA
MIC_INL

WM-64PCY_2P
45@

Delete redundant part base on


vender's suggestion 20100810

Cheange to pop for PVT for EMI solution


20101006

2
0_0402_5%

R696
1

2
0_0402_5%

wide 30MIL

Short GND and GNDA base on


vender's suggestion 20100810

close to Codec
JSPK1

0_0402_5%
1

L57 ~ L60 change to 0ohms base on


vender's suggestion 20100810

D30 RB751V_SOD323
(14)

FCH_SPKR

1PC_BEEP1

D31 RB751V_SOD323

1
C997

L57 ~ L60 Change from SD013000080 to SM01000BZ00


pop C863, C864, C865, C861
EMI solution 20100824

PC_BEEP
2
0.1U_0402_16V4Z

@
R935
10K_0402_5%

20101007
Follow vender recommanded circuit
20100722

R934
1
2
33_0402_5%

1
2
3
4

5
6

GND1
GND2

ACES_88231-04001
ME@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/06/30

Deciphered Date

2012/06/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CX20671 Codec
Size
C

Document Number

Rev
1.0

LA6755P/7P

Date: Tuesday, November 30, 2010


5

1
2
3
4

ICH Beep

SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN

1000P_0402_50V7K

BEEP#

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

1000P_0402_50V7K
C865

(31)

2
2
2
2

1000P_0402_50V7K
C864

EC Beep

1
1
1
1

1000P_0402_50V7K
C861

R953
2

PC Beep

L57
L58
L59
L60

SPK_R1SPK_R2+
SPK_L1SPK_L2+

GNDA

C863

GND

Sheet
1

28

of

48

Close U32

R704
10K_0402_5%
@

REMOTE1-

REMOTE2+
@
C869
2200P_0402_50V7K

1
2
2

REMOTE2-

C871
0.1U_0402_16V4Z

Q94
MMST3904-7-F_SOT323-3

2
B
2

+5VS

REMOTE1-

VDD

SMCLK

10

EC_SMB_CK2 (5,19,31)

DP1

SMDATA

EC_SMB_DA2 (5,19,31)

REMOTE1-

DN1

ALERT#

REMOTE2+

DP2

THERM#

REMOTE2-

DN2

GND

JFAN1

REMOTE1+

FAN1 Conn

U32

@
C867
100P_0402_50V8J

@
C870
100P_0402_50V8J

7
6

1
2
3
4
5
6

(31) EC_TACH
(31) EC_FAN_PWM

Under WLAN

REMOTE2+

REMOTE2-

C872
10U_0805_10V4Z

C
1

Q95 @
MMST3904-7-F_SOT323-3

2
B
2

+3VS

Close to DDR

REMOTE1+

C868
2200P_0402_50V7K

+3VS

SMSC thermal sensor


placed near by VRAM

1
2
3
4
G5
G6

ACES_85205-04001
ME@

REMOTE1+
1

EMC1403-2-AIZL-TR_MSOP10

REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"

Address 1001_101xb
Change from SA000029210 to SA000046C00 for main source

SATA HDD Conn.


ODD Power Control

JHDD1
SATA_ITX_DRX_P0
SATA_ITX_DRX_N0

(15) SATA_ITX_DRX_P0
(15) SATA_ITX_DRX_N0
(15) SATA_DTX_C_IRX_N0
(15) SATA_DTX_C_IRX_P0

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0

C874 1
C873 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_IRX_N0
SATA_DTX_IRX_P0

1
2
3
4
5
6
7

GND
RX+
RXGND
TXTX+
GND

@
1

J8

+5VS

1
+5VS

+3VS

1
C877
1000P_0402_50V7K

1
C878
0.1U_0402_16V4Z

1
C879
1U_0603_10V4Z

1
C880
10U_0805_10V4Z

@
C881
10U_0805_10V4Z

@
C882
0.1U_0402_16V4Z

2
1
GND
GND

23
24

(15) ODD_EN

IN

+5VS

OUT

Q96
AP2301GN-HF_SOT23-3
R707
10K_0402_5%

GND

+3VS

3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V

+5VS_ODD
Change footprint
20100812
1

3
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

JUMP_43X79

C884
1

2
R859
100K_0402_5%

0.01U_0402_16V7K

C883
0.1U_0402_16V4Z

2
2

C885
10U_0805_10V4Z

Q97
DTC124EKAT146_SC59-3

SUYIN_127043FB022G278ZR
ME@

For cost concern


20101012

Issued Date

2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Title

HDD/ODD/EMC1403/FAN
Size
B

Document Number

Rev
1.0

LA6755P/7P

Date:

Tuesday, November 30, 2010


G

Sheet

29
H

of

48

Mini-Express Card for WLAN/WiMAX(Half)


+1.5VS
+3VALW
+3VS

1
2

2 0_0402_5%
2 0_0402_5%

GND

GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

@
C886
0.1U_0402_16V4Z

@
C887
0.1U_0402_16V4Z

@
C888
0.1U_0402_16V4Z

R885 1
R710 1

2
2

LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
0_0402_5%
0_0402_5%

R711 1
R712 1

2 @ 0_0402_5%
0_0402_5%
2

R713 1
R714 1

2 @ 0_0402_5%
2 @ 0_0402_5%

WL_OFF# (15)
WL_OFF#_EC (31)
PLT_RST# (13,26,31)
+3VALW
+3VS
FCH_SMCLK0
FCH_SMDAT0

(8,9,14)
(8,9,14)

USB20_N7 (14)
USB20_P7 (14)
0_0402_5%
0_0402_5%

2
2

@
@

1 R715
1 R716

WLAN_LED#

(46)

54

R719
100K_0402_5%
1

For EC to detect
debug card insert.

WAKE#
3.3V
NC
GND
NC
1.5V
CLKREQ#
NC
GND
NC
REFCLKNC
REFCLK+
NC
GND
NC
NC
GND
NC
NC
GND
PERST#
PERn0
+3.3Vaux
PERp0
GND
GND
+1.5V
GND
SMB_CLK
PETn0
SMB_DATA
PETp0
GND
GND
USB_DNC
USB_D+
NC
GND
NC
LED_WWAN#
NC
LED_WLAN#
NC
LED_WPAN#
NC
+1.5V
NC
GND
NC
+3.3V

TAITW_PFPET0-AFGLBG1ZZ4N0
ME@

R708 1
R709 1

J10
JUMP_43X79

JWLN1
WLAN_WAKE# 1
3
5
WLAN_CLKREQ#
7
(14) WLAN_CLKREQ#
9
11
(13) CLK_PCIE_WLAN#
13
(13) CLK_PCIE_WLAN
15
PCI_RST#_R
17
CLK_PCI_DB
19
21
23
(13) PCIE_FRX_DTX_N1
25
(13) PCIE_FRX_DTX_P1
27
29
31
(13) PCIE_FTX_C_DRX_N1
33
(13) PCIE_FTX_C_DRX_P1
35
+3VS_WLAN
37
39
41
43
100_0402_1%
45
R717
47
EC_TX_P80_DATA 1
2
49
(31,32) EC_TX_P80_DATA
EC_RX_P80_CLK 1
2
51
(31,32) EC_RX_P80_CLK
R718
100_0402_1%
53

(14,26) FCH_PCIE_WAKE#
(33) BT_ACTIVE

JUMP_43X79

Mini-Express Card(WLAN/WiMAX)
1

+1.5VS

+3VS_WLAN
J9

Reserve for SW mini-pcie debug card.


Series resistors closed to KBC side.
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
PCI_RST#_R
CLK_PCI_DB

R720
R721
R722
R723
R724
R725

1
1
1
1
1
1

@
@
@
@
@
@

2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
PLT_RST#

LPC_FRAME# (13,31)
LPC_AD3 (13,31)
LPC_AD2 (13,31)
LPC_AD1 (13,31)
LPC_AD0 (13,31)
CLK_PCI_DB

(13)

Compal Secret Data

Security Classification

Issued Date

2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Mini PCIE
Size

Document Number

Rev
1.0

LA6755P/7P
Date:

Compal Electronics, Inc.

Tuesday, November 30, 2010


E

Sheet

30

of

48

+3VALW
+EC_AVCC

KSI3
KSI4

KSO[0..17]
KSI[0..7]

(46)

KSI[0..7]

+3VALW
R737 1

2 47K_0402_5% KSO1

R738 1

2 47K_0402_5% KSO2

ENE UPDATE 08/10/21

(37)
(37)
(5,19,29)
(5,19,29)

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

(14) SLP_S3#
(14) SLP_S5#
(14) EC_SMI#

77
78
79
80

EC_SMI#

+3VS
INVT_PWM

1
R746

FSEL#SPICS#
2
@ 100K_0402_1%

XCLKI
XCLKO
2
0_0402_5%

1
R858

SUSCLK

122
123

R949
100K_0402_5%

change from 4.7K to 2.2K for PWR request


20101011

67

9
22
33
96
111
125

AVCC

VCC
VCC
VCC
VCC
VCC
VCC

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

PS2 Interface

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

SPI Flash ROM

GPIO
SM Bus

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

GPI

XCLK1
XCLK0

V18R

C1002
20P_0402_50V8

BATT_TEMP

(28)

ACOFF

(36,38)

TP_CLK

ADP_I

IREF

83
84
85
86
87
88

TP_CLK
TP_DATA

97
98
99
109

LID_SW#

POP for susclk implemented


20100810

119
120
126
128
73
74
89
90
91
92
93
95
121
127
100
101
102
103
104
105
106
107
108
110
112
114
115
116
117
118
124

KB930QF A0 LQFP 128P

FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#

CHARGE_LED0#
CAPS_LED#
CHARGE_LED1#
SYSON
ACIN

EC_LID_OUT#
EC_ON
ICH_POK_EC
BKOFF#

2 4.7K_0402_5%

TP_DATA R732 1

2 4.7K_0402_5%

BATT_TEMP

(38)

ACIN

IREF
(38)
CHGVADJ (38)

USB_ON#

R731 1

BATT_TEMP (37)

BRDID

SPI Device Interface

GND
GND
GND
GND
GND

FRD#SPI_SO
2
@ 100K_0402_1%

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

68
70
71
72

ACOFF

BEEP#

EC_MUTE#

(13)
1
R745

+3VALW

EC_TX_P80_DATA
EC_RX_P80_CLK

R727
10K_0402_5%
@
EC_FAN_PWM

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

(10)
INVT_PWM
(29)
EC_TACH
(46)
ODD_DA#
(30,32) EC_TX_P80_DATA
(30,32) EC_RX_P80_CLK
(34)
ON/OFF#
(29) EC_FAN_PWM
(34) NUM_LED#

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

DA Output

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

KSO[0..17]
(46)

1
C899
1
C900

20100727

+3VALW
R733 1

10K_0402_5%

+5VALW

EC_MUTE# (28)
USB_ON# (33,34)

USB_ON#

R734 1

CMOS_OFF# (10)
TP_CLK (46)
TP_DATA (46)

+3VALW

ID
Reserve for EMI for PVT build
20101005

@ C1010
1
2

BRD ID

R900

R901

Vab

R10 MP

0V

R03 PVT

100K

8.2K

0.25V

R02 DVT

100K

18K

0.5V

R01 EVT

100K

33K

0.82V

(44)
+3VS

D16
1

@
RB751V_SOD323
ICH_POK
2

R739
10K_0402_5%

ICH_POK (14)

EC_TACH

1
2
1
2
+3VS
R743 0_0402_5% R744 10K_0402_5%
@

SUSP#

ENBKL (10)
EAPD
(28)
NOVO#
(34)
SUSP# (35,40,42,43)
PBTN_OUT# (14)

@
C902
1000P_0402_50V7K

V18R
1

C901
4.7U_0603_6.3V6K
Change footprint
20100812

+3VALW

R740
10K_0402_5%

EC_SMB_CK1

R751

2 8.2K_0402_5%

100P_0402_50V8J

BKOFF# (10)
RF_LED# (46)
WL_OFF#_EC (30)
BT_OFF#_EC (33)

SUSP#
PBTN_OUT#
EC_PME#

2 100K_0402_5%

(19,38)

EC_RSMRST# (14)
EC_LID_OUT# (14)
EC_ON
(34,39)
BATT_SEL_EC (38)

Rb

VR_ON
ACIN

R900 1
R901 1

(32)
(32)
(32)
(32)

EC_PROCHOT# (5)
KILL_SW#_EC (46)
FSTCHG (38)
CHARGE_LED0# (46)
CAPS_LED# (34)
PWR_LED# (34,46)
CHARGE_LED1# (46)
SYSON
(35,41,42)

2 10K_0402_5%

Ra
BRDID

VGATE
(14,44)
CE_EN
(10)
APU_ALERT#_EC (5)
LID_SW# (46)
FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#

2
100P_0402_50V8J
2
100P_0402_50V8J

AD

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

63
64
65
66
75
76

+5VS
BEEP#

21
23
26
27

PWM Output

PWR function required


20101115

(46)
(46)

+3VALW

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

EC_SCI#
BATT_LEN#

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

U33

12
13
37
20
38

PLT_RST#
EC_RST#
EC_SCI#

AGND

(14)
(37)

2
C898
0.1U_0402_16V4Z

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

(13) LPC_CLK0_EC
(13,26,30) PLT_RST#

2
47K_0402_5%

1
2
3
4
5
7
8
10

69

10_0402_5%

ECAGND

1
R730

(14)
GATEA20
(14)
KB_RST#
(13)
SERIRQ
(13,30) LPC_FRAME#
(13,30) LPC_AD3
(13,30) LPC_AD2
(13,30) LPC_AD1
(13,30) LPC_AD0

11
24
35
94
113

+3VALW

C894
1000P_0402_50V7K

2
1
2
1
@ C897 22P_0402_50V8J @ R729

C893
1000P_0402_50V7K

2 1 ECAGND 2
FBM-11-160808-601-T_0603

1
L62

C892
0.1U_0402_16V4Z

C896
1000P_0402_50V7K

C891
0.1U_0402_16V4Z

+EC_AVCC

C890
0.1U_0402_16V4Z

C895
0.1U_0402_16V4Z

C889
0.1U_0402_16V4Z

L61 1
2
+3VALW
FBM-11-160808-601-T_0603

2.2K_0402_5%
EC_SMB_DA1

R752
2.2K_0402_5%

(26) LAN_WAKE#
@
1

+3VS

NC
Y8

OSC
@

@
C903
100P_0402_50V8J

2
15P_0402_50V8J
@

unpop for susclk implemented


20100823

PCI_PME#

+3VALW

@ Q98
2N7002_SOT23

changed
1
R923

C979
@
C904
100P_0402_50V8J

XCLKI

(14)

@
R860
20M_0603_5%
2

EC_SMB_CK2
EC_SMB_DA2

R922

FCH_RTCX2_OUT (13)

32.768KHZ_12.5PF_9H03200413
3 NC
OSC 4

2
0_0402_5%

XCLKO 1

@
R748
2.2K_0402_5%

2
@ 0_0402_5%

15P_0402_50V8J

If Q8 or R429, R432 implemented,


R747 & R748 need to be mounted
@
R747
2.2K_0402_5%

EC_PME#

2
0_0402_5%

1
R742

C978

1
R741

2
0_0402_5%

09.09.08

FCH_RTCX1_OUT (13)

Compal Secret Data

Security Classification
Issued Date

2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.


BIOS & EC I/O Port

Size Document Number


Custom
Date:

Rev
1.0

LA6755P/7P

Tuesday, November 30, 2010

Sheet

31

of

48

FOR EC 128KB SPI ROM


(150mil PACKAGE)
SA00003FL10
SA00003JD00

SPI_CLK_R

SPI_CLK_R

R960
0_0402_5%

+3VALW

C936
0.1U_0402_16V4Z

R758
10K_0402_5%

U35
(31) FRD#SPI_SO

FRD#SPI_SO

R759 1

1
@
C937
10P_0402_50V8J
2

(31) FSEL#SPICS#

FSEL#SPICS#
SPI_SO
2 15_0402_5%

1
2
3
4

CS#
DO
WP#
GND

VCC
HOLD#
CLK
DIO

8
7
6
5

MX25L2005CMI-12G SOP

20mils

Change from SD028150A80 to SM01000DI00


EMI solution after A phase 20100824

HOLD#
SPI_CLK_R
SPI_SI_EC

1 R760

2 15_0402_5%

SPI_CLK

1 R761

2 15_0402_5%

FW R#SPI_SI

1
C1004
12P_0402_50V8J

EMI requested after A test


20100817
R960 change to SD028330A80
C1004 change to SE071220J80
20100826

EMI

SPI_CLK (31)
FW R#SPI_SI (31)

FD6

FD5

FD8

FD7

EC DEBUG PORT
H_3P8
H1
HOLEA

H2
HOLEA

H3
HOLEA

H4
HOLEA

1
2
3
4

ACES_85205-0400
ME@

H_3P3

1
2
3
4

EC_TX_P80_DATA
EC_RX_P80_CLK

+3VALW
(30,31) EC_TX_P80_DATA
(30,31) EC_RX_P80_CLK

JECDP1

H_3P0x4P5N

H6
HOLEA

H_6P0

H16
HOLEA

H17
HOLEA

H15
HOLEA

H_2P8

H9
HOLEA

H7
HOLEA

H8
HOLEA

H13
HOLEA

H14
HOLEA

H_3P0N
H5
HOLEA

H_5P5N

H10
HOLEA

H11
HOLEA

H12
HOLEA

Compal Secret Data

Security Classification
2010/06/30

Issued Date

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


EC SPI ROM/LPC Debug Conn.

Size
B
Date:

Document Number

Rev
1.0

LA6755P/7P
Tuesday, November 30, 2010

Sheet
1

32

of

48

+5VALW

Low Active

L64
C942
@ 1000P_0402_50V7K

USB20_P3

USB20_N3

@
USB20_P3_C

USB20_N3_C

USB20_P2_C

WCM-2012-900T_4P
L65
USB20_P2

USB20_N2_C

(14)
(14)

1 0.1U_0402_16V4Z

OUT
OUT
OUT
OC#

USB_OC1# (14)

APL3510BKI_SO8

Low Active

C943
470P_0402_50V7K

C945
@ 1000P_0402_50V7K

D21
@

5
6
7
8

GND1
GND2
GND3
GND4

SUYIN_020173GR004M58BZL
ME@

1 0_0402_5%
1 0_0402_5%

ESATA and USB Conn.

USB20_N3_C
USB20_P3_C

1
2
3
4

VCC
DD+
GND

D20
@

5
6
7
8

GND1
GND2
GND3
GND4
SUYIN_020173GR004M58BZL
ME@

+USB_VCCC

GND
IN
IN
EN

8
7
6
5

1
2
3
USB_ON# 4

VCC
DD+
GND

JUSB2

2 R865
2 R864

USB20_N3
USB20_P3

USB20_P2_C
PJDLC05_SOT23-3

U37

1
2
3
4

W=80mils

USB20_N2_C

+USB_VCCC

D19
@

Left USB Conn.

WCM-2012-900T_4P

+5VALW

C944 2

USB20_N0
USB20_P0

1 0_0402_5% USB20_N0_C
1 0_0402_5% USB20_P0_C

C940
470P_0402_50V7K

+USB_VCCC
USB20_N2

JUSB1

2 R862
2 R863

( 220U 6.3V M V LESR15M VL H5.9 )*1


=(SF000001500)

(14)
(14)

C939
220U_6.3V_M

W=80mils

WCM-2012-900T_4P

USB_OC0# (14)

APL3510BKI_SO8

USB20_N0_C

10.1U_0402_16V4Z
(31,34) USB_ON#

+USB_VCCB

OUT
OUT
OUT
OC#

USB20_P0_C

PJDLC05_SOT23-3

C941

GND
IN
IN
EN

8
7
6
5

USB20_N0

U36

1
2
3
USB_ON# 4

Left USB Conn.

PJDLC05_SOT23-3

USB20_P0

L63

+USB_VCCB

W=80mils

+USB_VCCC

EMI request
1
C947
220U_6.3V_M

(15) SATA_ITX_DRX_P2
(15) SATA_ITX_DRX_N2
ESATA@
0.01U_0402_16V7K 2
1 C948 SATA_DTX_C_IRX_N2_C
0.01U_0402_16V7K 2
1 C949 SATA_DTX_C_IRX_P2_C

R768
R769
R770
R771

C946
470P_0402_50V7K

(14)
2
(14)

( 220U 6.3V M 6.3X4.2 )*1=(SF000002Y00)

(15) SATA_DTX_C_IRX_N2
(15) SATA_DTX_C_IRX_P2

1 ESATA@2
1
2
ESATA@
1 ESATA@2
1
2
ESATA@

JESAT1
0_0402_5%
USB20_N2_C
2 R866
1
USB20_P2_C
2 R867
1
0_0402_5%

USB20_N2
USB20_P2

0_0402_5%
0_0402_5%

SATA_ITX_DRX_P2_R
SATA_ITX_DRX_N2_R

0_0402_5%
0_0402_5%

SATA_DTX_C_IRX_N2_R
SATA_DTX_C_IRX_P2_R

ESATA@

OUT
GND

EN

SATA_ITX_DRX_P2
SATA_ITX_DRX_N2

1
2

RX_0P
RX_0N

VCC
VCC
VCC
VCC

SATA_DTX_C_IRX_P2_C
SATA_DTX_C_IRX_N2_C

5
4

TX_1P
TX_1N

D0
D1

JBT1

USB20_P5
USB20_N5

1
2
3
4
5
6

BTON_LED
BT_ACTIVE

BT_ACTIVE

1
2
3
4
5 G1
6 G2

3
13
17
18
19
21

7
8

ACES_87213-0600G
ME@

Issued Date

GND
GND
GND
GND
GND
PAD

6
10
16
20

C952
0.01U_0402_16V7K
1 @

C951
0.1U_0402_16V4Z
2 @

R775
4.7K_0402_5%
@

R776
4.7K_0402_5%
@

9
8

TX_0P
TX_0N

15
14

SATA_ITX_DRX_P2_R
SATA_ITX_DRX_N2_R

RX_1N
RX_1P

12
11

SATA_DTX_C_IRX_N2_R
SATA_DTX_C_IRX_P2_R

R777
0_0402_5%
@

R778
0_0402_5%
@

SN75LVCP412RTJR_QFN20_4X4
@

Compal Electronics, Inc.

Compal Secret Data


2010/06/30

Deciphered Date

2012/06/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

U38

Q100
1
BT@
0.1U_0402_16V4Z
AP2301GN-HF_SOT23-3 C953
BT@
2

+3VS

R774
4.7K_0402_5%

Security Classification

R943
0_0402_5%
@

30mils
3

Q101
DTC124EKAT146_SC59-3
@
(14)
(14)
IN 2
(30)

Change footprint
20100812

2
BT_LED#

(46)

FOX_3Q38111-RB1C3-7HC
SATA_DET#_R

+3VS

12
13
14
15

2
1

2
BT@
+3VS_BT

Q99
DTC124EKAT146_SC59-3
BT@

SHIELD
SHIELD
SHIELD
SHIELD

IN

ESATA

BT_OFF#_EC

1 R773
2
100K_0402_5%
BT@

+3VS

GND
A+
AGND
BB+
GND

USB
A+ = RXP
A- = RXN
B- = TXN
B+ = TXP

0.1U_0402_16V4Z

1)

GND

5)

@
2 R883
1
0_0402_5%
BT_OFF#
BT@
2 R884
1
0_0402_5%

C950

5
6
7
8
9
10
11

ME@
USB

R772
100K_0402_5%

OUT

@
2 R941
1
0_0402_5%

C998
0.1U_0402_16V4Z
1 @

20100728

BT@
20100728

ESATA@
1 R942
2
0_0402_5%

BT MODULE CONN

1
3

R902 2 ESATA@1 10K_0402_5%


(14) SATA_DET#

VBUS
DD+
GND

+3VS
+5VALW

1
2
3
4

USB/BT/eSATA
Size Document Number
Custom
Date:

Rev
1.0

LA6755P/7P

Tuesday, November 30, 2010

Sheet
E

33

of

48

ON/OFF switchSW 2
Power Button

Power Button Board Conn. 8pin


+3VALW

6
5

SMT1-05_4P

Card Reader/Audio Jack SB CONN

TOP Side

J11

+5VALW

@
2

R779
100K_0402_5%
D22

ON/OFFBTN#

ON/OFF#

51_ON#

ON/OFF# (31)

(31) NUM_LED#
(31) CAPS_LED#
(31,46) PW R_LED#
NOVO_BTN#
ON/OFFBTN#

51_ON# (36)

CHN202UGP_SOT323-3
Change footprint
20100812

D23
PJSOT24C 3P C/A SOT-23
@

Q102
2N7002H_SOT23-3

2
G

1
2
3
4
5
6
7
8
9
10

JCR1

1
2
3
4
5
6
7
8

HP_OUTL
HP_OUTR
PLUG_IN

1
2
3
4
EXT_MIC_L
5
EXT_MIC_R
6
MIC_JD
7
8
2 R908
1 0_0402_5% USB20_P6_C 9
2 R909
1 0_0402_5% USB20_N6_C 10
11
12
13
14

(28) HP_OUTL
(28) HP_OUTR
(28) PLUG_IN
(28) EXT_MIC_L
(28) EXT_MIC_R
(28) MIC_JD

GND
GND

+3VS

(14) USB20_P6
(14) USB20_N6

ACES_88058-080N
ME@

Change footprint
20100812

1
2
3
4
5
6
7
8
9
10
11
12
GND
GND

ACES_88058-120N
ME@

R780
10K_0402_5%

EC_ON

EC_ON

ON/OFFBTN#

NOVO_BTN#

L67

EMI REQUEST 1ST = SCA00000E00


2ST = SCA00000R00

USB20_P6

USB20_N6

USB20_P6_C

USB20_N6_C

W CM-2012-900T_4P

EMI request

+3VALW

R783
100K_0402_5%

+USB_VCCA

51_ON#

NOVO_BTN#

U39

1
2
3
USB_ON# 4

C954 0.1U_0402_16V4Z
2
1
(31,33) USB_ON#

3
CHN202UGP_SOT323-3
Change footprint
20100812

GND
IN
IN
EN

OUT
OUT
OUT
OC#

RIGHT USB PORT X1

8
7
6
5

USB_OC2# (14)

APL3510BKI_SO8

C957
@ 1000P_0402_50V7K

Right USB Conn.


+USB_VCCA

1
C956 +
220U_6.3V_M

W=80mils

+USB_VCCA
1

(14)
(14)

JUSB3

2 R868
2 R869

USB20_N4
USB20_P4

1
USB20_N4_C 2
USB20_P4_C 3
4
5
6

1 0_0402_5%
1 0_0402_5%

C955
470P_0402_50V7K

(220uF_6.3V_5.8L_ESR17m)*1=(SF000001500)

L66
USB20_P4

USB20_N4

USB20_P4_C

USB20_N4_C

1
2
3
4
G5
G6

ACES_85205-04001
ME@

NOVO#

D27
@

NOVO#

PJDLC05_SOT23-3

(31)

+5VALW

D25

(31,39)

Pin swap
20100810

JPW RB1

SHORT PADS

Bottom Side

W CM-2012-900T_4P

EMI request

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Other IO/USB (right)


Size
Document Number
Custom

Rev
1.0

LA6755P/7P

Date: Tuesday, November 30, 2010

Sheet

34

of

48

+VSB
1

1
C960
1U_0603_10V4Z

2
C967
0.1U_0603_25V7K

SUSP

2
G

Change footprint
20100812

D
Q107
S 2N7002H_SOT23-3

2 SUSP
G
Q104
2N7002_SOT23
@

S
100K_0402_5%
R789

3VS_GATE

R791
0_0402_5%
@

C968
0.1U_0603_25V7K

Change footprint
20100812

Change footprint
20100812
Change from SB00000GV00 to SB548000210
U43
+1.1VALW
+1.1VS
20101125
DMN3030LSS-13_SOP8L-8
8
1
7
2
1
1
1
6
3
C971
C972
C973
5
R801
10U_0805_10V4Z
10U_0805_10V4Z
1U_0603_10V4Z
2
2
2
470_0603_5%
@

SUSP# 2
G

R784
470_0603_5%
@

+5VALW

2
2

15VS_GATE_R

10K_0402_5%
Q106
2N7002H_SOT23-3

S
R788
47K_0402_5%

5VS_GATE2 R790
D

2
G

@
C959
10U_0805_10V4Z

D
2 SUSP
G
Q103
2N7002_SOT23
@

SUSP

R786
470_0603_5%
@

1
AP2301GN-HF_SOT23-3

R787
20K_0402_5%

1
C958
10U_0805_10V4Z

+VSB

1
R785
470_0603_5%
@

+1.5VS

Q126
3

C963
1U_0603_10V4Z

Change footprint
20100812
+1.5V

C962
10U_0805_10V4Z

+1.5V to +1.5VS

1 2

C961
10U_0805_10V4Z

U42
+3VALW
+3VS
DMN3030LSS-13_SOP8L-8
8
1
7
2
1
1
1
6
3
C964
C965
C966
5
10U_0805_10V4Z
10U_0805_10V4Z
1U_0603_10V4Z
2
2
2

+5VS

DMN3030LSS-13_SOP8L-8
8
1
7
2
6
3
5

Change from SB00000GV00 to SB548000210


20101125
Change footprint
20100812

+3VALW TO +3VS

1 2

U41

+5VALW

Change from SB00000GV00 to SB548000210


20101125
Change footprint
20100812

+5VALW TO +5VS

1
2
R792
75K_0402_5%
Q108
2N7002H_SOT23-3

2 SUSP
G
Q105
2N7002_SOT23
@

1.5VS_GATE
1
1
@
C969
C970
0.1U_0603_25V7K
2
2
0.1U_0603_25V7K

Change footprint
20100812

+1.1ALW to +1.1VS

+RTCBATT

+5VALW

IN

(31,41,42) SYSON

SYSON

IN

2
1
OUT
GND

2
OUT

(31,40,42,43) SUSP#

Q117
S 2N7002H_SOT23-3

2 SUSP
G
Q116
2N7002_SOT23
@

@
R800
100K_0402_5%
SYSON#
Q115
DTC124EKAT146_SC59-3
@

GND

Q114
DTC124EKAT146_SC59-3

1.1VS_GATE
R803
0_0402_5%

2
1

2
G

SUSP

SUSP

S
R802
75K_0402_5%

SUSP

(42)

+5VALW

@
R799
100K_0402_5%

R798
100K_0402_5%

+5VALW

C975
0.1U_0603_25V7K

Change footprint
20100812

1
R797
470_0603_5%
@

D
2 SYSON#
G
Q110
2N7002_SOT23
@

1 2

+0.75VS

R796
470_0603_5%
@

D
2 SUSP
G
Q113
2N7002_SOT23
@

2 SUSP
G
Q112
2N7002_SOT23
@

1 2

D
2 SUSP
G
Q109
2N7002_SOT23
@

R794
470_0603_5%
@

1 2

1 2

R793
470_0603_5%
@

+1.0VS

+1.5V

+1.8VS

2010/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

DC Interface
Size Document Number
Custom
Date:

Rev
1.0

LA6755P/7P

Tuesday, November 30, 2010

Sheet
E

35

of

48

VIN

DC030006J00
PF101
7A_24VDC_429007.WRML
APDIN
1
2 APDIN1

Precharge detector
15.97V/14.84V FOR
ADAPTOR

PL101
SMB3025500YA_2P
1
2

PreCHG
PR102
1K_1206_5%
1
2

PD102
2

PR107 @
1K_1206_5%
1
2

PQ103
PDTC115EU_SOT323-3
@

(39)

+5VALWP

@
RB715F_SOT323-3

B+

PC106
0.1U_0603_25V7K

PC107
2
1

1
@

+3VLP

@
2N7002W-T/R7_SOT323-3

PR119
34K_0402_1%
@
2
1

PD106
RB751V-40_SOD323-2

PC110
0.01U_0402_25V7K

ML1220T13RE
45@

PC108
0.1U_0603_25V7K @

2
1
PR116
499K_0402_1%

+CHGRTC

6251VREF

PQ105
2
G

PR120
(38)
47K_0402_5%
2
1

PACIN

@ RB715F_SOT323-3

ACON

1
PR115
205K_0402_1%

+RTCBATT

(38)

PRG++ 2

PR118
560_0603_5%
1
2

PR117
560_0603_5%
1
2

1
3
+RTCBATT

PU101A
LM393DG_SO8
1 O

2
PD105

PR114
100K_0402_1%

MAINPWON

PC109
1000P_0402_50V7K

VS

2
1
PR113
499K_0402_1%

PR111
2.2M_0402_5%
2
1

(37,39)

JRTC1

VL

VS

PQ104
PDTC115EU_SOT323-3
@

0.01U_0402_25V7K

51_ON#

PC105
0.22U_0603_25V7K
2
1

1
(34)

PR112
22K_0402_5%
1
2

PR110
100K_0402_5%

PR109
68_1206_5%

ACOFF

PQ101
TP0610K-T1-E3_SOT23-3
N1

PR101
68_1206_5%
C

(31,38)

1 2

PD103
1

BATT+

2
1

@
@

@
PD101
LL4148_LL34-2

PD104
LL4148_LL34-2
2
1

PR108
100K_0402_1%

PR104 @
1K_1206_5%
1
2

VIN

LL4148_LL34-2
@

PR103 @
1K_1206_5%
1
2

PR106
100K_0402_1%
2
1

VIN

PQ102
TP0610K-T1-E3_SOT23-3

PR105
100K_0402_1%
2
1

1
2

PC104
1000P_0402_50V7K

1
2

@ 4602-Q04C-09R 4P P2.5
JDCIN1

PC103
100P_0402_50V8J

PC102
100P_0402_50V8J

PC101
1000P_0402_50V7K

PQ106
@ PDTC115EU_SOT323-3
@
2

2
@

PR121
@
66.5K_0402_1%

+5VALWP

ACIN
Precharge detector
Min.
typ.
Max.
L-->H 14.991V 15.381V 15.782V
H-->L 13.860V 14.247V 14.621V

Compal Secret Data

Security Classification
Issued Date

BATT ONLY
Precharge detector
Min.
typ.
Max.
L-->H 7.196V 7.349V 7.505V
H-->L 6.138V 6.214V 6.056V

2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


DCIN / Vin Detector /Pre-charge

Size Document Number


Custom
Date:

Rev
0.1

PAWGC

Tuesday, November 30, 2010

Sheet
1

36

of

47

VMB2
1
2
3
4
5
6
7
8
9

PH1 under CPU botten side :


CPU thermal protection at 92 degree C
Recovery at 56 degree C

PL201
SMB3025500YA_2P
1
2

BATT+
D

1
2

PC201
1000P_0402_50V7K

PC202
0.01U_0402_25V7K

VL

PR205
@ 100K_0402_1%
1

PU201
1

VCC TMSNS1

8
2

EC_SMB_CK1 (31)

1
PR204
21.5K_0402_1%
<BOM Structure>
2

2
PR203
10K_0402_1%
1

PC203
0.1U_0603_25V7K

VL

TYCO_1775789-1
@

2
1
PR202
100_0402_1%

EC_SMCA
EC_SMDA
2
1
PR201
100_0402_1%

1
2
3
4
5
6
7
GND
GND

VMB
PF201
12A_65V_451012MRL
1
2

JBATT1
D

A/D

BATT_TEMP (31)

PR206
9.76K_0402_1%
<BOM Structure>

6
1

OT2 RHYST2

G718TM1U_SOT23-8

1
2
PR209
10K_0402_5%
<BOM Structure>

PH201
100K_0402_1%_TSM0B104F4251RZ
<BOM Structure>
MAINPWON (36,39)

+3VALW

OT1 TMSNS2

1
2
PR207
6.49K_0402_1%
<BOM Structure>

EC_SMB_DA1 (31)

GND RHYST1

1
2
PR208
@ 47K_0402_1%

PH202
@ 100K_0402_1%_TSM0B104F4251RZ

+3VS

2
PR211
10K_0402_1%
<BOM Structure>
1

PR210
100K_0402_1%
<BOM Structure>
2

BATT_OUT (38)

PQ202
TP0610K-T1-E3_SOT23-3

(31) BATT_LEN#
6251VREF

PR218
22K_0402_1%
1
2

VL

+VSBP

PC206
0.1U_0603_25V7K

PR217
10K_0402_1%
<BOM Structure>

PQ204
D 2N7002KW_SOT323-3

2
G
3

1
1

B+
S

2
G

PC205
0.22U_0603_25V7K

PU101B
LM393DG_SO8

2
1
PR216
100K_0402_1%

O
-

PR219
100K_0402_1%

SPOK

PR220
1K_0402_5%
2

(39,40)

D
PQ203
2N7002W-T/R7_SOT323-3

2
G
3

PC207
1U_0402_6.3V6K

PR215
232K_0402_1%

+3VALW

PQ201
2N7002KW_SOT323-3
D

PR214
10K_0402_1%
1
2

PR213
5.1M_0402_5%
1

PR212
649K_0402_1%

VMB2

PC204
0.01U_0402_25V7K

VS

PJ201
@ JUMP_43X39
1 1
2 2

+VSBP

+VSB

Compal Secret Data

Security Classification
Issued Date

2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


BATTERY CONN/OTP

Size Document Number


Custom
Date:

Rev
0.1

PAWGC

Tuesday, November 30, 2010

Sheet
1

37

of

47

B+

P3
P2

ICOMP

CSIN

20

6251_VCOMP

VCOMP

CSIP

19

ICM

PHASE

18

PC325
10U_0805_25V6K
2
1

1
PC324
10U_0805_25V6K
2

2ACOFF-1

1DISCHG_G-1
1

2200P_0402_50V7K

PC311
0.1U_0603_25V7K
2
1

2N7002W -T/R7_SOT323-3
2 PACIN
G

PR323
0.02_1206_1%

BATT+

12

ACLIM

VDDP

15

VADJ

LGATE

14

PGND

13

GND

PR327
0_0603_5%
BST_CHG 1

PC317
0.1U_0603_25V7K
2 BST_CHGA 2
1
PD302

6251_VDDP
DL_CHG

RB751V-40_SOD323-2
1
26251_VDD
PR330
4.7_0402_5%
PC322
4.7U_0805_6.3V6K

PC319
10U_0805_25V6K
2
1

16

PC323
10U_0805_25V6K
2
1

BOOT

PC318
10U_0805_25V6K
2
1

CHLIM

DH_CHG

PR325
4.7_1206_5%

10

6251_VADJ
11

17

PR332
15.4K_0402_1%
1
2

(31) CHGVADJ

PC321
680P_0603_50V7K

PR331
2.2K_0402_1%

UGATE

16251_SN
2

VREF

6251VREF

Connect to EC A/D Pin.

5
6
7
8
8

ISL6251AHAZ-T_QSOP24
B

2
G
@

PL301
10U_LF919AS-100M-P3_4.5A_20%
<BOM Structure>
1
2 CHG
1
PQ314
AO4466L_SO8

1
2
6251VREF
PC316
6251_CHLIM
0.1U_0402_16V7K
PR328
21K_0402_1%
1
2 6251_ACLIM

ACPRN

1
PR329
100K_0402_1%

PD304
1SS355_SOD323-2
2

PQ312
2N7002W-T/R7_SOT323-3

6251_ICOMP

CSOP

21

CSOP

CSON

PQ311
AO4466L_SO8

6251_CSON
PC312
0.047U_0402_16V7K
6251_CSOP 1
2
PR317
20_0402_5%
6251_CSIN
2
1
PC314
PR319
0.1U_0402_16V7K
20_0402_5%
6251_CSIP
1
2
PR321
2_0402_5%
LX_CHG

2
G

IREF

PR326
154K_0402_1%
2
1
<BOM
Structure>

1
1

BATT_OUT

(31)

2N7002KW_SOT323-3

PR342
0_0402_5%

PQ315

CELLS

@
PR316
20_0402_5%
1
2

22

CSON

1
26251_ICM
PR322
100_0402_1%

ADP_I

PQ310

EN

ACPRN

100K_0402_5%
PC310
2
1

23

PR314
1

ACSET ACPRN

(31)

PC309
0.1U_0603_25V7K
6251_DCIN
2
1

CELLS

PR324
10k_0402_5%

2
ACOFF-1

24

0.01U_0402_25V7K

PC320
0.01U_0402_25V7K
2
1

ACOFF

2
2

(31,36)

10K_0402_1%
2

DCIN

5
6
7
8

6251_EN

VDD

3
2
1

PC315
PR320
1
26251_VCOMP-1
1

PQ313
PDTC115EU_SOT323-3

PR308
200K_0402_1%

ACSETIN

6800P_0402_25V7K
2

1 1
PU301

3
2
1

ACON

(36)

PC313
1

PD303
1SS355_SOD323-2

PQ307
PDTC115EU_SOT323-3
<BOM Structure>
2

PQ308B
2N7002KDW -2N_SOT363-6

VIN

PR307
10K_0402_1%

PC307
1000P_0402_25V8J

PR315
2

P2-2
PR318
47K_0402_1%
1
2

PACIN

PACIN

(36)

PR310
14.3K_0402_1%

PQ309
2N7002KW _SOT323-3

ACSETIN

PR305
47K_0402_1%
1
2

BATT_ON

BATT_OUT

100K_0402_1%

2
G

PR311
10_1206_5%

DISCHG_G

PR312
10K_0402_1%
12

1
1

PQ308A
2N7002KDW -2N_SOT363-6

PR313
150K_0402_1%

(31) FSTCHG

6251_VDD
PC308
2.2U_0603_6.3V6K
1
2

PR309
0_0402_5%
2
1

PD301
RB751V-40_SOD323-2

P2-1

@ PR306
191K_0402_1%

2N7002KDW -2N_SOT363-6
@

8
7
6
5

BATT_OUT (37)

BATT_ON

PR301

2
PQ306
PDTC115EU_SOT323-3

PQ303
AO4407A_SO8
1
2
3

PreCHG

PC305
2200P_0402_50V7K

VIN

PC306
4.7U_0805_25V6-K
1 Structure>
2
<BOM

CSIN
CSIP

PC304
4.7U_0805_25V6-K
1 Structure>
2
<BOM

1.2UH_1231AS-H-1R2N=P3_2.9A_30%

PQ305B
2N7002KDW -2N_SOT363-6
@

PC303
4.7U_0805_25V6-K
1
2

PQ305A

191K_0402_1%

1
2

PR303
47K_0402_1%
@

CHG_B+

PL302

VIN

1
2

PQ304
PDTA144EU

PC301
0.1U_0603_25V7K
2
1
PR304
200K_0402_1%

1
PR343
47K_0402_5%

PR302
0.02_1206_1%

8
7
6
5

1
2
3

1
2
3

8
7
6
5

PC302
0.1U_0603_25V7K

VIN

PQ302
SI4459A_SO8

PC326
5600P_0402_25V7K

PQ301
AO4407A_SO8

<BOM Structure>
PR333
31.6K_0402_1%

CHGVADJ=(Vcell-4)/0.10627
CHGVADJ

UMA CP mode (40W*85%)


(39)
Vaclim=2.39*((31.6K//152K)/(31.6K//152K+12.1K//152K))=1.6731V
Iinput=(1/0.05)((0.05*Vaclim)/2.39+0.05)
where Vaclim=1.6731V, Iinput=1.7A

ACPRN

ACPRN

1
3

1
6
PR339
0_0402_5%
2

PQ317
PDTC115EU_SOT323-3
PR341

PR302=20mohm

1
PR340
@ 0_0402_5%

(31) BATT_SEL_EC

2
2

VCHLIM need over 95mV

CELLS

PACIN

14.3K_0402_1%
PQ316A
@ 2N7002KDW -2N_SOT363-6

PQ316B
@ 2N7002KDW -2N_SOT363-6

IREF=0.254V~3.048V

(19,31)

PR331=2.2K

IREF=1.016*Icharge

ACIN

PR334
PR335
@ 100K_0402_1% @ 100K_0402_1%

CC=0.25A~3A

PR338
10K_0402_1%

PR336
47K_0402_1%

PR328=21K

PR337
10K_0402_1%
1
2

3.2935V

6251_VDD

4.35V

4cell : VDD
3cell : GND

6251_VDD

DIS CP mode (65W*85%)


Vaclim=2.39*((2.2K//152K)/(2.2K//152K+21K//152K))=0.25136V
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05)
where Vaclim=0.25136V, Iinput=2.76293A

1.882V

1 2

0V

4.2V

4V

6251_VDD

Vcell

PR328=12.1K(SD034121280)
PR331=31.6K(SD034316280)
PR302=50mohm(SD00000CI10)

2010/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

CHARGER
Size

Document Number

Rev
0.1

PAWGC
Date:

Tuesday, November 30, 2010

Sheet
1

38

of

47

Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO

2VREF_8205

PJ402

+3VALW P

+3VALW

PC402
1U_0603_10V6K

@ JUMP_43X118

PJ403

+5VALW P

RT8205_B+

PR404
20K_0402_1%
1
2

+5VALW

RT8205_B+

LGATE1

19

LG_5V

RT8205EGQW _W QFN24_4X4

3
2
1
PQ404

18

17

16

LGATE2

AO4456_SO8

3
2
1
PC418
1U_0603_10V6K
2
1

RT8205_B+

2
PC420
0.1U_0603_25V7K

PQ405B
2N7002KDW -2N_SOT363-6

2VREF_8205
4

PC419
4.7U_0805_10V6K

VL

Typ: 175mA

PR410
4.7_1206_5%

12

4.7UH_PCMB104E-4R7MS_10A_20%
PL402
1
2

LG_3V

AO4406AL_SO8

+5VALWP

<BOM Structure>
PC417
680P_0603_50V7K

LX_5V

NC

UG_5V

20

13

5
6
7
8

PC410
0.1U_0603_25V7K
2
1

PC409
2200P_0402_50V7K
2
1

PC408
4.7U_0805_25V6-K
2
1

1
ENTRIP1

21

PHASE1

VREG5

UGATE1

PHASE2

VIN

UGATE2

11

GND

10

LX_3V

SKIPSEL

UG_3V

(37,40)

1
2

PR413
100K_0402_1%

ENTRIP2

PR408 PC413
0_0603_5% 0.1U_0603_25V7K
BST_5V 1
2 1
2

SPOK

B+

PQ403
AON7702L

FB1

FB2

22

PR412
499K_0402_1%
1
2

ENTRIP1

PQ405A
2N7002KDW -2N_SOT363-6

PC407
4.7U_0805_25V6-K
2
1

ENTRIP1

ENTRIP2

23

BOOT1

1
2
3

PC415
680P_0603_50V7K
2
1

PGOOD

BOOT2

PR411 @
0_0402_5%
MAINPW ON 2
1

PR414
0_0402_5%
2
1

VREG3

VFB=2.0V

5
6
7
8

PQ402

4
24

<BOM Structure>

150U_B2_6.3VM_R45M
2

(36,37) MAINPWON

PR406
121K_0402_1%
2

VO1

15

PC414

VO2

EN

PR409
4.7_1206_5%
2
1

4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
PL401
1
2

BST_3V

14

1
2
3

PR407
2 1
2
0_0603_5%
PC412
0.1U_0603_25V7K

+3VALWP

P PAD

REF

25

TONSEL

PU401

ENTRIP2

PR405
110K_0402_1%
1
2

PQ401
4 AON7408L

PC411
4.7U_0805_10V6K

PC422
0.1U_0603_25V7K

PR403
20K_0402_1%
1
2

+3VLP

1
PC406
2200P_0402_50V7K
2
1

PC405
4.7U_0805_25V6-K
2
1

@ JUMP_43X118

PC404
4.7U_0805_25V6-K
2
1

PR402
30K_0402_1%
1
2

Typ: 175mA

PJ401

PC403
0.1U_0603_25V7K
2
1

PC401
680P_0402_50V7K
2
1

B+

PR401
13K_0402_1%
1
2

JUMP_43X118

PC416

150U_B2_6.3VM_R45M
2

PR415
100K_0402_1%
2
1

VL

TONSEL=VREF (1)SMPS1=300KHZ(+5VALWP)
(2)SMPS2=375KHZ(+3VALWP)

PR417
100K_0402_1%

PQ408
PDTC115EU_SOT323-3

+3.3VALWP
Iocp=5.81A

2
PC421
2.2U_0603_10V7K

VS

EC_ON

PQ406
PDTC115EU_SOT323-3

2
1
PR418
40.2K_0402_1%

1
1

Compal Secret Data

Security Classification
2010/06/30

Issued Date
3

(31,34)

2
G
3

ACPRN

PR416
200K_0402_1%
2
1

PQ407
2N7002W-T/R7_SOT323-3

+5VALWP
Iocp=19.306A

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

Compal Electronics, Inc.


3VALWP/5VALWP

Size
Document Number
Custom
Date:

Rev
0.1

PAWGC

Tuesday, November 30, 2010

Sheet
1

39

of

47

PR501
255K_0402_1%
1
2

10
9

1
PQ502
2

+5VALW

DL_1.1V

4
1

PGND

LGATE

RT8209BGQW_WQFN14_3P5X3P5

GND
7

PC506
4.7U_0603_6.3V6K

PGOOD

2
PR506
15K_0402_1%

PC508
4.7U_0805_10V6K

AO4712L_SO8

PR507
P_R
1

+1.1VALW

@ JUMP_43X118

PC501
4.7U_0805_25V6-K

+1.1VALWP

1
+

+1.1VALWP
Iocp=7.21A

+1.1VALWP

PC505
220U_6.3V_M

VDDP

PR504
4.7_1206_5%

NC

FB

3
2
1

11

0.1U_0603_25V7K

15

14
CS

LX_1.1V

VDD

DH_1.1V

12

PC507
680P_0603_50V7K

13

PHASE

UGATE

5
6
7
8

VOUT

PJ502

3
2
1

+5VALW

TON

B+

PL501
2.2UH_FMJ-0630T-2R2 HF_8A_20%
1
2

PC504
1

2
PR505
100_0603_1%
1
2

PU501

EN/DEM

PC503
@.1U_0402_16V7K

AO4466L_SO8

BST_1.1V

BOOT

SPOK

PR503
2.2_0603_5%
1
2
1

(37,39)

PQ501

PR502
0_0402_5%
1
2

@ JUMP_43X118

1
2

5
6
7
8
D

PC502
4.7U_0805_25V6-K

PJ501
1.1VALW_B+

PR508
10K_0402_1%

PJ503

DL_1.0V

1
5
6
7
8

+5VALW
2

2
PR515
10K_0402_1%

PQ504

RT8209BGQW_WQFN14_3P5X3P5

4
PC516
4.7U_0805_10V6K

AO4456_SO8

+1.0VS
B

+1.0VSP
Iocp=14.74A

PC510
4.7U_0805_25V6-K

+1.0VSP

1
+
2

PR516
3.74K_0402_1%
1
2

@ PR513
4.7_1206_5%

10

PC513
220U_6.3VM_R15

LGATE

PGND
8

GND

PGOOD

PC514
4.7U_0603_6.3V6K

0.1U_0603_25V7K

VDDP

LX_1.0V

12
11

FB

3
2
1

14

NC

CS

DH_1.0V

13

PHASE

VDD

PL502
2.2UH_FMJ-0630T-2R2 HF_8A_20%
1
2

PC512
BST_1.0V

UGATE

VOUT

B+

@ JUMP_43X118

@ PC515
680P_0603_50V7K

AO4406AL_SO8

3
2
1

+1.0VSP

PR514
100_0603_1%
1
2

+5VALW

TON

@ JUMP_43X118

PJ504

BOOT

15

PU502

PC511
.1U_0402_16V7K

PR518
47K_0402_5%

4
PR512
0_0603_5%
1
2

(18,20,43) VGA_PWRGD

PR510
255K_0402_1%
1
2

PR511
100K_0402_1%
1
2
@

EN/DEM

(31,35,42,43) SUSP#

1
2

5
6
7
8
PQ503
PR509
100K_0402_1%
1
2

PC509
4.7U_0805_25V6-K

1.0V_B+

PR517
10K_0402_1%
A

Compal Secret Data

Security Classification
2010/06/30

Issued Date

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


+1.1VALWP/+1.0VSP

Size

Document Number

Rev
0.1

PAWGC
Date:

Tuesday, November 30, 2010

Sheet
1

40

of

47

PJ601

PR603
267K_0402_1%
1
2

+1.5VP

PR606
4.7_1206_5%

10
DL_1.5V

PC606
220U_B2_2.5VM_R15M

RT8209BGQW_WQFN14_3P5X3P5

PC608
680P_0603_50V7K

AO4456_SO8

PC610
4.7U_0603_6.3V6K
<BOM Structure>

4
PC607
4.7U_0805_10V6K

3
2
1

1
PQ602
+5VALW

LGATE

LX_1.5V

11

PGOOD

VDDP

12

B+
@ PC604
@PC604
680P_0402_50V7K

PL601
1UH_FDUE1040D-1R0M-P3_21.3A_20%
1
2

5
6
7
8

14

NC

BOOT

15

FB

CS

+5VALW

@ PC609
@PC609
47P_0402_50V8J
1
2

PHASE

VFB=0.75V

DH_1.5V

6
PR607
100_0603_5%
1
2

VDD

13

AO4406AL_SO8

PR604
PC605
2.2_0603_5%
0.1U_0603_25V7K
1
2BST_1.5V-1 1
2

PR608
9.76K_0402_1%

VOUT

PGND

BST_1.5V

UGATE

TON

GND

EN/DEM

PU601
PC601 @
.1U_0402_16V7K

2
1

PR605
47K_0402_5%

3
2
1

(31,35,42) SYSON

JUMP_43X118

PR601
0_0402_5%
1
2

PQ601

2
PC603
4.7U_0805_25V6-K
2
1

PC602
4.7U_0805_25V6-K
2
1

5
6
7
8

1.5_51117_B+

PR609

2
10K_0402_1%

PR610
10K_0402_1%

PJ602
+1.5VP

2
@

+1.5V
1

JUMP_43X118

+1.5VP
Iocp=15.6A

Compal Secret Data

Security Classification
2010/06/30

Issued Date

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


1.5VP

Size

Document Number

Rev
0.1

PAWGC
Date:

Tuesday, November 30, 2010

Sheet
1

41

of

47

+1.5V
D

PJ701
JUMP_43X79
@

PU701

VREF

NC

VOUT

NC

TP

+3VALW
PJ702
PC702

+0.75VSP

1U_0603_10V6K

+0.75VS

JUMP_43X118

PC706
1
2

+0.75VSP

10U_0603_6.3V6M

10U_0603_6.3V6M

PC705
1
2

PR703

PC703
0.1U_0402_16V7K
2
1

2
G
2

NC

G2992F1U_SO8

@ PC704
1U_0402_6.3V6K

PR701
0_0402_5%
1
2

PQ701
2N7002W-T/R7_SOT323-3

(35) SUSP

VCNTL

GND

PR702
1K_0402_1%

1K_0402_1%

(31,35,41) SYSON

VIN

@ PR709
@PR709
0_0402_5%
1
2

PC701
4.7U_0805_6.3V6K

62K_0402_1%

SY8033BDBC_DFN10_3X3

+1.8VS

FB_1.8V

PR707
1M_0402_5%

PC712
0.1U_0402_10V7K

PR706

NC

TP

FB=0.6Volt

EN_1.8V

JUMP_43X118

PC711
22U_0805_6.3VAM

(31,35,40,43) SUSP#

FB
EN

11

PR705
30K_0402_1%

SVIN

2
@

LX

PJ704
+1.8VSP

+1.8VSP

PC710
22U_0805_6.3VAM

PL701
1UH_FMJ-0630T-1R0 HF_11A_20%
1
2
PC708
68P_0402_50V8J
2
1

PC707
22U_0805_6.3VAM

PVIN

LX_1.8V

LX

JUMP_43X118

PVIN

PC709
PR704
680P_0603_50V7K 4.7_1206_5%

10

1 2

NC

PG

PU702
PJ703

+5VALW

PR708
14.7K_0402_1%

Compal Secret Data

Security Classification
2010/06/30

Issued Date

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


0.75VP/1.8VP

Size

Document Number

Rev
0.1

PAWGC
Date:

Tuesday, November 30, 2010

Sheet
1

42

of

47

PD804
@ RB751V-40_SOD323-2
1
2
+3VS

RT8209BGQW _W QFN14_3P5X3P5

2
PC812
@ 47P_0402_50V8J
1
2

0_0402_5%

PC810
4.7U_0805_6.3V6K
<BOM Structure>

PC809
10U_0805_6.3V6M

PC808
10U_0805_6.3V6M

+
2

LG_VGA

PC807
10U_0805_6.3V6M

LGATE

+5VALW

+VGA_COREP

10

VDDP

VGA_TRIP
1
2
PR806
9.1K_0402_1%

PR807
4.7_1206_5%

3
2
1

BOOT

SW _VGA

11

PR832
1

(18,20,40) VGA_PW RGD

NC

12

CS

B+

PC805
330U_6.3V_M

PGOOD

PHASE

1VGA_SNB
2

6
PR824
100K_0402_1%

UG_VGA

PL801
0.56UH +-20% PCMC104T-R88MN 20A
1
2

FB

13

@ JUMP_43X79

UGATE

VGA_FB

PGND

VDD

VOUT

14

3
VGA_V5FILT
+3VS

PC806
4.7U_0603_6.3V6K
<BOM Structure>

EN/DEM

TON

GND

15

0.1U_0603_25V7K

PR808
100_0603_1%
1
2
1

PC811
680P_0603_50V7K

PR805
PC804
0_0603_5%
BST_VGA 1<BOM Structure>
2BST_VGA-1
1
2

PC803
4.7U_0805_25V6-K
2
1

@ PR831
47K_0402_5%

PU801

+5VALW

PD801
1SS355_SOD323-2
2
+5VALW

PC802
4.7U_0805_25V6-K
2
1

PC801
0.1U_0402_16V7K

100K_0402_1%

PQ801
TPCA8065-H_SOP-ADV8-5

VGA_EN
1

@ PR804
1

(31,35,40,42) SUSP#

PJ801
VGA_IN

@ PR801
100K_0402_1%
2
1

(20,21) PX_MODE

PR803
205K_0402_1%
1
2

VGA_TON

PQ802
TPCA8059-H_SOP-ADVANCE8-5

PR802
@ 10K_0402_5%

3
2
1

PD805 @
RB751V-40_SOD323-2

(13,20,21) PE_GPIO1

PR823
100K_0402_1%
2
1

2
PR809
2K_0402_1%
1
2
PR810
10K_0402_1%

PR813
10K_0402_1%

GVID1-2

PJ802
VGA_PWRSEL0

VGA_PWRSEL1

GPU_VID0

GPU_VID1

PR815
8.66K_0402_1%
2

Core Voltage Level

+VGA_CORE

PJ803

0.9V

0.95V

1.12 V

@ JUMP_43X118

PQ804A
2
PC814
2N7002KDW -2N_SOT363-6
0.022U_0402_16V7K

+1.0VGS

1
2
FB

VIN

+VGA_PCIEP

PR830
1.15K_0402_1%

APL5912-KAC-TRL_SO8

@
@

PR828
4.53K_0402_1%

VGA_PCIE

1.0V

1.1 V

PR828

4.53K

3K

PC817
0.01U_0402_25V7K

22U_0805_6.3V6M

PC818
2
1

VOUT

VCNTL

VIN
VOUT

EN

PR827
@ 47K_0402_5%

GND

POK

1
1

PR829
@ 40.2K_0402_1%
1
2

@ RB751V-40_SOD323-2

2
2

PD803

PC816
4.7U_0805_6.3V6K

SUSP#

PU802

PC819
0.1U_0603_25V7K
2
1

(31,35,40,42) SUSP#

@
6

PR825
@ 0_0402_5%
PR826
@ 40.2K_0402_1%
1
2

PE_GPIO1

JUMP_43X79
@

@ RB751V-40_SOD323-2
1
2

(13,20,21) PE_GPIO1

PC815
1U_0402_6.3V6K

PD802

+VGA_PCIEP

PJ805
JUMP_43X79
@

+5VALW

PJ804

+5VALW

PR820
@ 10K_0402_5%

+VGA_COREP
Iocp=23.38A

+1.5VGS

6
2
PR819
10K_0402_1%

10K_0402_1%

PR818

PR822
3K_0402_5%

1GVID0-1

(19) GPU_VID0

2
1
PR821
10K_0402_1%

PQ804B
2N7002KDW -2N_SOT363-6

@ JUMP_43X118

GVID0-2
1

PR817
3K_0402_5%

<BOM Structure>
+3VALW

2
1 5
PR816
10K_0402_1%

Robson XT

PC813
0.022U_0402_16V7K
4

(19) GPU_VID1

PQ803A
2N7002KDW -2N_SOT363-6
1

PR814
@ 10K_0402_5%

PR811
30K_0402_1%
2

+VGA_COREP

1GVID1-1 2

2
PQ803B
2N7002KDW -2N_SOT363-6

1
PR812
2

10K_0402_1%

+3VALW

2010/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

VGA_COREP
Size

Document Number

Rev
0.1

PAWGC
Date:

Tuesday, November 30, 2010

Sheet
1

43

of

47

PL901
HCB2012KF-121T50_0805

CPU_B+
PC901
33P_0402_50V8J
2
1

PR906
2_0603_5%

PR911
27.4K_0402_1%
2
1

PR923
0_0402_5%

PR925
95.3K_0402_1%
2
1

SVC

PGND0
LGATE0

ISL6265CHRTZ-T_TQFN48_6X6

RBIAS

OCSET

LGATE1

VDIFF0

PGND1

UGATE0

33

PHASE0

32

1 2
3
2
1
4

+5VS
LGATE0

31
30
29
28

PC918
1U_0603_16V6K

LGATE0

PVCC

34

PC905
4.7U_0805_25V6-K
2
1

PC914
4.7U_0805_25V6-K
2
1

PC923
68U_25V_M_R0.36

PC913
4.7U_0805_25V6-K
2
1

PC912
4.7U_0805_25V6-K
2
1

@ PR920
4.7_1206_5%

PR922
9.31K_0402_1%

@PC916
@PC916
680P_0603_50V7K

PC917
2
1
0.1U_0603_16V7K
2

27

APU_VDD0_RUN_FB_L

26

TP

25

ISN0

VSEN0

+1.5VS

1
PR931
0_0402_5%

+CPU_CORE
Iocp~15A

VW0

PR933
PC919
255_0402_1% 2200P_0402_25V7K
FB_0
2
1 2
1

COMP0

PC920
180P_0402_50V8J
PR934
1K_0402_5%
2
1

PR935
2

PC922
2
1

PC921
1000P_0402_50V7K
4

PR936
6.81K_0402_1%
2
1

54.9K_0402_1% 1200P_0402_50V7K
@

PR937
36.5K_0402_1%

Compal Secret Data

Security Classification
2010/06/30

Issued Date

2012/06/30

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Compal Electronics, Inc.


+CPU_CORE/VDDNBP

+VDDNBP
Iocp~15A

PR930

PR932
10_0402_5%
1
2
DIFF_0

PR926
5.11K_0402_1%

0_0402_5%
2
1 RTN0
(5)

+APU_CORE

49

ISN1
24

ISP1
23

VW1
22

COMP1
21

FB1
20

VDIFF1
19

VSEN1
18

RTN1
17

RTN0

ISN0

ISP0
ISN0

BOOT1

ISP0

PR929
2
0_0402_5%

14

13

PR928
0_0402_5%

VSEN1

APU_VDD0_RUN_FB_H

ISP0

2 VSEN1

PR927
2
1
10_0402_5%

(5)

UGATE1

VW0

+APU_CORE

COMP0
VSEN0

12

PHASE1

16

11

FB0

15

10

2
2

PHASE0

PC915
0.22U_0603_25V7K

38

39

40

41

42

43

44

37
UGATE_NB

PHASE_NB

LGATE_NB

PGND_NB

OCSET_NB

RTN_NB

VSEN_NB

45

UGATE0

SVD

ENABLE

FSET_NB

46

PWROK

BOOT0

ISN0

35

36

ISP0

VR_ON
PR924
21.5K_0402_1%
2
1

1
PR921
0_0402_5%2

BOOT0

ISL6265_PWROK
2

BOOT_NB

PGOOD

PL903
0.36UH_ETQP4LR36WFC_24A_20%

1 2

(31)

APU_SVD
APU_SVC

PC909
220U_D2_4VM

(5)
(5)

OFS/VFIXEN

BOOT_NB

PR918
2.2_0603_1%
BOOT0 1
2 1

3
2
1

(13) H_PWRGD_L

2
@ PR917 100K_0402_5%
2
PR919 100K_0402_5%

PHASE0

FB_NB

1
1

COMP_NB

47
VCC

VIN

48

1
2

2
VGATE

PQ903
TPCA8065-H_SOP-ADV8-5

1
2
(14,31)
(14) FCH_PWRGD

LGATE_NB

UGATE0
PU901

@ PC910
680P_0603_50V7K

CPU_B+

UGATE_NB

@ PR916
105K_0402_1%

1 @ PR9102
10_0402_5%
PHASE_NB

@ PR915
10K_0402_1%

+APU_CORE_NB

AO4712L_SO8

PHASE_NB

PR914
105K_0402_1%

@PR905
4.7_1206_5%

PQ904
TPCA8059-H_SOP-ADVANCE8-5

@ PR913
105K_0402_1%

(5)

PR912
0_0402_5%

APU_VDDNB_RUN_FB_H

APU_VDD0_RUN_FB_L

PC911
0.1U_0603_25V7K

+3VS

+5VS

PR908
0_0402_5%
2
1
PR909
0_0402_5%
2
1

PC908
0.22U_0603_25V7K
4

3
2
1

+
2

PL902
3.3UH_PCMB104E-3R3MS_11A_20%
1
2
PQ902

+
2

B+

PR903
2.2_0603_1%
BOOT_NB 1
2 1
@ PR907
10_0402_5%
1
2 +APU_CORE_NB LGATE_NB

CPU_B+

PQ901
AO4466L_SO8

PHASE_NB

PR904
22K_0402_1%
2
1

PC907
0.1U_0603_16V7K

PC904
4.7U_0805_25V6-K
2
1

UGATE_NB

PC906
1000P_0402_50V7K
2
1
1

+5VS

PC902
1000P_0402_50V7K

PR902
2_0603_5%
1
2

5
6
7
8

3
2
1

PR901
44.2K_0402_1%

5
6
7
8

2
1

PC903
68U_25V_M_R0.36

Size Document Number


Custom
Date:

Rev
0.1

PAWGC

Tuesday, November 30, 2010

Sheet
E

44

of

47

Version Change List ( P. I. R. List ) for Power Circuit


Page#

Title
power sequence
Add PU802 for AMD's request

Add PL302,PC324 and PC325 for EMC Solution.


Add PC422 for EMC Solution.
Add PQ204 for EM6.0 battery learning function.

Date

Request
Owner

2010/07/30

HW

2010/09/21

AMD

2010/10/04

Issue Description

EMC

2010/10/06

EMC

2010/11/12

PWR

Solution Description
PR701 change to 0 ohm and PC704 non mount.

change PJ301 to PL302.

Compal Secret Data

Security Classification

Issued Date

2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.


Power PIR

Size
Document Number
Custom
Date:

Rev
0.1

LA6755P/7P

Tuesday, November 30, 2010

Sheet

45

of

47

INT_KBD Conn.
KSO[0..15]

Lid Switch

ME@
ACES_88514-2401

(31)

26
25

KSO[0..15] (31)

KSO2

C905 1

2 @ 100P_0402_50V8J

KSO1

C906 1

2 @ 100P_0402_50V8J

KSO15

C907 1

2 @ 100P_0402_50V8J

KSO7

C908 1

2 @ 100P_0402_50V8J

KSO6

C909 1

2 @ 100P_0402_50V8J

KSI2

C910 1

2 @ 100P_0402_50V8J

KSO8

C911 1

2 @ 100P_0402_50V8J

KSO5

C912 1

2 @ 100P_0402_50V8J

KSO13

C913 1

2 @ 100P_0402_50V8J

KSI3

C914 1

2 @ 100P_0402_50V8J

KSO12

C915 1

2 @ 100P_0402_50V8J

KSO14

C916 1

2 @ 100P_0402_50V8J

KSO11

C917 1

2 @ 100P_0402_50V8J

KSI7

C918 1

2 @ 100P_0402_50V8J

KSO10

C919 1

2 @ 100P_0402_50V8J

KSI6

C920 1

2 @ 100P_0402_50V8J

KSO3

C921 1

2 @ 100P_0402_50V8J

KSI5

C922 1

2 @ 100P_0402_50V8J

KSO4

C923 1

2 @ 100P_0402_50V8J

KSI4

C924 1

2 @ 100P_0402_50V8J

KSI0

C925 1

2 @ 100P_0402_50V8J

KSO9

C926 1

2 @ 100P_0402_50V8J

KSO0

C927 1

2 @ 100P_0402_50V8J

KSI1

C928 1

2 @ 100P_0402_50V8J

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

GND2
GND1
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
JKB1

To TP/B Conn.
ME@
ACES_88058-060N

C933
0.1U_0402_16V4Z

TP_CLK
TP_DATA
SW /L
SW /R

@
C935
100P_0402_50V8J

ZZZ1

ZZZ2

1
R886
1 @
R887

(31) KILL_SW #_EC


(14) KILL_SW #

D26

6
5

SW 3

8
7

GND
GND

6
5
4
3
2
1

6
5
4
3
2
1

PCB

LA6755P

CR2032_0

CR2032_0

<BOM Structure>

<BOM Structure>

<BOM Structure>

SMT1-05_4P

White

2
300_0402_5%

1
R763

+5VALW

19-213A-T1D-CP2Q2HY-3T_W HITE
LED2

BATT_LOW_LED#

Left --> White


Right --> Orange

(31) CHARGE_LED0#

White

(33) BT_LED#

(15) SATA_ITX_DRX_P1
(15) SATA_ITX_DRX_N1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_IRX_N1
SATA_DTX_IRX_P1

1
2
3
4
5
6
7

GND
A+
AGND
BB+
GND

8
9
10
11
12
13

DP
+5V
+5V
MD
GND
GND

R881 1

2
10K_0402_5%

1
R706

2
0_0402_5%

(14) ODD_DETECT#
+5VS_ODD

2
0_0402_5%
R809 1 @
2 ODD_DETECT#_R
0_0402_5%

ODD_DA#_R

@ Q118 2N7002_SOT23

1
R765

+3VALW

2
300_0402_5%

1
R764

+5VALW

19-213A-T1D-CP2Q2HY-3T_W HITE
@

LED3

White

2
300_0402_5%

1
R766

+5VS

2
300_0402_5%

1
R767

+5VS

19-213A-T1D-CP2Q2HY-3T_W HITE

RB751V_SOD323

JODD1

SATA ODD Conn.

1
R705

2
470_0402_5%

Change design to two LED


20101005

BATT_CHG_LED#
D17

SW 4

(15) SATA_DTX_C_IRX_N1
(15) SATA_DTX_C_IRX_P1

HT-191UD5_AMBER

RB751V_SOD323
@
D18

C875 1
C876 1

LED5

(30) W LAN_LED#

(31) RF_LED#

R874 1

2 0_0402_5%

LED4

White
(15) HDD_LED#

GND
GND

19-213A-T1D-CP2Q2HY-3T_W HITE

15
14

ALLTO_C18518-11305-L
ME@

2
G

2
0_0402_5%
2
0_0402_5%

OFF
ON

(31,34) PW R_LED#

LSSM12-P-V-T-R_3P

LED

Reserve for ESD

(14) ODD_DA#_FCH

LED1

SW /R

2
1

SW /L

(31) ODD_DA#

U34

SW 1

STATUS
1,2(LOW)
2,3(HI)

ZZZ3

PACDN042Y3R_SOT23-3

6
5

SMT1-05_4P

+3VS

+3VS

Compal Secret Data

Security Classification
2010/06/30

Issued Date

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

C932
10P_0402_50V8J

JTP1

LID_SW # (31)

100K_0402_5%

Orange

Kill Switch

(31) CHARGE_LED1#

OUTPUT

Kill
ZZZ

@
C934
100P_0402_50V8J

2 100K_0402_5%

S-5711ACDL-M3T1S_SOT23-3

2 R757

R756 1

+3VALW

+5VS

TP_CLK
TP_DATA

+VCC_LID

2
0_0402_5%

C931
0.1U_0402_16V4Z

CONN PIN define need double check

(31)
(31)

1
R755

+3VALW

KSI[0..7]

KSI[0..7]

VDD

GND

Title

Compal Electronics, Inc.


14" ONLY

Size
B
Date:

Document Number

Rev
1.0

LA6755P/7P
Tuesday, November 30, 2010

Sheet
1

46

of

48

ZZZ

ZZZ1

ZZZ2

ZZZ3

ZZZ4

ZZZ5

PCB

LA6757P

CR2032_0

CR2032_0

CR2032_0

CR2032_0

<BOM Structure>

<BOM Structure>

<BOM Structure>

<BOM Structure>

<BOM Structure>

JKB1
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
KSO16
KSO17

KSI[0..7]
KSO[0..17]

KSO17

C1000 1

2 @ 100P_0402_50V8J

KSO16

C1001 1

2 @ 100P_0402_50V8J

KSO1

C906 1

2 @ 100P_0402_50V8J

KSO7

C908 1

2 @ 100P_0402_50V8J

KSO2

C905 1

2 @ 100P_0402_50V8J

KSO15
KSO6

C909 1

2 @ 100P_0402_50V8J

KSI2

C910 1

2 @ 100P_0402_50V8J

KSO8

C911 1

2 @ 100P_0402_50V8J

KSO5

C912 1

2 @ 100P_0402_50V8J

KSO13

C913 1

2 @ 100P_0402_50V8J

KSI3

C914 1

2 @ 100P_0402_50V8J

KSO12

C915 1

2 @ 100P_0402_50V8J

KSO14

C916 1

2 @ 100P_0402_50V8J

KSO11

C917 1

2 @ 100P_0402_50V8J

KSI7

KSO10

C919 1

2 @ 100P_0402_50V8J

KSI6

C920 1

2 @ 100P_0402_50V8J

KSI5

C922 1

2 @ 100P_0402_50V8J

C926 1

2 @ 100P_0402_50V8J

KSO3
KSO4

C923 1

2 @ 100P_0402_50V8J

KSI4

KSI0

C925 1

2 @ 100P_0402_50V8J

KSO9

KSO0

KSI1

C928 1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

GND
GND

31
32

ACES_88514-3001
ME@

2 @ 100P_0402_50V8J

D17

RF_LED#_R

RB751V_SOD323
D18

R937 1

C933

7
8

D26

1
2
3
4
5
6

2
0_0402_5%
2
0_0402_5%

GND
GND

C875 1
2 0.01U_0402_16V7K
C876 1
2 0.01U_0402_16V7K
R881 1
2
0_0402_5%
R809 1 @
2 ODD_DETECT#_R
0_0402_5%

SMT1-05_4P

1
R939
1 @
R940

ACES_88058-060N
ME@

6
5

6
5

1
R706

SMT1-05_4P

2
0_0402_5%

SATA_DTX_IRX_N1
SATA_DTX_IRX_P1

ODD_DA#_R

@ Q118 2N7002_SOT23

SW /R

3
SW 4

2
G

SW 3

SW /L

1
2
3
4
5
6

TP_CLK
TP_DATA
SW /L
SW /R

@
C935
100P_0402_50V8J

KILL_SW #_R

JTP1

PACDN042Y3R_SOT23-3

@
C934
100P_0402_50V8J

RF_LED#_R

1
2
R874 0_0402_5%

0.1U_0402_16V4Z

2 100K_0402_5%

LID_SW #

RB751V_SOD323

Compal Secret Data

Security Classification
2010/06/30

Issued Date

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


15" ONLY

Size
B
Date:

Document Number

Rev
1.0

LA6757P
Tuesday, November 30, 2010

Sheet
1

46

of

48

PHASE

PAGE

Modification list

PURPOSE

0.2

P08

C643 change to OS-CON type

For cost down purpose

0.2

P10

pop R490, unpop R491

LVDS PWM controls by EC

0.2

P10

Add CE_EN @ JLVDS1.16 and U33.98

For color engine function

0.2

P10

R488 pull-up to +5VALW

For C38 module design

0.2

P10

Add R938

For CMOS cost down purpose

0.2

P12

JCRT1 change foot-print from DC060003O00 to DC060004S00

Foot-print is wrong

0.2

P14

SATA_DET# change from U26.AE19 to U26.AB21

For corresponding SATA port assigned

0.2

P16

Delete R635

Our codec consumes +3V

0.2

P18

Add R936

For VGA_PWRGD reservation

0.2

P20

Q69 ~ Q72 change to N-MOS

Follow BACO suggestion SCH

0.2

P21

R840 pull-up change to +5VALW and R857 change to 20K ohms

For +3VGS sequence design

0.2

P21

Delete Q122, Add U47, C999, R944

For +1.0VGS DC power design

0.2

P23

L27 change to 0 ohms

For new reference circuit

0.2

P23

Delete GND connection of U8.N11 and U8.N12

For new reference circuit

0.2

P21

R344 change to 20K ohms

Prevent Q74 damage

0.2

P28

J7 foot-print update

Base on DFX request

0.2

P28

Add net CLK_PCI_DB_R and unpop R854

for EMI concern

0.2

P28

Modify PC_Beep circuit

Base on vender suggestion

0.2

P23

Delete C421, C422, C431, C432, C433

For new reference circuit

0.2

P31

R734 pull-high change to +5VALW

For USB ports ACIN leakage

0.2

P31

Add BATT_SEL_EC at U33.103

For Battery selection reservation

0.2

P33

Add R941

For further cost down purpose

0.2

P33

Add R942, R943, C998

For SATA_DET# function design

0.2

P28

Delete C851, C855

For useless AGND bridge

0.2

P34

Change JP7 to JPWRB1 and JP8 to JCR1

For standard naming

0.2

P34

Del U45, R890 ~ R899, J12, CHR_ON# (U33.70)

Deleting USB charge function

0.2

P35

Delete C974

Deleting unnecessary part for +1.1VS

0.2

P19

Add R945, R946

For HDMI Audio strap

0.2

P13

Delete T79, T80

For layout space needed for SATA calibration

0.2

P28

Add R947, R948

For EMI solution reservation base on vender suggetion

0.2

P28

Delete C857, R694

To delete redundant part base on vender suggestion

0.2

P28

L57 ~ L60 change to 0_0603_5%

Base on vender suggestion

0.2

P28

R672 change to 0ohm and location to be series on HDA_BITCLK_AUDIO

For EMI solution reservation base on vender suggetion

0.2

P14

Kill_SW# change from U26.G24 to U26.K1

Kill_SW# function needs event pin

0.2

P31

Add R949, C1002

Requirement of implementing SUSCLK

0.2

P28

Add R950 @ +3VS, R951 @ +LDO_OUT_3.3V, R952 @ +5VS

For customer request (PWR consumption)

0.2

P28

Add R953

For PC Beep circuit

0.2

P29

Add R954, R955

For customer request (PWR consumption)

0.2

P13
P18

Add C1003, U48, R956, R957


Delete R556, R841, R889, D28

For PX GPU_RST# function

0.2

P05

Add R958

For enabling HDMI function

0.2

P28

Add R959

For EMI reservation

0.2

P32

Add R960 and c1004

For EMI reservation

0.2

P09

Add R961 and R962

For DDR SO-DIMMB strap pin reservation

0.2

P05

Delete T74, T75

For layout limitation

0.3

P29
P46

change +5V_ODD to +5VS_ODD

For better net name

0.3

P32

R760 change to 100ohm bead and R761 change back to 15ohm resistor

For correct EMI solution

0.3

P21

U47 change to SB00000GV00 footprint

For correct symbol

0.3

P05

R958 change to HDMI@ and R422 change to nonHDMI@

For SKU without HDMI function

0.3

P21

Add PX_MODE off page

For design correction


Compal Secret Data

Security Classification
2010/06/30

Issued Date

Change footprint
20100812
5

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

: For cost down purpose to change parts


4

Title

Compal Electronics, Inc.


HW-PIR1

Size
B
Date:

Document Number

Rev
1.0

LA-6755P
Tuesday, November 30, 2010

Sheet
1

47

of

48

PHASE

PAGE

Modification list

PURPOSE

0.2

P08

C643 change to OS-CON type

For cost down purpose

0.2

P10

pop R490, unpop R491

LVDS PWM controls by EC

0.2

P10

Add CE_EN @ JLVDS1.16 and U33.98

For color engine function

0.2

P10

R488 pull-up to +5VALW

For C38 module design

0.2

P10

Add R938

For CMOS cost down purpose

0.2

P12

JCRT1 change foot-print from DC060003O00 to DC060004S00

Foot-print is wrong

0.2

P14

SATA_DET# change from U26.AE19 to U26.AB21

For corresponding SATA port assigned

0.2

P16

Delete R635

Our codec consumes +3V

0.2

P18

Add R936

For VGA_PWRGD reservation

0.2

P20

Q69 ~ Q72 change to N-MOS

Follow BACO suggestion SCH

0.2

P21

R840 pull-up change to +5VALW and R857 change to 20K ohms

For +3VGS sequence design

0.2

P21

Delete Q122, Add U47, C999, R944

For +1.0VGS DC power design

0.2

P23

L27 change to 0 ohms

For new reference circuit

0.2

P23

Delete GND connection of U8.N11 and U8.N12

For new reference circuit

0.2

P21

R344 change to 20K ohms

Prevent Q74 damage

0.2

P28

J7 foot-print update

Base on DFX request

0.2

P28

Add net CLK_PCI_DB_R and unpop R854

for EMI concern

0.2

P28

Modify PC_Beep circuit

Base on vender suggestion

0.2

P23

Delete C421, C422, C431, C432, C433

For new reference circuit

0.2

P31

R734 pull-high change to +5VALW

For USB ports ACIN leakage

0.2

P31

Add BATT_SEL_EC at U33.103

For Battery selection reservation

0.2

P33

Add R941

For further cost down purpose

0.2

P33

Add R942, R943, C998

For SATA_DET# function design

0.2

P28

Delete C851, C855

For useless AGND bridge

0.2

P34

Change JP7 to JPWRB1 and JP8 to JCR1

For standard naming

0.2

P34

Del U45, R890 ~ R899, J12, CHR_ON# (U33.70)

Deleting USB charge function

0.2

P35

Delete C974

Deleting unnecessary part for +1.1VS

0.2

P19

Add R945, R946

For HDMI Audio strap

0.2

P13

Delete T79, T80

For layout space needed for SATA calibration

0.2

P28

Add R947, R948

For EMI solution reservation base on vender suggetion

0.2

P28

Delete C857, R694

To delete redundant part base on vender suggestion

0.2

P28

L57 ~ L60 change to 0_0603_5%

Base on vender suggestion

0.2

P28

R672 change to 0ohm and location to be series on HDA_BITCLK_AUDIO

For EMI solution reservation base on vender suggetion

0.2

P14

Kill_SW# change from U26.G24 to U26.K1

Kill_SW# function needs event pin

0.2

P31

Add R949, C1002

Requirement of implementing SUSCLK

0.2

P28

Add R950 @ +3VS, R951 @ +LDO_OUT_3.3V, R952 @ +5VS

For customer request (PWR consumption)

0.2

P28

Add R953

For PC Beep circuit

0.2

P29

Add R954, R955

For customer request (PWR consumption)

0.2

P13
P18

Add C1003, U48, R956, R957


Delete R556, R841, R889, D28

For PX GPU_RST# function

0.2

P05

Add R958

For enabling HDMI function

0.2

P28

Add R959

For EMI reservation

0.2

P32

Add R960 and c1004

For EMI reservation

0.2

P09

Add R961 and R962

For DDR SO-DIMMB strap pin reservation

0.2

P05

Delete T74, T75

For layout limitation

Add C1000, C1001

For 15" 30pin KB connector

15 only part
0.2

P46

Compal Secret Data

Security Classification
2010/06/30

Issued Date

Change footprint
20100812

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

: For cost down purpose to change parts


5

Deciphered Date

Title

Compal Electronics, Inc.


HW-PIR

Size
B
Date:

Document Number

Rev
1.0

LA6757P
Tuesday, November 30, 2010

Sheet
1

47

of

48

Modification list

PHASE

PAGE

0.3

P14

R603 and R604 change to pop

For SM Bus pull-high

0.3

P23

Reserve C1005

For PWR team request reserving a 330u capcitor

PURPOSE

0.3

P33

C939 change to 5.9H OS-con

For cost saving

0.3

P33

R902 and R942 change to unpop

For eSATA function deletion

0.3

P29

U32 change PN to SA000046C00

For main source PN concern

0.3

P05

Delete JHDT1

For layout limitation

0.3

P11

Add F2 and change SM-BUS pull high net name to +5VS_HDMI_F

For safety team requirement

0.3

P21

change J3 footprint

For larger jumper footprint

0.3

P21

R856 change from 20K to 39K

For VGA power sequence

0.3

P11

Add net name +5VS_HDMI_F

For power trace indecation

0.3

P20

Change Q69 ~ Q72 PN

For design correction

0.3

P28

Add R963

For 20671-21Z update

0.3

P28

Change U31 PN to SA00003K410

For 20671-21Z PN

0.3

P20

U10.5, U46.5, and U44.5 change from +3VS to +3VGS

For BACO circuit update

0.3

P28

Delete R951

For unnecessary part deletion

0.3

P07

C623 change to unpop

Base on AMD checklist

0.3

P16

Delete C734, add C1006, C1007

For ME concern

0.3

P21

R924 cahgne pull-up from +3VS to +3VALW

For BACO design correction

0.3

P21

R925 change to pop

For BACO design correction

0.3

P14

Reserve C1008 at FCH_PWRGD

For EMI request

0.3

P14

Reserve C1009 at VGATE

For EMI request

0.3

P31

Reserve C1010 at VR_ON

For EMI request

0.3

P13

Reserve C1011 at H_PWRGD_L

For EMI request

0.3

P28

pop C849, C850, R692, R693, R696, C826

For EMI request

0.3

P27

Add C1012, C1013

For EMI request (gas discharge tube)

0.3

P27

Add D1

For EMI request (ESD diode)

0.3

P28

update R672 location

For EMI request (RC to GND for codec BIT_CLK)

0.3

P07

Delete C617

For EMI solution space needed

0.3

P28

Pop D30, D31, unpop R953

For FCH PC-beep function

0.3

P31

R751 and R752 change from 4.7K ohm to 2.2K ohm

For PWR team request

0.3

P13

C719, C720 change from 22P to 18P

For RTC design

14" only part

0.3

P46

Change one dual-diode LED2 to two single diode LED2 and LED5

For design change

1.0

P5

unpop R415

AMD checklist update

1.0

P10

R486, R487 change pull-high to +5VS

AMD checklist update

1.0

P11

R522, R523 change from 2.2K to 2K

AMD checklist update

1.0

P12

reserve R964, R965, change R546 ~ R549 from 4.7K to 2K

AMD checklist update

1.0

P31

BATT_LEN# added to U33.38

PWR team request

1.0

P20

Delete R341

For design update

1.0

P21

Delete R837, R832, R836

For design update

1.0

P28

Delete R947, R948, R950, R952

For design update

1.0

P29

Delete R955, R954, R810

For design update

1.0

P30

unpop C887, C888

For design update

1.0

P25

unpop C494, C484, C498, C482, C490

For design update

Compal Secret Data

Security Classification
2010/06/30

Issued Date

Change footprint
20100812
5

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

: For cost down purpose to change parts


4

Title

Compal Electronics, Inc.


HW-PIR2

Size
B
Date:

Document Number

Rev
1.0

LA-6755P
Tuesday, November 30, 2010

Sheet
1

48

of

48

PHASE

PAGE

0.3
0.3

P29
P46
P32

Modification list

PURPOSE

change +5V_ODD to +5VS_ODD

For better net name

0.3

P21

R760 change to 100ohm bead and R761 change back to 15ohm resistor
U47 change to SB00000GV00 footprint

For correct EMI solution


For correct symbol

0.3

P05

R958 change to HDMI@ and R422 change to nonHDMI@

For SKU without HDMI function

0.3

P21

Add PX_MODE off page

For design correction

0.3

P14

R603 and R604 change to pop

For SM Bus pull-high

0.3

P23

Reserve C1005

For PWR team request reserving a 330u capcitor

0.3

P33

C939 change to 5.9H OS-con

For cost saving

0.3

P33

R902 and R942 change to unpop

For eSATA function deletion

0.3

P29

U32 change PN to SA000046C00

For main source PN concern

0.3

P05

Delete JHDT1

For layout limitation

0.3

P11

Add F2 and change SM-BUS pull high net name to +5VS_HDMI_F

For safety team requirement

0.3

P21

change J3 footprint

For larger jumper footprint

0.3

P21

R856 change from 20K to 39K

For VGA power sequence

0.3

P11

Add net name +5VS_HDMI_F

For power trace indecation

0.3

P20

Change Q69 ~ Q72 PN

For design correction

0.3

P28

Add R963

For 20671-21Z update

0.3

P28

Change U31 PN to SA00003K410

For 20671-21Z PN

0.3

P20

U10.5, U46.5, and U44.5 change from +3VS to +3VGS

For BACO circuit update

0.3

P28

Delete R951

For unnecessary part deletion

0.3

P07

C623 change to unpop

Base on AMD checklist

0.3

P16

Delete C734, add C1006, C1007

For ME concern

0.3

P21

R924 cahgne pull-up from +3VS to +3VALW

For BACO design correction

0.3

P21

R925 change to pop

For BACO design correction

0.3

P14

Reserve C1008 at FCH_PWRGD

For EMI request

0.3

P14

Reserve C1009 at VGATE

For EMI request

0.3

P31

Reserve C1010 at VR_ON

For EMI request

0.3

P13

Reserve C1011 at H_PWRGD_L

For EMI request

0.3

P28

pop C849, C850, R692, R693, R696, C826

For EMI request

0.3

P27

Add C1012, C1013

For EMI request (gas discharge tube)

0.3

P27

Add D1

For EMI request (ESD diode)

0.3

P28

update R672 location

For EMI request (RC to GND for codec BIT_CLK)

0.3

P07

Delete C617

For EMI solution space needed

0.3

P28

Pop D30, D31, unpop R953

For FCH PC-beep function

0.3

P31

R751 and R752 change from 4.7K ohm to 2.2K ohm

For PWR team request

0.3

P13

C719, C720 change from 22P to 18P

For RTC design

1.0

P5

unpop R415

AMD checklist update

1.0

P10

R486, R487 change pull-high to +5VS

AMD checklist update

1.0

P11

R522, R523 change from 2.2K to 2K

AMD checklist update

1.0

P12

Add R964, R965, change R548, R549 from 4.7K to 2K


unpop R546, R547, Q89

AMD checklist update


PWR team request

1.0

P31

BATT_LEN# added to U33.38

1.0

P46

Kill_SW#_R change from JLED1.5 to JLED1.12

Design change update

1.0

P20

Delete R341

For design update

1.0

P21

Delete R837, R832, R836

For design update

1.0

P28

Delete R947, R948, R950, R952

For design update

1.0

P29

Delete R955, R954, R810

For design update

1.0

P30

unpop C887, C888

For design update

1.0

P25

unpop C494, C484, C498, C482, C490

For design update

2010/06/30

Issued Date

Compal Secret Data

Security Classification

Change footprint
20100812

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

: For cost down purpose to change parts


4

Title

Compal Electronics, Inc.


HW-PIR2

Size
B
Date:

Document Number

Rev
1.0

LA6757P
Tuesday, November 30, 2010

Sheet
1

48

of

48

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