library IEEE; use IEEE.STD_LOGIC_1164.

ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Accm is port( b: in std_logic_vector(3 downto 0); sclr, clk, b1, b2 : in std_logic; q : out std_logic_vector(7 downto 0) ); end Accm; architecture Behavioral of Accm is -- signal declaration type tell is (rdy,pulse,not_rdy); signal d_n_s: tell; signal en: std_logic; -- component declaration COMPONENT my_accm PORT ( b : IN STD_LOGIC_VECTOR(3 DOWNTO 0); clk : IN STD_LOGIC; sclr : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; -- port map begin A1 : my_accm PORT MAP ( b => b, clk => en, sclr => sclr, q => q ); process(clk) begin if clk'event and clk='1' then case d_n_s is when rdy => en <= '0'; if b1='1' then d_n_s <= pulse; end if; when pulse => en <= '1'; d_n_s <= not_rdy; when not_rdy => en <='0'; if b2='1' then d_n_s <= rdy; end if; end case; end if;

end process; -- .VHO CODE ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG COMPONENT my_accm PORT ( b : IN STD_LOGIC_VECTOR(3 DOWNTO 0); clk : IN STD_LOGIC; sclr : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; -- COMP_TAG_END ------ End COMPONENT Declaration ------------- The following code must appear in the VHDL architecture -- body. Substitute your own instance name and net names. ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG your_instance_name : my_accm PORT MAP ( b => b, clk => clk, sclr => sclr, q => q ); end Behavioral; I am also pasting an