Array Multiplier

Haibin Wang
Qiong Wu

Outlines
Background & Motivation
Principles Implementation & Simulation

Advantages & Disadvantages

Conclusions

Background & Motivation

One of the most critical functions carried out by ALU
Digital multiplication is the most extensively used operation (especially in signal processing), people who design digital signal processors sacrifice a lot of chip area in order to make the multiply as fast as possible Innumerable schemes have been proposed for realization of the operation

Multiplication Schemes
Serial Multiplication (Shift-Add)
Computing a set of partial products, and then summing the partial products together. The implementations are primitive with simple architectures (used when there is a lack of a dedicated hardware multiplier)

Parallel Multiplication
Partial products are generated simultaneously Parallel implementations are used for high performance machines, where computation latency needs to be minimized

Principles of Array Multiplier

4*4 bit multiplication
a3

a2 b2 a2b0 a1b1 a0b2

a1 b1 a1b0 a0b1

a0 b0 a0b0

b3 a3b0

a3b1 a3b2 a3b3

p7 p6

a2b1 a1b2 a3b0

p3

a2b2 a3b1
p4

a3b2
p5

p2

p1

p0

For 4*4 Array Multiplier, it needs 16 AND gates, 4 HAs, 8FAs (total 12 Adders) For m*n Array Multiplier, it needs m*n AND gates, n HAs, (m-2)*n FAs, (total (m-1)*n Adders)

Principles of Array Multiplier(Cont.)

Principles of Array Multiplier(Cont.)

Implementation & Simulation

Verilog (ISE 10.1)
Multiplier Design
Cell: MulCell Multiplier: ArrayMult

Testbench
Stimulus Verification & Timing

Cell

Multiplier

Simulation Result & Timing

Advantages & Disadvantages

Advantages:
Minimum complexity Easily scalable Easily pipelined Regular shape, easy to place & route

Disadvantages:
High power consumption More digital gates resulting in large chip area

Conclusions
Array multiplier is implemented and verified in Verilog
Although it utilizes more gates, the performance can easily be increased using pipeline technique As a parallel multiplication method, array multiplier outperforms serial multiplication schemes in terms of speed.

Reference
[1]. http://www.trivology.com/articles/534/what-is-anarray-multiplier.html
[2]. http://ece.gmu.edu ece645_lecture7.ppt

Questions?