WT7515
PC POWER SUPPLY SUPERVISOR
Data Sheet
REV. 1.50 May 07, 2004
The information in this document is subject to change without notice. Weltrend Semiconductor, Inc. All Rights Reserved.
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2F, No. 24, Industry E. 9 th RD., Science-Based Industrial Park, Hsin-Chu, Taiwan TEL:886-3-5780241 FAX:886-3-5794278.5770419 Email:support@weltrend.com.tw
WT7515
Rev. 1.50
GENERAL DESCRIPTION
The WT7515 provides protection circuits, power good output (PGO), fault protection latch (FPOB), and a protection detector function (PSONB) control. It can minimize external components of switching power supply systems in personal computer. The Over / Under Voltage Detector (OVD / UVD) monitors 3.3V, 5V, 12V input voltage level. The Over Current Detector (OCD) monitor IS33, IS5, IS12 input current sense. When OVD or UVD or OCD detect the fault voltage level, the FPOB is latched HIGH and PGO go low. The latch can be reset by PSONB go HIGH. There is 2.4 ms delay time for PSONB turn off FPOB. When OVD and UVD and OCD detect the right voltage level, the power good output (PGO) will be issue.
FEATURES
The Over / Under Voltage Detector (OVD / UVD) monitors 3.3V, 5V, 12V input voltage level. The Over Current Detector (OCD) monitors IS33, IS5, IS12 input current sense. Both of the power good output (PGO) and fault protection latch (FPOB) are Open Drain Output. 75 / 300 ms time delay for UVD. 300 ms time delay for PGO. 38 ms for PSONB input signal Debounce. 73 us for internal signal Deglitches. 2.4 ms time delay for PSONB turn-off FPOB.
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1 2 3 4 5 6 7
14 13 12 11 10 9 8
ORDERING INFORMATION PACKAGE 14Pin Plastic DIP WT7515N140WT WT7515N141WT WT7515N140WT Pb LeadFree] Pb^ WT7515N141WT Pb The Top-Side Marking would been added a
14Pin Plastic SOP WT7515S140WT WT7515S141WT WT7515S140WT Pb WT7515S141WT Pb dot]^in the right side for lead-free package.
WT7515
Rev. 1.50
PIN DESCRIPTION Pin Name TYPE PGI I GND P FPOB O PSONB I IS12 I RI I VCC2 I IS5 I IS33 I V12 I V33 I V5 I VCC I PGO O
Description Power good input signal pin Ground Fault protection output pin, open drain output On/Off switch input 12V over current protection sense input Current sense adjust input Current sense power supply 5V over current protection sense input 3.3V over current protection sense input 12V over/under voltage input pin 3.3V over/under voltage input pin 5V over/under voltage input pin Power supply Power good output signal pin, open drain output
BLOCK DIAGRAM
VCC
PWR
Bandgap Reference
VREF = 1.2V
38ms debounce - UN
+
clr
V33
clr
75ms delay
OSC
CLK
- OV
+
V5
- UN
+
RST
R FPOB
- OV
+
73us debounce
V12
- UN
+
RST - OV
+ VREF PGI PGO
- UN
+ VCC2
73us debounce
clr
300ms delay
IS33
- OI
+
V12
IREF * 8
VCC2 IS5
- OI
+
V12 VREF +
VCC2
IREF
RI
IREF * 8
IS12
- OI
+
IREF * 8
WT7515
Rev. 1.50
PGI and PGO Parameter Under voltage threshold V33 V5 V12 PGO = 5V Isink =10mA -5 Condition Min. 2.55 4.1 9.5 1.16 Typ. 2.69 4.3 10 1.20 5 0.4 Max. 2.83 4.47 10.5 1.24 Unit V V V V uA V mV
Input threshold voltage(PGI) ILEAKAGE Leakage current(PGO) VOL Low level output voltage(PGO) Input offset voltage of OCP comparators PSONB Parameter Input pull-up current High-level input voltage Low-level input voltage
Condition PSONB= 0V
Min. 2.0
Typ. 150
Max.
0.8
Unit uA V V
WT7515
Rev. 1.50
TOTAL DEVICE Parameter Icc Supply current Vcc low voltage SWITCHING CHARACTERISTICS, Vcc=5V Parameter tdb1 De-bounce time (PSONB) tdleay1 Delay time (PGI to PGO) tdb2 De-bounce time (PSONB) tg De-glitch time tdelay2 PSONB to FPOB delay time tdelay3 Internal UVD/OCD delay time Condition PDON _N= 5V Min. Typ. 3.6 Max. 1 Unit mA V
Min. Typ. Max. 32 38 61 200 300 490 32 38 61 63 73 120 tdb2+2.0 tdb2+2.4 tdb2+3.8 after FPOB go low & 65 75 122 PGI > 1.2V after FPOB go low & 260 300 488 PGI < 1.2V
Condition
Unit mS mS mS uS mS mS mS
WT7515
Rev. 1.50
APPLICATION CIRCUIT
+5V +5VSB PGI +5VSB 10K 300 PSONB 0.01uF IS12 30K, 1% RI IS5 V12 IS33 22uF R2, 1% +3.3V input VCC2 R0=47 +3.3V PSONB V33 +5V input 1K PGI GND FPOB WT7515-141 1uF 1K +5VSB
22uF
R1, 1%
APPLICATION NOTE
When the current cross inductor raised, inductor voltage raised. And when inductor voltage exceeded resistor voltage, the OCP active. We can setup OCP point by the following equation Let VR = VL R * IR = RL * IL IR = 8 * IREF R * (8 * VREF / RI) = RL * IL R = (RL * IL) / (8 * VREF / RI) (1)
WT7515
Rev. 1.50
APPLICATION TIMMING
1.) PGI (UNDER_VOLTAGE)G
WT7515
Rev. 1.50
tdb1
tdelay3=300mS PSONB tdelay3+tg FPOB PGO PGI V33/V5/V12 IS33/IS5/IS12 tdb1 tdb1 tdelay1+tg tdb2 tdelay2
WT7515
Rev. 1.50
WT7515
Rev. 1.50
MECHANICAL INFORMATION
PLASTIC DUALINLINE PACKAGE
NOTE 1G linear dimensions are in inches] millimeters^. All NOTE 2G This drawing is subject to change without notice. NOTE 3G Falls within JEDEC MS001
WT7515
Rev. 1.50
NOTE 1G linear dimensions are in inches] millimeters^. All NOTE 2G This drawing is subject to change without notice. NOTE 3G Falls within JEDEC MS012