S 3 Astarter

##############################################################################
## Copyright (c) 2006, 2007 Xilinx, Inc.

## This design is confidential and proprietary of Xilinx, All Rights Reserved.
##############################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor:
Xilinx
## \ \ \/
Version:
1.0.1
## \ \
Filename:
starter_kit_constraints.ucf
## / /
Date Created: December 25, 2006
## /___/ /\
Last Modified: April 1, 2007
## \ \ / \
## \___\/\___\
##
## Devices: Spartan-3 Generation FPGA
## Purpose: Complete constraint file for Spartan-3A(N) Starter Kit
## Contact: crabill@xilinx.com
## Reference: None
##
## Revision History:
## Rev 1.0.0 - (crabill) Created December 25, 2006 for PCB revision C.
## Rev 1.0.1 - (crabill) Modified April 1, 2007 to mention revision D
##
of the PCB and applicability to Spartan-3AN.
##
##############################################################################
##
## LIMITED WARRANTY AND DISCLAIMER. These designs are provided to you "as is".
## Xilinx and its licensors make and you receive no warranties or conditions,
## express, implied, statutory or otherwise, and Xilinx specifically disclaims
## any implied warranties of merchantability, non-infringement, or fitness for
## a particular purpose. Xilinx does not warrant that the functions contained
## in these designs will meet your requirements, or that the operation of
## these designs will be uninterrupted or error free, or that defects in the
## designs will be corrected. Furthermore, Xilinx does not warrant or make any
## representations regarding use or the results of the use of the designs in
## terms of correctness, accuracy, reliability, or otherwise.
##
## LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be liable
## for any loss of data, lost profits, cost or procurement of substitute goods
## or services, or for any special, incidental, consequential, or indirect
## damages arising from the use or operation of the designs or accompanying
## documentation, however caused and on any theory of liability. This
## limitation will apply even if Xilinx has been advised of the possibility
## of such damage. This limitation shall apply not-withstanding the failure
## of the essential purpose of any limited remedies herein.
##
##############################################################################
## Copyright (c) 2006, 2007 Xilinx, Inc.
## This design is confidential and proprietary of Xilinx, All Rights Reserved.
##############################################################################
# On this board, VCCAUX is 3.3 volts.
CONFIG VCCAUX = "3.3" ;
# Configure SUSPEND mode options.
CONFIG ENABLE_SUSPEND = "FILTERED" ;
# FILTERED is appropriate for use with the switch on this board. Other allowed
# settings are NO or UNFILTERED. If set NO, the AWAKE pin becomes general I/O.
# Please read the FPGA User Guide for more information.
# Configure POST_CRC options.
CONFIG POST_CRC = "DISABLE" ;
#
#
#
#
DISABLE the post-configuration CRC checking so INIT_B is available for

general I/O after configuration is done. On this board, INIT_B is used
after configuration to control the Platform Flash device. Other allowed
settings are ENABLE. Please read the FPGA User Guide for more information.
##############################################################################
# These are sample constraints for the three clock inputs. You will need
# to change these constraints to suit your application. Please read the
# FPGA Development System Reference Guide for more information on expressing
# timing constraints for your design.
##############################################################################
NET "CLK_50M"
LOC = "E12" | IOSTANDARD = LVCMOS33 | PERIOD = 20.000 ;
OFFSET = IN 10.000 VALID 20.000 BEFORE "CLK_50M" ;
OFFSET = OUT 20.000 AFTER "CLK_50M" ;
NET "CLK_AUX"
LOC = "V12" | IOSTANDARD = LVCMOS33 | PERIOD = 20.000 ;
OFFSET = IN 10.000 VALID 20.000 BEFORE "CLK_AUX" ;
OFFSET = OUT 20.000 AFTER "CLK_AUX" ;
NET "CLK_SMA"
LOC = "U12" | IOSTANDARD = LVCMOS33 | PERIOD = 20.000 ;
OFFSET = IN 10.000 VALID 20.000 BEFORE "CLK_SMA" ;
OFFSET = OUT 20.000 AFTER "CLK_SMA" ;
##############################################################################
# Discrete Indicators (LED)
##############################################################################
NET "LED<0>"
OW ;
NET "LED<1>"
OW ;
NET "LED<2>"
OW ;
NET "LED<3>"
OW ;
NET "LED<4>"
OW ;
NET "LED<5>"
OW ;
NET "LED<6>"
OW ;
NET "LED<7>"
OW ;
LOC = "R20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "T19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
LOC = "U20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
LOC = "V19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
LOC = "Y22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
LOC = "W21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
##############################################################################
# Character Display (LCD)
##############################################################################
NET "LCD_DB<0>"
OW ;
NET "LCD_DB<1>"
OW ;

LOC = "AB18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
NET "LCD_DB<2>"
OW ;
NET "LCD_DB<3>"
OW ;
NET "LCD_DB<4>"
OW ;
NET "LCD_DB<5>"
OW ;
NET "LCD_DB<6>"
OW ;
NET "LCD_DB<7>"
OW ;
NET "LCD_E"
OW ;
NET "LCD_RS"
OW ;
NET "LCD_RW"
OW ;

LOC = "AA12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
##############################################################################
# Stereo Audio Output (AUD)
##############################################################################
NET "AUD_L"
OW ;
NET "AUD_R"
OW ;

##############################################################################
# Video Output Port (VGA)
##############################################################################
NET "VGA_B<0>"
ST ;
NET "VGA_B<1>"
ST ;
NET "VGA_B<2>"
ST ;
NET "VGA_B<3>"
ST ;
NET "VGA_G<0>"
ST ;
NET "VGA_G<1>"
ST ;
NET "VGA_G<2>"
ST ;
NET "VGA_G<3>"
ST ;
NET "VGA_R<0>"
ST ;
NET "VGA_R<1>"
ST ;
NET "VGA_R<2>"
ST ;
NET "VGA_R<3>"
ST ;
NET "VGA_HSYNC"
ST ;
NET "VGA_VSYNC"
ST ;
LOC = "C7"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA
LOC = "D7"
LOC = "B9"
LOC = "C9"
LOC = "C5"
LOC = "D5"
LOC = "C6"
LOC = "D6"
LOC = "A3"
LOC = "B3"
LOC = "B8"
LOC = "C8"
LOC = "C11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

LOC = "B11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA
##############################################################################
# Hirose Expansion Connector (FX2)
##############################################################################
NET "FX2_IO<1>"
OW ;
NET "FX2_IO<2>"
OW ;
NET "FX2_IO<3>"
OW ;
NET "FX2_IO<4>"
OW ;
NET "FX2_IO<5>"
OW ;
NET "FX2_IO<6>"
OW ;
NET "FX2_IO<7>"
OW ;
NET "FX2_IO<8>"
OW ;
NET "FX2_IO<9>"
OW ;
NET "FX2_IO<10>"
OW ;
NET "FX2_IO<11>"
OW ;
NET "FX2_IO<12>"
OW ;
NET "FX2_IO<13>"
OW ;
NET "FX2_IO<14>"
OW ;
NET "FX2_IO<15>"
OW ;
NET "FX2_IO<16>"
OW ;
NET "FX2_IO<17>"
OW ;
NET "FX2_IO<18>"
OW ;
NET "FX2_IO<19>"
OW ;
NET "FX2_IO<20>"
OW ;
NET "FX2_IO<21>"
OW ;
NET "FX2_IO<22>"
OW ;
NET "FX2_IO<23>"
OW ;
NET "FX2_IO<24>"
OW ;
NET "FX2_IO<25>"
OW ;
NET "FX2_IO<26>"
OW ;
NET "FX2_IO<27>"
OW ;
NET "FX2_IO<28>"
LOC = "A13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "B13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
LOC = "D19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
LOC = "E17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
LOC = "F18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
LOC = "G20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
OW ;
NET "FX2_IO<29>"
OW ;
NET "FX2_IO<30>"
OW ;
NET "FX2_IO<31>"
OW ;
NET "FX2_IO<32>"
OW ;
NET "FX2_IO<33>"
OW ;
NET "FX2_IO<34>"
OW ;
NET "FX2_IO<35>"
OW ;
NET "FX2_IO<36>"
OW ;
NET "FX2_IO<37>"
OW ;
NET "FX2_IO<38>"
OW ;
NET "FX2_IO<39>"
OW ;
NET "FX2_IO<40>"
OW ;
NET "FX2_CLKIN"
OW ;
NET "FX2_CLKIO"
OW ;
NET "FX2_CLKOUT"
OW ;
LOC = "H19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "J18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
LOC = "K18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
LOC = "L19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
LOC = "M20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
LOC = "P20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
##############################################################################
# Accessory Headers (J18, J19, J20)
##############################################################################
NET "J18_IO<1>"
OW ;
NET "J18_IO<2>"
OW ;
NET "J18_IO<3>"
OW ;
NET "J18_IO<4>"
OW ;
NET "J19_IO<1>"
OW ;
NET "J19_IO<2>"
OW ;
NET "J19_IO<3>"
OW ;
NET "J19_IO<4>"
OW ;
NET "J20_IO<1>"
OW ;
NET "J20_IO<2>"
OW ;
NET "J20_IO<3>"
OW ;



NET "J20_IO<4>"
OW ;
##############################################################################
# Mouse and/or Keyboard Connector (PS2)
##############################################################################
# Primary connection, simply plug device into connector.
NET "PS2_CLK1"
OW ;
NET "PS2_DATA1"
OW ;
# Secondary connection, use requires a splitter cable.
NET "PS2_CLK2"
OW ;
NET "PS2_DATA2"
OW ;
##############################################################################
# High-Speed LVDS Receiver Connector (RX)
##############################################################################
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"RX_CLK_N"
"RX_CLK_P"
"RX_N<0>"
"RX_P<0>"
"RX_N<1>"
"RX_P<1>"
"RX_N<2>"
"RX_P<2>"
"RX_N<3>"
"RX_P<3>"
"RX_N<4>"
"RX_P<4>"
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
=
=
=
=
=
=
=
=
=
=
=
=
"A11"
"A12"
"B4"
"A4"
"A5"
"B6"
"A6"
"A7"
"A8"
"A9"
"C10"
"A10"
|
|
|
|
|
|
|
|
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
=
=
=
=
=
=
=
=
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
;
;
;
;
;
;
;
;
;
;
;
;
##############################################################################
# High-Speed LVDS Transmitter Connector (TX)
##############################################################################
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"TX_CLK_N"
"TX_CLK_P"
"TX_N<0>"
"TX_P<0>"
"TX_N<1>"
"TX_P<1>"
"TX_N<2>"
"TX_P<2>"
"TX_N<3>"
"TX_P<3>"
"TX_N<4>"
"TX_P<4>"
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
=
=
=
=
=
=
=
=
=
=
=
=
"AB10"
"AA10"
"AA3"
"AB2"
"AA4"
"AB3"
"AB6"
"AA6"
"AB7"
"Y7"
"AB8"
"AA8"
|
|
|
|
|
|
|
|
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
=
=
=
=
=
=
=
=
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
;
;
;
;
;
;
;
;
;
;
;
;
##############################################################################
# Directional Push-Buttons (BTN)
##############################################################################
NET "BTN_EAST"
NET "BTN_NORTH"
NET "BTN_SOUTH"
LOC = "T16" | IOSTANDARD = LVCMOS33 | PULLDOWN ;

NET "BTN_WEST"
LOC = "U15" | IOSTANDARD = LVCMOS33 | PULLDOWN ;
##############################################################################
# Rotary Knob (ROT)
##############################################################################
NET "ROT_CENTER"
NET "ROT_A"
NET "ROT_B"
LOC = "R13" | IOSTANDARD = LVCMOS33 | PULLDOWN ;

LOC = "T13" | IOSTANDARD = LVCMOS33 | PULLUP ;
LOC = "R14" | IOSTANDARD = LVCMOS33 | PULLUP ;
##############################################################################
# Mechanical Switches (SW)
##############################################################################
NET
NET
NET
NET
"SW<0>"
"SW<1>"
"SW<2>"
"SW<3>"
LOC
LOC
LOC
LOC
=
=
=
=
"V8"
"U10"
"U8"
"T9"
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
;
;
;
;
##############################################################################
# Serial Ports (RS232)
##############################################################################
NET "RS232_DCE_RXD" LOC = "E16" | IOSTANDARD = LVCMOS33 ;
NET "RS232_DCE_TXD" LOC = "F15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
OW ;
NET "RS232_DTE_RXD" LOC = "F16" | IOSTANDARD = LVCMOS33 ;
NET "RS232_DTE_TXD" LOC = "E15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
OW ;
##############################################################################
# Regulator I2C Control (REG)
##############################################################################
# Controls VCCINT, VCCAUX, and VCCO_012 supply rails.
NET "REG1_SCL"
OW ;
NET "REG1_SDA"
OW ;
# Controls SDRAM, TERM, and VREF supply rails.
NET "REG2_SCL"
OW ;
NET "REG2_SDA"
OW ;
##############################################################################
# 10/100 Ethernet (E)
##############################################################################
NET "E_TX_CLK"
LOC = "E11" | IOSTANDARD = LVCMOS33 | PERIOD = 40.000 ;
OFFSET = IN 5.000 VALID 10.000 BEFORE "E_TX_CLK" ;
OFFSET = OUT 10.000 AFTER "E_TX_CLK" ;
NET "E_RX_CLK"
LOC = "C12" | IOSTANDARD = LVCMOS33 | PERIOD = 40.000 ;
OFFSET = IN 5.000 VALID 10.000 BEFORE "E_RX_CLK" ;
OFFSET = OUT 10.000 AFTER "E_RX_CLK" ;
NET "E_NRST"
OW ;
NET "E_MDC"
OW ;
NET "E_MDIO"
OW ;

NET "E_TXD<0>"
ST ;
NET "E_TXD<1>"
ST ;
NET "E_TXD<2>"
ST ;
NET "E_TXD<3>"
ST ;
NET "E_TX_EN"
ST ;
LOC = "F8"
LOC = "E7"
LOC = "E6"
LOC = "F7"
LOC = "D8"
NET
NET
NET
NET
NET
"E_RXD<0>"
"E_RXD<1>"
"E_RXD<2>"
"E_RXD<3>"
"E_RX_DV"
LOC
LOC
LOC
LOC
LOC
=
=
=
=
=
"G7"
"G8"
"G9"
"H9"
"H10"
|
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
=
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
|
|
|
|
;
NET
NET
NET
NET
"E_RX_ERR"
"E_NINT"
"E_CRS"
"E_COL"
LOC
LOC
LOC
LOC
=
=
=
=
"G10"
"B2"
"H12"
"G12"
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
;
| PULLUP ;
| PULLDOWN ;
| PULLDOWN ;
PULLUP
PULLUP
PULLUP
PULLUP
;
;
;
;
##############################################################################
# Serial Peripheral System
##############################################################################
NET "SPI_SCK"
OW ;
NET "SPI_MOSI"
OW ;
NET "SPI_MISO"
OW ;
NET "AMP_OUT"
P
NET "DAC_OUT"
C
NET "ADC_OUT"
C
NET "SPI_SS_B"
OW ;
NET "ALT_SS_B"
OW ;
NET "FPGA_INIT_B"
OW ;
NET "AMP_CS"
OW ;
NET "DAC_CS"
OW ;
NET "AD_CONV"
OW ;
LOC = "Y4"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
LOC = "Y5"
NET "AMP_SHDN"

LOC = "T7"
| IOSTANDARD = LVCMOS33 ; # Private MISO for AM
LOC = "V7"
| IOSTANDARD = LVCMOS33 ; # Private MISO for DA
LOC = "D16" | IOSTANDARD = LVCMOS33 ; # Private MISO for AD

LOC = "W6"
LOC = "W7"
LOC = "Y6"
OW ;
NET "DAC_CLR"
OW ;
NET "ST_SPI_WP"
OW ;
NET "DATAFLASH_WP"
OW ;
NET "DATAFLASH_RST"
OW ;

##############################################################################
# Parallel Flash (NF)
##############################################################################
NET "NF_CE"
OW ;
NET "NF_BYTE"
OW ;
NET "NF_OE"
OW ;
NET "NF_RP"
OW ;
NET "NF_WE"
OW ;
NET "NF_WP"
OW ;
NET "NF_STS"
NET "NF_A<1>"
OW ;
NET "NF_A<2>"
OW ;
NET "NF_A<3>"
OW ;
NET "NF_A<4>"
OW ;
NET "NF_A<5>"
OW ;
NET "NF_A<6>"
OW ;
NET "NF_A<7>"
OW ;
NET "NF_A<8>"
OW ;
NET "NF_A<9>"
OW ;
NET "NF_A<10>"
OW ;
NET "NF_A<11>"
OW ;
NET "NF_A<12>"
OW ;
NET "NF_A<13>"
OW ;
NET "NF_A<14>"
OW ;
NET "NF_A<15>"
OW ;
NET "NF_A<16>"
OW ;
LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "P22" | IOSTANDARD = LVCMOS33 ;

LOC = "P18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
LOC = "N22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL
NET "NF_A<17>"
OW ;
NET "NF_A<18>"
OW ;
NET "NF_A<19>"
OW ;
NET "NF_A<20>"
OW ;
NET "NF_A<21>"
OW ;

# Note: NF_D<0> pin is shared with SPI_MISO pin which was previously
NET "NF_D<1>"
LOC = "Y17" | IOSTANDARD = LVCMOS33 | DRIVE = 8
OW ;
NET "NF_D<2>"
LOC = "AA17" | IOSTANDARD = LVCMOS33 | DRIVE = 8
OW ;
NET "NF_D<3>"
LOC = "U13" | IOSTANDARD = LVCMOS33 | DRIVE = 8
OW ;
NET "NF_D<4>"
LOC = "AB11" | IOSTANDARD = LVCMOS33 | DRIVE = 8
OW ;
NET "NF_D<5>"
OW ;
NET "NF_D<6>"
LOC = "AB9" | IOSTANDARD = LVCMOS33 | DRIVE = 8
OW ;
NET "NF_D<7>"
OW ;
NET "NF_D<8>"
LOC = "T20" | IOSTANDARD = LVCMOS33 | DRIVE = 8
OW ;
NET "NF_D<9>"
LOC = "W22" | IOSTANDARD = LVCMOS33 | DRIVE = 8
OW ;
NET "NF_D<10>"
LOC = "V22" | IOSTANDARD = LVCMOS33 | DRIVE = 8
OW ;
NET "NF_D<11>"
OW ;
NET "NF_D<12>"
OW ;
NET "NF_D<13>"
OW ;
NET "NF_D<14>"
LOC = "R21" | IOSTANDARD = LVCMOS33 | DRIVE = 8
OW ;
NET "NF_D<15>"
OW ;
# Note: NF_D<15> becomes NF_A<0> when NF_BYTE is asserted (for 8-bit
declared.
| SLEW = SL
| SLEW = SL
| SLEW = SL
| SLEW = SL
| SLEW = SL
| SLEW = SL
| SLEW = SL
| SLEW = SL
| SLEW = SL
| SLEW = SL
| SLEW = SL
| SLEW = SL
| SLEW = SL
| SLEW = SL
| SLEW = SL
mode).
##############################################################################
# DDR2 SDRAM Device (SD)
##############################################################################
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"SD_A<0>"
"SD_A<1>"
"SD_A<2>"
"SD_A<3>"
"SD_A<4>"
"SD_A<5>"
"SD_A<6>"
"SD_A<7>"
"SD_A<8>"
"SD_A<9>"
"SD_A<10>"
"SD_A<11>"
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
=
=
=
=
=
=
=
=
=
=
=
=
"R2"
"T4"
"R1"
"U3"
"U2"
"U4"
"U1"
"Y1"
"W1"
"W2"
"T3"
"V1"
|
|
|
|
|
|
|
|
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
=
=
=
=
=
=
=
=
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
;
;
;
;
;
;
;
;
;
;
;
;
NET
NET
NET
NET
"SD_A<12>"
"SD_A<13>"
"SD_A<14>"
"SD_A<15>"
LOC
LOC
LOC
LOC
=
=
=
=
"Y2"
"V3"
"V4"
"W3"
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
;
;
;
;
NET "SD_BA<0>"
NET "SD_BA<1>"
NET "SD_BA<2>"
LOC = "P3"
LOC = "R3"
LOC = "P5"
| IOSTANDARD = SSTL18_I ;
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"SD_RAS"
"SD_CAS"
"SD_CK_N"
"SD_CK_P"
"SD_CKE"
"SD_ODT"
"SD_CS"
"SD_WE"
"SD_LDM"
"SD_LDQS_N"
"SD_LDQS_P"
"SD_LOOP_IN"
"SD_LOOP_OUT"
"SD_UDM"
"SD_UDQS_N"
"SD_UDQS_P"
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
"M3"
"M4"
"M2"
"M1"
"N3"
"P1"
"M5"
"N4"
"J3"
"K2"
"K3"
"H4"
"H3"
"E3"
"J5"
"K6"
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"SD_DQ<0>"
"SD_DQ<1>"
"SD_DQ<2>"
"SD_DQ<3>"
"SD_DQ<4>"
"SD_DQ<5>"
"SD_DQ<6>"
"SD_DQ<7>"
"SD_DQ<8>"
"SD_DQ<9>"
"SD_DQ<10>"
"SD_DQ<11>"
"SD_DQ<12>"
"SD_DQ<13>"
"SD_DQ<14>"
"SD_DQ<15>"
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
"H1"
"K5"
"K1"
"L3"
"L5"
"L1"
"K4"
"H2"
"F2"
"G4"
"G1"
"H6"
"H5"
"F1"
"G3"
"F3"
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
##############################################################################

S 3 Astarter

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##############################################################################

## Copyright (c) 2006, 2007 Xilinx, Inc.

DISABLE the post-configuration CRC checking so INIT_B is available for

LOC = "R20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "Y13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "AB17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "Y10" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

LOC = "C11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

LOC = "A13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "H19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "AA21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "Y18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "V14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "AB21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "W18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "V16" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "T16" | IOSTANDARD = LVCMOS33 | PULLDOWN ;

LOC = "U15" | IOSTANDARD = LVCMOS33 | PULLDOWN ;

LOC = "R13" | IOSTANDARD = LVCMOS33 | PULLDOWN ;

LOC = "D15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "D10" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FA

LOC = "AA20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "AB14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "W15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "AB20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

| IOSTANDARD = LVCMOS33 ; # Private MISO for AM

| IOSTANDARD = LVCMOS33 ; # Private MISO for DA

LOC = "D16" | IOSTANDARD = LVCMOS33 ; # Private MISO for AD

LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "AB13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "W20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "Y21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "R19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

LOC = "H20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SL

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