PIC16F627A/628A/648A

4.0
4.1

MEMORY ORGANIZATION
Program Memory Organization

4.2

Data Memory Organization

The PIC16F627A/628A/648A has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh) for the PIC16F627A, 2K x 14 (0000h-07FFh) for the PIC16F628A and 4K x 14 (0000h-0FFFh) for the PIC16F648A are physically implemented. Accessing a location above these boundaries will cause a wraparound within the first 1K x 14 space (PIC16F627A), 2K x 14 space (PIC16F628A) or 4K x 14 space (PIC16F648A). The Reset vector is at 0000h and the interrupt vector is at 0004h (Figure 4-1).

The data memory (Figure 4-2 and Figure 4-3) is partitioned into four banks, which contain the General Purpose Registers (GPRs) and the Special Function Registers (SFRs). The SFRs are located in the first 32 locations of each bank. There are General Purpose Registers implemented as static RAM in each bank. Table 4-1 lists the General Purpose Register available in each of the four banks.

TABLE 4-1:

GENERAL PURPOSE STATIC RAM REGISTERS

PIC16F627A/628A PIC16F648A 20-7Fh A0h-FF 120h-17Fh 1F0h-1FFh 20-7Fh A0h-FF

Bank0 Bank1 Bank2 Bank3

FIGURE 4-1:

PROGRAM MEMORY MAP AND STACK

PC<12:0> 13

120h-14Fh, 170h-17Fh 1F0h-1FFh

CALL, RETURN RETFIE, RETLW

Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector 000h

Addresses F0h-FFh, 170h-17Fh and 1F0h-1FFh are implemented as common RAM and mapped back to addresses 70h-7Fh. Table 4-2 lists how to access the four banks of registers via the Status register bits RP1 and RP0.

TABLE 4-2:
Bank 0 1 0004 0005 2 3

ACCESS TO BANKS OF REGISTERS

RP1 0 0 1 1 RP0 0 1 0 1

Interrupt Vector On-chip Program Memory PIC16F627A, PIC16F628A and PIC16F648A

4.2.1
03FFh

GENERAL PURPOSE REGISTER FILE

On-chip Program Memory PIC16F628A and PIC16F648A 07FFh On-chip Program Memory PIC16F648A only 0FFFh

The register file is organized as 224 x 8 in the PIC16F627A/628A and 256 x 8 in the PIC16F648A. Each is accessed either directly or indirectly through the File Select Register (FSR), See Section 4.4 Indirect Addressing, INDF and FSR Registers.

1FFFh

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PIC16F627A/628A/648A
FIGURE 4-2: DATA MEMORY MAP OF THE PIC16F627A AND PIC16F628A
File Address Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTB 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh CMCON General Purpose Register 80 Bytes 6Fh 70h 16 Bytes 7Fh Bank 0 1Fh 20h General Purpose Register 80 Bytes EFh F0h VRCON TXSTA SPBRG EEDATA EEADR EECON1 EECON2(1) PR2 PCON PCLATH INTCON PIE1 Indirect addr.(1) OPTION PCL STATUS FSR TRISA TRISB 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register 48 Bytes 11Fh 120h 14Fh 150h 16Fh 170h 17Fh Bank 2 1EFh 1F0h PCLATH INTCON PORTB Indirect addr.(1) TMR0 PCL STATUS FSR 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh PCLATH INTCON TRISB Indirect addr.(1) OPTION PCL STATUS FSR 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh

accesses 70h-7Fh Bank 1

accesses 70h-7Fh

accesses 70h-7Fh Bank 3

FFh

1FFh

Unimplemented data memory locations, read as 0. Note 1: Not a physical register.

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PIC16F627A/628A/648A
FIGURE 4-3: DATA MEMORY MAP OF THE PIC16F648A
File Address Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTB 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh CMCON General Purpose Register 80 Bytes 6Fh 70h 16 Bytes 7Fh Bank 0 1Fh 20h General Purpose Register 80 Bytes EFh F0h VRCON TXSTA SPBRG EEDATA EEADR EECON1 EECON2(1) PR2 PCON PCLATH INTCON PIE1 Indirect addr.(1) OPTION PCL STATUS FSR TRISA TRISB 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register 80 Bytes 16Fh 170h 17Fh Bank 2 1EFh 1F0h 11Fh 120h PCLATH INTCON PORTB Indirect addr.(1) TMR0 PCL STATUS FSR 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh PCLATH INTCON TRISB Indirect addr.(1) OPTION PCL STATUS FSR 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh

accesses 70h-7Fh Bank 1

accesses 70h-7Fh

accesses 70h-7Fh Bank 3

FFh

1FFh

Unimplemented data memory locations, read as 0. Note 1: Not a physical register.

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PIC16F627A/628A/648A
4.2.2 SPECIAL FUNCTION REGISTERS
The SFRs are registers used by the CPU and Peripheral functions for controlling the desired operation of the device (Table 4-3). These registers are static RAM. The special registers can be classified into two sets (core and peripheral). The SFRs associated with the core functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.

TABLE 4-3:
Address Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Legend: Note 1: INDF TMR0 PCL STATUS FSR PORTA PORTB PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON CCPR1L Name

SPECIAL REGISTERS SUMMARY BANK0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset(1) Details on Page

Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Modules Register Program Counters (PC) Least Significant Byte IRP RA7 RB7 RP1 RA6 RB6 RP0 RA5 RB5 TO RA4 RB4 PD RA3 RB3 Z RA2 RB2 DC RA1 RB1 C RA0 RB0 Indirect Data Memory Address Pointer

xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx xxxx 0000 xxxx xxxx

30 47 30 24 30 33 38 30 26 28 50 50 50 54 54 57 57 57 74 79 82 63

Unimplemented Unimplemented Unimplemented GIE EEIF PEIE CMIF T0IE RCIF Write Buffer for upper 5 bits of Program Counter INTE TXIF RBIE T0IF CCP1IF INTF TMR2IF RBIF TMR1IF

---0 0000 0000 000x 0000 -000 xxxx xxxx xxxx xxxx

Unimplemented Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TOUTPS3 T1CKPS1 T1CKPS0 T1OSCEN TOUTPS0 T1SYNC TMR2ON TMR1CS T2CKPS1 TMR1ON T2CKPS0 TMR2 Modules Register TOUTPS2 TOUTPS1 Unimplemented Unimplemented Capture/Compare/PWM Register (LSB) Capture/Compare/PWM Register (MSB) SPEN RX9 CCP1X SREN CCP1Y CREN CCP1M3 ADEN CCP1M2 FERR CCP1M1 OERR CCP1M0 RX9D

--00 0000 0000 0000 -000 0000 xxxx xxxx xxxx xxxx --00 0000 0000 000x 0000 0000 0000 0000

CCPR1H CCP1CON RCSTA TXREG RCREG CMCON

USART Transmit Data Register USART Receive Data Register Unimplemented Unimplemented Unimplemented Unimplemented C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0

0000 0000

- = Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.

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PIC16F627A/628A/648A
TABLE 4-4:
Address Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Legend: Note 1: PR2 TXSTA SPBRG EEDATA EEADR EECON1 EECON2 VRCON INDF OPTION PCL STATUS FSR TRISA TRISB PCLATH INTCON PIE1 PCON Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU IRP TRISA7 TRISB7 INTEDG RP1 TRISA6 TRISB6 T0CS RP0 TRISA5 TRISB5 T0SE TO TRISA4 TRISB4 PSA PD TRISA3 TRISB3 PS2 Z TRISA2 TRISB2 PS1 DC TRISA1 TRISB1 PS0 C TRISA0 TRISB0 Program Counters (PC) Least Significant Byte Indirect Data Memory Address Pointer xxxx xxxx 1111 1111 0000 0000 0001 1xxx xxxx xxxx 1111 1111 1111 1111 PEIE CMIE T0IE RCIE Write Buffer for upper 5 bits of Program Counter INTE TXIE RBIE OSCF T0IF CCP1IE INTF TMR2IE POR RBIF TMR1IE BOR ---0 0000 0000 000x 0000 -000 ---- 1-0x 1111 1111 TXEN SYNC BRGH TRMT TX9D 0000 -010 0000 0000 xxxx xxxx xxxx xxxx WRERR WREN WR RD ---- x000 ---- --- VRR VR3 VR2 VR1 VR0 000- 0000 30 25 30 24 30 33 38 30 26 27 29 54 73 75 91 92 92 92 69

SPECIAL FUNCTION REGISTERS SUMMARY BANK1

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset(1) Details on Page

Unimplemented Unimplemented Unimplemented GIE EEIE Unimplemented Unimplemented Unimplemented Timer2 Period Register Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented CSRC TX9 Baud Rate Generator Register EEPROM Data Register EEPROM Address Register Unimplemented VREN VROE EEPROM Control Register 2 (not a physical register)

Unimplemented

- = Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.

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PIC16F627A/628A/648A
TABLE 4-5:
Address Bank 2 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh Legend: Note 1: INDF TMR0 PCL STATUS FSR PORTB PCLATH INTCON Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx Timer0 Modules Register Program Counters (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C Indirect Data Memory Address Pointer Unimplemented RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 Unimplemented Unimplemented Unimplemented GIE Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented PEIE T0IE Write Buffer for upper 5 bits of Program Counter INTE RBIE T0IF INTF RBIF xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx xxxx xxxx ---0 0000 0000 000x 30 47 30 24 30 38 30 26

SPECIAL FUNCTION REGISTERS SUMMARY BANK2

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset(1) Details on Page

- = Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented. For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.

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PIC16F627A/628A/648A
TABLE 4-6:
Address Bank 3 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh Legend: Note 1: INDF OPTION PCL STATUS FSR TRISB PCLATH INTCON Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx RBPU IRP INTEDG RP1 T0CS RP0 T0SE TO PSA PD PS2 Z PS1 DC PS0 C 1111 1111 0000 0000 0001 1xxx xxxx xxxx TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 PEIE T0IE Write Buffer for upper 5 bits of Program Counter INTE RBIE T0IF INTF RBIF ---0 0000 0000 000x Program Counters (PC) Least Significant Byte Indirect Data Memory Address Pointer Unimplemented TRISB7 TRISB6 Unimplemented Unimplemented Unimplemented GIE Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented 30 25 30 24 30 38 30 26

SPECIAL FUNCTION REGISTERS SUMMARY BANK3

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset(1) Details on Page

- = Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.

2009 Microchip Technology Inc.

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