2 Prof Hahanov

ODESSA 15 JUNE SUMMER SCHOOL
Kharkov National University of Radio Electronics
CYBERSPACE AND HUMANITY

Vladimir Hahanov
Kharkov National University of Radio Electronics, Design Automation Department, hahanov.kture.kharkov.ua
1. Education and Study

Hahanov Vladimir (Ivanovich), Doctor of Science, Professor of Computer Design Automation
of Kharkov National University of Radio Electronics (KNURE), Dean of Computer Engineering
Faculty, IEEE Computer Society Senior and Golden Core Member, Academician of the Academy of
Sciences of Applied Radio Electronics.
Address: Ukraine, 61166, Kharkov, Lenin Avenue 14, tel. (380) -57-7021326
E-mail: hahanov@kture.kharkov.ua
1. Education and training work

1996 - Doctor of Science, Kharkov State Technical University of Radio Electronics, specialty: 05.13.08computers, systems and networks, components and devices of computers and control systems; 05.13.02 mathematical modeling in scientific research. Thesis - "Models of digital and microprocessor-based structures
and methods for their analysis in the testing and diagnosis service." 1997 - Professor of Computer Aided
Design Department of KNURE.
1985 - PhD, Kharkov Institute of Radio Electronics, a specialty - control of technical systems. Thesis - "Models
of digital devices and methods for their analysis for diagnosis automation system." 1988 - Associate Professor
of Computer Science HIRE.
1978 - Systems Engineering, Kharkov Institute of Radio Electronics, a specialty - automation control
systems. Thesis - "Automatic control of digital devices.
Lectures (10): "Digital computers", "Logical modeling", "Diagnosis of computers and systems", "Electronic
computers", "Special sections of mathematics", "Fundamentals of Discrete Mathematics", "Certification and
verification of computer systems"; "Testing and optimization of computer systems and networks", "Fundamentals
of design automation of digital systems on Chip, Design and Testing of Computer Systems.
Kharkiv National University of Radio Electronics, Design Automation Department, e-mail: hahanov@kture.kharkov.ua
Science Field of Interests:
2. Science
Computer systems, networks and cyberspace engineering (Metric and analysis technology of
cyberspace, virtual machines, brain-like computing and quantum processes, Design and Testing of
computer systems and networks on chip, verification of hardware and software products).
The head of scientific school "Design, verification and testing of computer systems and networks.
Scientific and technical achievements.
1) Technology of deductive fault simulation of structural and functional violations of digital systems.
2) Methods of deterministic activation test synthesis for SoC components.
3) Technology of Verification and diagnosis of digital systems on Chip.
4) Two-frames cubic calculus and compact description of the functional and structural model for
analysis and synthesis of computer systems.
5) Models and methods of assertion-based testing and verification of hardware and software
components of the SoC.
6) Technology and metrics analysis of the information space based on the vector-associative logic of
computing structures.
7) Models and methods for brain-like quantum computing processes for the cyberspace analysis.
Supervising for PhD and Doctor of Science.
Supervisor of three doctors Eliseev(VV , Chumachenko SV Litvinova EI) and
2 PhDs (Monzharenko IV,Hanko,VV, Kovalev E., Masood Mehedi, Dzhahirul Haq, Khalil_Abu Zanuneh,
Skvortsova OB, Sysenko I., Berezhnaya M,
MA,Kolesnikov, KV, Egorov, A., Guz O., Wade, Ghribi,Hassan Kteyman,
Kaminska MA, KamenyukaEA, ParfentiyAN , Pobezhenko IA, Zaichenko SA, Christopher Ngene,
YvesTiekura, Filippenko, IA) in the field of Design Automation Systems," "Computer systems and
components. "
3. References
430 publications, 12 books (6 textbook, and 6 monographs), 2 of the invention. Among them:
1. Hahanov VI Technical diagnostics of digital and microprocessor-based structures. Tutorial. K.: IZMN. In
1995.252p.
2. Hahanov VI Technical diagnostics elements and units of personal computers. K.: IZMN. In 1997. 308 p.
3. Design and Diagnostics of Computer Systems and Networks / Bondarenko MF, Krivulya GF, Ryabtsev VG, SA
Fradkov, VI Hahanov Kiev: NMC IN, 2000. 306p.
4. Semenets VV Hahanova IV, VI Hahanov Design of digital systems using the language VHDL. Kharkov: KNURE,
2003.492p.
5. Hahanov VI, IV Hahanova VHDL + Verilog = Synthesis in a minutes. - Kharkov: KNURE. - 2006. - 264p.
6. Hahanov VI, Litvinov, E., Hahanova IV, Guz O. Design and testing of digital systems in the crystals. Kharkov:
KNURE. - 2009. - 484 p.
7. Verilog & System Verilog. Design and verification of digital systems in crystals / VI Hahanov, I. Hahanova,
E. Litvinov, OAGuz. - Kharkov: KNURE. - 2010. - 526 p.
8. Bondarenko MF, Hahanov VI, Guz OA, Shabanov, JP Kushnarenko Brain-like computing infrastructure
processes.Kharkov: KNURE. In 2010. 169p.
9. Hahanov VI, Litvinov, E., S. Chumachenko, Guz O. The logical associative computer / / E simulation. , 2011. 1
(33). P. 73-89.
10. Hahanov V., Wajeb Gharibi, Litvinova E., Chumachenko S. Information analysis infrastructure for diagnosis / /
Information an international interdisciplinary journal. , 2011.Japan. Vol.14. Number 7. P. 2419-2433.
11. Hahanov VI, Hahanova IV, Litvinov, H., Guz O. Testing and verification of HDL-models of digital systems in
crystals / / E simulation. In 2010. Number 2 (32). P. 31-39.
12. Hahanov VI, Barkalov OO, Marian Adamski. Infrastructure intellectual property for SoC simulation and diagnosis
service. Springer, 2011. P. 289-330.
4. Public and international activities

Editor-in-chief of Radio Electronics and Informatics" and Control Systems and automation devices." Member of
two specialized Boards for the defense of doctoral thesis: Design Automation," "Computer systems and
components."Chairman of the International Symposium of the annual IEEE East-West Design & Test. A
member of the editorial boards of 25 international journals, and Program Committee of international
conferences. Member of the IEEE Computer Society Society since 2001. IEEE Computer Society Golden Core
Member, 2006. Senior Member of IEEE Computer Society since 2011. Scientific adviser of corporations Aldec,
USA, Echostar, USA, DataArt Lab, Kaspersky Lab. Head of Students' Scientific Club Elite Teaching
Aldec. Member of the International Committee of the World Award of Recognition in Global IT.
5. Public relation
Participant of 33 TV programs over the past 10 years in Kharkov (7 channel, OTB, Favorite), Moscow, Leningrad,
Yerevan, Bucharest, BBC), devoted to the results of volunteer research and educational activities. Several articles
in the newspaper, and in a business magazines.
6. Honors and Awards
Diploma of the "Best Scientist of Kharkov City" in 2000 and 2001, winner of Intel's projects in the field of Design
Automation in 2003, "Excellence in Education of Ukraine", 2005, IEEE Recognition Award, 2005; IEEE Gerald
W.Gordon Award, 2005; IEEE diploma - for organizing and hosting international conferences, 2005; IEEE
Computer Society Golden Core Member, 2006. Medal winner of the concourse "Kharkov 2005", IEEE Computer
Society certificates for international recognition in 2006 and 2007, a diploma and a premium watch from the
President of Ukraine, in 2006. Diploma of winner of competition "Kharkov - the names of the best" in the category
"Best Dean" in 2008. Award Computer Society Outstanding Contribution Award from the President of the IEEE
Society. Medal of Ukraine For scientific achievement," 2009. A gold medal from the Academy of Applied Radio
Electronics, 2010.
7. Other information.
Was born February 27, 1953. Four children. Hobbies: traveling, basketball, volleyball, skiing, soccer, theater.
Trends in IT-industry
1) The number of specialized digital systems on a chip (SoC,
SiP) = 3 000 000 000.
SoC die - one billion gates, 10,000 vies (holes), 7 plates
(dies) in package SiP. The thickness of a plate (thickness)
- 5 (25) micrometers. Industrial technology of today14 nm.
Age 21 - while cloud services and service-oriented design
technologies SoC.
The stages of intellectual development of cyberspace: a)
Mouse brain - 2012. 2) Human brain - 2020. Humanity
brain -2050. Self-improving computer (SIC) - 2025.
2)
Challenges:
How to fill silicone chip by services.
How to reduce power dissipation in the SoC.
How to improve the reliability and quality of the SoC.
Reconstruction of the Internet or the infrastructure of
cyberspace.
Creating a high-speed search engines for pattern
recognition and decision-making based on a
standardized infrastructure of cyberspace.
Gartner's Hype Cycle 2011
Individual computer, not PC

The aim is to make the computer and Internet useful to improve the quality of life by continuous their
use for 24 hours when searching, pattern recognition and decision making (i.e. passport ID,
medicine, business, home, learning, vacation, traveling, communication, eating, friendship ).
Products of Intel and Microsoft are regarded as the available tools used to build standardized,
specialized, brain-like and user-friendly personal servers. How many people - so many friendly
computers, which are configured for each human. = 6 Bln specialized comps.
Market appeal of IC is determined by the entire population and all computers on the world.
Risk consists of the possibility to get out of human control self-developing information computer
ecosystem (ICES) of the world .
Problems:
1) Remove arithmetic from computer to increase the speed of brain-like (associative logic) problems
many times.
2) Create standardized data structures (table hierarchy) for ICES.
3) Develop a high speed concurrent logical associative brain-like multiprocessor without arithmetic
operations.
4) Create a theory for associative logic calculating to exact search, recognition and decision making
in information computer space of the world.
5)
6)
7)
Create simple metrics and criterion for evaluating solutions in a vector logical information space.
All facilities to be developed should be scalable and self-developing.
The incentives of ICES development are recreation and entertainment industry, focused on
qualitative satisfaction of human needs.
8)
Football and three men (Ahmetov, Jaroslavsky and Tabachnik) of the decade will raise Ukraine.
Metric and Analysis of Cyberspace Criteria

The purpose of the scalar criterion to evaluate any of the interactions in interval estimation [0,1]
through the sharing of three parameters: the minimum distance and the two functions of
not belonging. Vector criterion evaluates the structure of the interaction of objects.
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Cyberspace. Infrastructure
Cyberspace - a set of interacting in the metric of
information processes and phenomena, by
using computer systems and
networks. Or. Cyberspace is Intellectual
and informational displaying of humanity.
Virtual PC - a friendly personal cyberspace with
filters oriented to improve the quality of life for
everyone. Or. Virtual PC is Intelligent
communication interface between human
and cyberspace.
Intelligence is the ability of a subject (object) for
self-learning and self-improving the environment,
with the goal to improve the quality of life.
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ANTISPAM Infrastructure
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Matrix processor of binary operations

The module focuses on the parallel execution in
this case, one of four statements (ISA - Instruction
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The complexity of MMP transferred to a data
structure where the memory matrix is a hardwareimplemented built-in command that allows you
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parallel computing (SIMD - Single Instruction
Multiple Data), sequential in nature.
No need to build complex compilers, targeted
to parallelization of computational processes.
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14
Models of quantum computing

The market attractiveness of the qubit, or quantum computing models based on high-parallelism solutions of discrete
optimization, compression and teleportation of data, fault-tolerant design, information security through increased
hardware
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Testing and Repair service of modules (memory)
Test Generation Service

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diagnosis are reduced to complete interaction graph of four
vertices (the functionality, real device, test, defects) based on
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18
10 Projects (Last 7 Years)

SIGETEST- fault simulation and test generation for complex
digital devices
PRUS - programmable unlimited systems, spherical
multiprocessor for Boolean equations solving, Aldec
Independent Test Lab:

- INFOWATCH Mail Storage
- Kaspersky lab Antivirus
HES+ARM Board - HW/SW co-simulator for complex SoCs

verification, Aldec
Assertions Engine - temporal assertions checker

CORDIC - IP Core generator for fast calculations of
trigonometric functions in hardware
JPEG/MPEG4 SoC implementation (R&D)

OpenTEST - Knowledge testing computer system
ASFTEST - automatic test synthesis system for state
machines
Cyberspace, Virtual Computing & Engines, Ukraine (2)

Malware & Security, Sweden
19
Co-operations with global IT-industry
IEEE East-West Design & Test Symposium

EWDTS2012, Kharkov, Ukraine, 14-17 September 2012
EWDT-History analysis
Authors (1754)
Countries - 61
EWDTS 2011Authors (222)

Countries (32)
Number of countries
40
35
35
30
32
24
20
18
Bangladesh -1
Belarus -7
Brazil -1
Chech Republic - 3
Cte dIvoire -1
Estonia -4
Germany -3
India -17
27
25
15
34
32
Armenia -9
Iran -1
Israel -2
17
Italy -5
12
Japan -1
10
Malaysia - 3
Mexico -2
0
2003
2004
2005
2006
2007
2008
2009
2010
2011
Nigeria -1
Norway -3
Number of authors
400
Palestine - 1
375
353
350
Poland -8
300
Romania -5
246
250
Russia -52
227
216
222
200
Turkey - 6
155
150
Saudi Arabia -1
130
UK - 1
109
100
Ukraine - 54
50
USA - 4
Viet Nam - 1
2003
2004
2005
2006
2007
2008
2009
2010
2011
European Projects Green Cyberspace

Purpose - a significant (x100) increasing the speed search services, recognition
and decision-making through the implementation of a multiprocessor and
parallel associative and logical operations of vector analysis graph and matrix
data structures in a discrete Boolean space without using arithmetic operations.
Challenges solving:
1. To safe Energy because of low level consumption Special SoC.
2. To decrease dimensions of SoC.
3. To increase the Internet services performance
4. To improve the quality of human life (creation of myself mirror reflection).
5. To provide low cost of gadgets and Internet services.
6. To increase the Yield and Reliability of critical SoC Functionality.
1. Multiprocessor digit-free system for searching, recognition and decisionmaking for computer information ecosystem.
2. Personal virtual Infrastructure of cyber computer and cyberspace analysis.
3. Quantum digit-free computing for providing Internet services.
4. English-based Master degree Education in Ukrainian IT-Universities
22
Green Cyberspace
Quantum digit-free computing for providing Internet Services.
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(, , , , Apple iPad, Samsung Galaxy S,
Apple MacBook Air, Logitech Revue, Google Nexus One (HTC Desire), Apple iPhone 4,
Apple TV, Toshiba Libretto W100, Microsoft Kinect, Nook Color).

(monitored remote control).
,

.

,
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30

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31
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32

2) ,
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3) (
),
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: 1)
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5% . 3)
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4) 510%
. 500 ,
. 5)

.
33

(Cyber Space), -
() ,
, Google, Microsoft.

, :
1)
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2)
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34

4)

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35

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, HDL-. 2.
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(functional coverage)
. 5. (),
, HDL-
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36

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(2, 4, 8, 16, 32, 64,).

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.
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37

,
,
. ,
. - (-, ) .
. : C = {9, 10, 11}, W = {11, 12, 13}, H =
{13, 14, 15}. m =
{10,11,12}. :
C (1110000), W (0011100), H (0000111).

xor-
m (0111000) :
(m C) m C (0111000) (1110000) (1001000);

(m W) m W (0111000) (0011100) (0100100);
(m H) m H (0111000) (0000111) (0111111).
38

, (a, b, c, ab, bc) (ac, abc)
m
.
m=(1101001) , xor:
(m A1 ) m A1 (1101001) (1110000) (0011001);

(m A 2 ) m A 2 (1101001) (0011100) (1110101);
(m A 3 ) m A 3 (1101001) (0000111) (1101110).
: m
1.
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39
-

1) ;
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40
Club Elite Teaching is our brand

Partnership:
Microsoft (MS IT-academy), Intel, Cadence, Aldec, Kaspersky Lab,
Freecode, Echostar, Softline, Mentor Graphics, Synopsys, II, ADB.
Goal is the quality of graduated people must be
satisfied to the IT-industry needs!
Courses from companies:
.NET/C# programming, SQL Server, ASP.NET
Microsoft Solutions Framework
Multicore and parallel programming
omputer viruses and tools for viruses control
Hardware/Software design and testing
Hardware description language
VHDL/Verilog/SystemC
Information Technology Infrastructure Library
(ITIL)
Creation of the technological corporative
institutes as University subdivisions.
41
Essence of Club Elite Teaching

There is system of additional optional students activity, which directed to knowledge
obtaining in the high-technology field.
Club education includes:
- lectures of the best world scientists in Hardware/Software Technology;
- lectures of the best world scientists in English;
- weekly seminars;
- scientists projects, grants;
- English movie;
- Conferences organization;
- Best conferences participation in area of computer and program engineering;
- trainings and probation in foreign universities, sport and active rest.
For club education new laboratory have been created, which works with the following
direction: Hardware/Software Design and Test, RFID and Wireless, Networks Management,
Soc and NoC Design, Image and Data Compression, Security and Antivirus, Parallel
Programming.
42
Linting technology
Linting is based on design rules library
collected the valid solutions from the best
companies and designers.
HDL Design
LINTING
TOOL
REPORT
Rule example: always sensitivity list should include

all signals that are referenced within the process
DESIGN
RULES
Verification Solutions under Aldec,

USA Mixed VHDL, Verilog,
SystemVerilog, and SystemC simulators
Assertions (PSL and SVA) and LINT
Support
Graphical design creation and
debugging tools
Hardware-assisted Verification
Solutions
Hardware acceleration and
prototyping in FPGAs
Software-Hardware Co-verification
for embedded CPUs
www.aldec.com
43
43
ALINT Solution: STARC. Integration with Riviera

ALINT confirms RTL Design Style Guide from
Semiconductor Technology Academic Research
Center (STARC)
Design guide from STARC is essentials from manyyears of experience in digital electronics design by
world-leading companies (members of STARC):
www.aldec.com
44
44
Accelerated Design Simulation

Active-HDL Simulator
Import the Design

to DVM
Outline:
The design is compiled in Active-HDL
simulator
Design is divided into 2 parts: one that
should stay in simulator and one
that should go to HES board
The design runs on simulators clock
(10-100Khz)
Testbench stays in simulator
Compile the Design
Design Verification Manager (DVM)

Run co-simulation
Run Synthesis
HW Board
Run Implementation
Bitstream
45
. 1
-,

L(B, T) (B A) L(B) ( A i ) ( Li )
:
i 1, n
i 1, n
1. (coverage) .
code coverage ,
.
s t
s
t
s
t

B {B , B } B B , B B B
:
B {Bs , Bt }
i

.

- Bij Ti B j {0,1}
( ) (testbench),
1, Bij 0
Testbench HDL-
.
46
. 2
functional coverage ,

.
:
F {Fc , Ft } Fc Ft , Fc Ft F
,
,
.
(coverage driven verification)
(constraints), .
3. ,
A [A ij ]
,
f(X) A ij {0,1}

Bij 1
: 1 , 0
. :
A {Ai , A b }
47
. 3

Riviera Aldec, . 4.

, 15%
.
Time-to-market comparison
Time-to-market (KMen/Hour)
30,00
25,00
20,00
Design + Classic Testbench

Design + Stimulus + Assertions
15,00
10,00
5,00
0,00
0,112 0,207 0,315 0,389 0,504 0,620 0,731 0,824 0,931 1,015
Design capacity (MGates)
test-bench ,
, (3) (. 5),
. ,

10-20 HDL-.
48
HDL-. 1
(.) HDL-
, I-IP 1500.
-:
,
, .
-
HDL-,
,
testbench
coverage
().
.

B
A
,

or (T F);
BA-:
m
m A A (T A c ).
j
49
HDL-. 2
2. -
HDL-.
, md
.
3. ,
, .
md ,
.
4.
,
m b
50

. 1

.
Aij {1 failed , 0 passed}
:
T
T1
T2
T3
m
mi Aij T4
j1
T5
T6
T7
T8
m A ij
.
T1
1
T2
.
T3
1 T4
.
T5
.
T6
.
T7
1
T8
A1
.
.
.
1
.
.
.
.
A2
.
1
.
.
.
.
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.
A 3 A 4 A 5 A 6 A 7 A8
. . . .
. .
1 . 1 .
. .
. . . .
. .
1 . . 1 . .
. . . .
. .
. . . .
. .
. . . .
. .
1 . . .
. .
51
Product Cycles Shrinking as System Complexity Continues to

Grow
Magdy S. Abadir, East-West
Design & Test Symposium
Technology
Products
12
Months
Yervant Zorian, East-West

Design & Test Symposium
18
CPU performance 2x every 18 months

Moore law
Product development 6 to12 months, or
miss market window
System performance 2x every 8-12 months
Demand for features 10x memory growth

3-4 .

.

.

(Time-tomarket quality Yield).
52
Yield life cycle curve improving
53
Infrastructure IP in SoC
Transparent to normal
functionality of SoC (not
functional IP)
Ensures manufacturability
and lifetime reliability of SoC
Basic types of Infrastructure
IP include:
1) IP for process monitoring

2) IP for testing
3) IP for diagnosis and debug
4) IP for repair
5) IP for characterization &
measurement
6) IP for robustness and fault
tolerance
54
Life success
55
56
57
A good beginning is half a bottle!!!
58
Coffee break
59
60
61
62

2 Prof Hahanov

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ODESSA 15 JUNE SUMMER SCHOOL

Kharkov National University of Radio Electronics

CYBERSPACE AND HUMANITY

Kharkov National University of Radio Electronics, Design Automation Department, hahanov.kture.kharkov.ua

ODESSA 15 JUNE SUMMER SCHOOL

1. Education and Study

1. Education and training work

ODESSA 15 JUNE SUMMER SCHOOL

Science Field of Interests:

ODESSA 15 JUNE SUMMER SCHOOL

ODESSA 15 JUNE SUMMER SCHOOL

4. Public and international activities

ODESSA 15 JUNE SUMMER SCHOOL

ODESSA 15 JUNE SUMMER SCHOOL

ODESSA 15 JUNE SUMMER SCHOOL

Gartner's Hype Cycle 2011

ODESSA 15 JUNE SUMMER SCHOOL

Individual computer, not PC

ODESSA 15 JUNE SUMMER SCHOOL

Metric and Analysis of Cyberspace Criteria

d(a , b) d(b, c) d(a , c).

d(m, A) [1 (m A)] [1 (A m)],

d(m, A) card (mi A i U);

(m A) card (A i U) card (mi A i U);

(A m) card (mi U) card (mi A i U);

ODESSA 15 JUNE SUMMER SCHOOL

ODESSA 15 JUNE SUMMER SCHOOL

ODESSA 15 JUNE SUMMER SCHOOL

Matrix processor of binary operations

ODESSA 15 JUNE SUMMER SCHOOL

Logical Associative Multiprocessor

ODESSA 15 JUNE SUMMER SCHOOL

Models of quantum computing

ODESSA 15 JUNE SUMMER SCHOOL

Testing and Repair service of modules (memory)

ODESSA 15 JUNE SUMMER SCHOOL

Test Generation Service

The space equation of (functionality, test, defects) to

ODESSA 15 JUNE SUMMER SCHOOL

B min [B j (Bij mi )];

Bm cb c cb c(c b) c(b 1);

ODESSA 15 JUNE SUMMER SCHOOL

10 Projects (Last 7 Years)

Independent Test Lab:

HES+ARM Board - HW/SW co-simulator for complex SoCs

Assertions Engine - temporal assertions checker

JPEG/MPEG4 SoC implementation (R&D)

Cyberspace, Virtual Computing & Engines, Ukraine (2)

ODESSA 15 JUNE SUMMER SCHOOL

Co-operations with global IT-industry

ODESSA 15 JUNE SUMMER SCHOOL

IEEE East-West Design & Test Symposium

EWDTS 2011Authors (222)

ODESSA 15 JUNE SUMMER SCHOOL

European Projects Green Cyberspace

ODESSA 15 JUNE SUMMER SCHOOL

ODESSA 15 JUNE SUMMER SCHOOL

ODESSA 15 JUNE SUMMER SCHOOL

Virtual Personal Computer

ODESSA 15 JUNE SUMMER SCHOOL

ODESSA 15 JUNE SUMMER SCHOOL

ODESSA 15 JUNE SUMMER SCHOOL

ODESSA 15 JUNE SUMMER SCHOOL