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Twin Cities Campus

Outline
Basic OOP in SystemVerilog Advanced OOP in SV Random Nunber Generator Homwork today

System-Level Modeling and Verification for SystemCommunications System Verilog Lecture 4 Prof. Xiaofang Zhou ASIC & Systems, Dept. of Microeletronics FUDAN University Shanghai, CHINA

OOP in SV
What's Object Oriented Program
OO code are easier to write and maintain
Let you create complex data types Tie data with routines work with them More privacy, more safety and robustness

A first Class in SV
A class contains 3 data and 2 functions
data in a class are called "Property" subroutines in a class are called "Method"

The ": name" after endfunction / endclass are optional class BusTran;
bit [31 : 0] addr, crc, data[8]; function void display; $display("BusTran: %h", addr); endfunction : display function void calc_crc; crc = addr ^ data.xor; endfunction : calc_crc
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Class can contain other classes more features: Inheritance, Virtual methods, etc

Where to define a Class

Inside a program, module, package
Program is a piece of test code run in special time domain

outside of any thing above

endclass : BusTran

Terms in OOP
Class: a basic building block containing

Alternative way to define BusTran

Separate the prototype and body of code
class BusTran2; bit [31 : 0] addr, crc, data[8]; extern function void display; extern function void calc_crc; endclass : BusTran2

routines and variables Object: an instance of a class Handle: a pointer to an object. Handle in SV are strongly typed. Property / Method : data/task, function
There are class data and object data

type g proto definin tern" "ex code o f th e Body ::" Name "Class

Prototype: the header of a routine shows

function void BusTran2::display; $display("BusTran: %h", addr); endfunction : display function void BusTran2::calc_crc; crc = addr ^ data.xor; endfunction : calc_crc

only the name, type and argument list.

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Creating a new objects

The "new" method is for constructor only
new will allocate memory spaces, and returns the handle of the newly created object. If there's a new method in class, it will get a chance to run. Put here the code to further initialize the object data.
class BusTran3; logic [31:0] addr, crc, data[8]; function new; addr = 3; foreach (data[i]) data[i] = 5; endfunction endclass program test; BusTran3 b1, b2; initial begin b1 = new; b2 = b1; b1 = new; end endprogram
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What's happening in program test?

Line 3 declares two "BusTran3" handle Line 5 allocate the first BusTran3 object
b1.addr is initialized to 3 b1.data[0] to b1.data[7] are all 5 b1.crc is at its default value (32'bx)

Line 6 both b1 b2 points to

the same object Line 7 b1 points to a 2nd object, and b2 points to the 1st BusTran3 object.

1 2 3 4 5 6 7 8 9

program test; BusTran3 b1, b2; initial begin b1 = new; b2 = b1; b1 = new; end endprogram
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Garbage collection
SV automatically does garbage collection after an object is deallocated (no longer used)
BusTran3 b;// create handle b = new; // allocate an object b = new; // allocate a 2nd one, free the 1st b = null; // Manually deallocate the 2nd

Access object property in SV

SV code tends to access object data directly just as we access data fields in a structure
BusTran b; // create handle b = new; // allocate an object b.addr = 32'h42; // access data directly!! b.display(); // calling methods

For circular lists, you need to manually broken the links, clear all handles before SV can deallocate these object
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This methodology is questionable. But when writing testbenches, our goal is to run faster and to control over all variables to generate the widest range of stimulus values.
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Strict OOP do it differently

Strict OOP code tends to 'hide' object data,

Class data
Class data is a property that commonly

i.e. make it private, and give a pair of set/get method to user package CompE; use strict;
#!/usr/bin/perl -w use strict; use CompE; use vars qw($a); $a = CompE->new(0); $a->x(100);
set
sub new { my $proto = shift; my $type = ref $proto || $proto; my($x) = @_; $x = 0 if not $x; my($this) = {x=>$x}; bless $this, $type; } de get co sub x { my $this = shift; $this->{x} = shift if (@_); $this->{x}; } 1;
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shared between all its objects.

class BusTran5; static int count = 0; int id; function new; id = count++; endfunction endclass program test;
lize cla Initia

a ss dat

Second id =

1, count =

set/

print $a->x, "\t", $a->y, "\n"; 1;

get

BusTran5 b1, b2; initial begin b1 = new; b2 = new; $display("Second id = %d, count = %d", b2.id, b2.count); end endprogram

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'this'?
In many OOP methods, 'this' or 'self' is used to refer to the object or class itself. So does SV. SV will search a name in current scope, then look it up in higher scope, and soon, until it finds a match. In SV, you can omit the 'this.' in most case.
scope of class 'Scoping'

Using a Class inside antoher

A class can contain an instance of anther class (handle).
class BusTran6; bit [31:0] addr, crc, data[8]; Statistics stats; endclass class Statistics; time startT, stopT; static int ntrans = 0; static time total_elapsed_time; endclass

class Scoping; string oname; function new(string oname); t data this.oname = oname; Objec e' 'onam endfunction endclass

ment n argu functio ame' 'on

scope of function 'new'

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Class BusTran6 shall initialize the stats handle (calling new) Class Bustran6 can refer to things in the Statstics class using hierarchical syntax, e.g. stats.start() Separate big class into small ones if necessary
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Pass value or pass ref to routine?

C always pass values, and Perl always pass ref. C++ and Pascal support both. What about SV? By default, SV pass value to routine. Put a 'ref' in arguments' table if you'd like to pass ref to routine. Since object in SV is pointed to by handles, and you can only pass handle not object to subroutines. The subroutine can actually modify the object even when you only pass the handle value to subroutine. To modify the handle itself, you must pass a reference to subroutine.
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Example, Pass value

Following task transmit can modify object

data.
task transmit(BusTran bt); bt.timestamp = $time; endtask BusTran b; initial begin b = new(); b.addr = 42; transmit(b); end
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Example, Pass ref

Code in the Left fails. The Right one use 'ref' is correct.
task create_pckt(BusTran bt); bt = new(); bt.addr = 42; endtask BusTran b; initial begin create_packet(b); $display(b.addr); end
ill null b is st

Modifying objects in flight

task gen_bad(int n); BusTran b; b = new(); repeat (n) begin b.addr = $random(); $display(); transmit(b); end endtask ject ne o b Only o ere again h g loopin again and

task gen_good(int n); BusTran b; repeat (n) begin b = new(); b.addr = $random(); $display(); transmit(b); end in bjects New o ration endtask e ch it
ea

task create_pckt(ref BusTran bt); bt = new(); bt.addr = 42; endtask BusTran b; initial begin create_packet(b); $display(b.addr); end

valid some b hold

t objec
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SV code may run multi-threaded

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How to make a copy of object

class BusTran; bit [31:0] addr, crc, data[8]; endclass BusTran src, dst; initial begin src = new; dst = new src; end o far find s Looks class BusTran; bit [31:0] addr, crc, data[8]; static int count = 0; int id; Statistics stats; function new; stats = new; id = count++; endfunction endclass

Deep copy, write your own copy()

A deep copy will copy all the data, create

new objects and copy recursively if copy.crc = crc; necessary. copy.data = data;
class BusTran; bit [31:0] addr, crc, data[8]; static int count = 0; int id; Statistics stats; function new; stats = new; id = count++; endfunction function BusTran copy; copy = new; copy.addr = addr; copy.stats = stats.copy; id = count++; endfunction endclass BusTran src, dst; initial begin src = new; src.stats.startT = 42; dst = src.copy; dst.stats.startT = 84; end
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BusTran src, dst; initial begin src = new; handle = new handle src.stats.startT = 42; is a shallow copy. It only dst = new src; dst.stats.startT = 84; copies the top level object. e end he sam ares t dst sh ject d src an stats ob
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Public vs. Private

Unlike C++, in SV, everything in object is

Outline
Basic OOP in SystemVerilog Advanced OOP in SV Class example Composition Inheritance (extended class) Virtual Function Random Nunber Generator Homwork today

public, unless labeled private.

Testbenches are not like other programs. Testbenches need to touch every part of

DUT, either monitoring, or injecting errors.

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Class example
Task: Write a class that generate wave forms to test our ADC_Adapter DUT There's unlimited kinds of waveforms (DC, square wave, saw tooth, ). May we simplify the job with OOP? One big class or several relative small classes? Does SV OOP support composition, inheritance, virtual functions?
Square Source DC Source DC Saw Tooth Source

Solution I: One big class

Easy understood, but not easy to make extension, nor to maintain. Doesn't take the advantages of OOP at all.
module test_AAdpter_I; class Source_AllinOne; int PERIOD; int MID; int MAX; int MIN; int AMP; int n; int result; function new(int period = 200, mid = 2048, max = 4097, min = 0, amp = 2000); PERIOD = period; MID = mid; MAX = max; MIN = min; AMP = amp; endfunction function int runDC; runDC = calcDC(); n++; if (n >= PERIOD) n = 0; endfunction function int calcDC; result = MID; calcDC = result; endfunction

s elds a data fi nts nsta co data object

Saw to

oth

function int runSawTooth; runSawTooth = calcSawTooth(); n++; if (n >= PERIOD) n = 0; endfunction function int calcSawTooth; result = n * AMP * 2 / PERIOD - AMP + MID; if (result < MIN) result = MIN; if (result > MAX) result = MAX; calcSawTooth = result; endfunction // more other waveform code // endclass Source_AllinOne S;

ADC behavior module

uctor constr

s t kind ifferen s Call d ethod of m

DUT
ADC adapter wishbone slave/master Checker

DC

initial begin S = new; repeat(1000) begin $display(S.runSawTooth); end end endmodule

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Solution II: Composition

Code is still clumsy
module test_AAdpter_II; class Source; int PERIOD; int MID; int MAX; int MIN; int AMP; int n; int result; function new(int period = 200, mid = 2048, max = 4097, min = 0, amp = 2000); PERIOD = period; MID = mid; MAX = max; MIN = min; AMP = amp; endfunction function int run; run = calc(); n++; if (n >= PERIOD) n = 0; endfunction function int calc; result = MID; calc = result; endfunction endclass class SawTooth; Source S; function new(int period = 200, mid = 2048, max = 4097, min = 0, amp = 2000); S = new(period, mid, max, min, amp); endfunction

Solution III: Inheritance

Direct borrow data and method from parent class
module test_AAdpter_III; class Source; int PERIOD; int MID; int MAX; int MIN; int AMP; int n; int result; function new(int period = 200, mid = 2048, max = 4097, min = 0, amp = 2000); PERIOD = period; MID = mid; MAX = max; MIN = min; AMP = amp; endfunction function int run; run = calc(); n++; if (n >= PERIOD) n = 0; endfunction function int calc; result = MID; calc = result; endfunction endclass

de ted co repea

function int run; run = calc(); S.n++; if (S.n >= S.PERIOD) S.n = 0; endfunction function int calc; S.result = S.n * S.AMP * 2 / S.PERIOD - S.AMP + S.MID; if (S.result < S.MIN) S.result = S.MIN; if (S.result > S.MAX) S.result = S.MAX; calc = S.result; endfunction endclass SawTooth S; initial begin S = new; repeat(1000) begin $display(S.run); end end endmodule

is? ove th e rem Can w

ted repea

code

ov class SawTooth extends Source; e rem function int run; Can w run = calc (); n++; if (n >= PERIOD) n = 0; endfunction function int calc; result = n * AMP * 2 / PERIOD - AMP + MID; if (result < MIN) result = MIN; if (result > MAX) result = MAX; calc = result; endfunction endclass
SawTooth S; initial begin S = new; repeat(1000) begin $display(S.run); end end endmodule

e this?

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Solution IV: Virtual Function

Virtual function. Indirect call
module test_AAdpter_IV; class Source; int PERIOD; int MID; int MAX; int MIN; int AMP; int n; int result;

Solution V: "Pure Virtual Function"

module test_AAdpter_V; class Source; int MID; int MAX; int MIN; int n; int result;

pe prototy same

class SawTooth extends Source; virtual function int calc; result = n * AMP * 2 / PERIOD - AMP + MID; if (result < MIN) result = MIN; if (result > MAX) result = MAX; calc = result; endfunction endclass SawTooth S;

ciate ins tan vel Don't t le bstrac ectly the a ir lass d base c

function new(int period = 200, mid = 2048, max = 4097, min = 0, amp = 2000); super.new(mid, max, min); PERIOD = period; AMP = amp; endfunction virtual function void step; super.step(); if (n >= PERIOD) n = 0; endfunction endclass class SawTooth extends Period; virtual function int calc; result = n * AMP * 2 / PERIOD - AMP + MID; if (result < MIN) result = MIN; if (result > MAX) result = MAX; calc = result; endfunction endclass SawTooth S; initial begin S = new; repeat(1000) begin $display(S.run); end end

initial begin function new(int period = 200, mid = 2048, S = new; max = 4097, min = 0, amp = 2000); repeat(1000) begin PERIOD = period; $display(S.run); MID = mid; end MAX = max; MIN = min; end AMP = amp; endfunction endmodule function int run; run = calc (); calc" n++; rrect " if (n >= PERIOD) n = 0; the co Call endfunction virtual function int calc; result = MID; od calc = result; l meth Virtua endfunction endclass

function new(int mid = 2048, max = 4097, min = 0); MID = mid; MAX = max; MIN = min; endfunction virtual function void step; n++; endfunction virtual function int calc; // $display("Can't call me directly"); calc = MID; endfunction function int run; run = calc(); step(); endfunction endclass class Period extends Source; int PERIOD; int AMP;

endmodule

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Outline
Basic OOP in SystemVerilog Advanced OOP in SV Random Nunber Generator Homwork today Theory:

Design Example Random-Number Generator

Xi+1=(a*Xi+c) mod m, i = 0, 1, 2,
when c != 0, (Wont be discussed here) when c == 0, m is a prime number, the maximun period of sequence X is Pmax = m 1; X0 within [1..m-1], Dont set X0 to 0. when c == 0, m is 2b, Pmax = m/4.

Lets select c = 0, m = 4093 (i.e 212-3), and

find a suitable a for our PRNG.

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prime m, choose good value for a

A perl script to check period for each a results
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.

Class Example
A class implements the previous PRNG
1. class OOPRNG4093; 2. logic [11 : 0] x; 3. function new(logic [11 : 0]n); 4. this.Srand(n); 5. endfunction 6. function void Srand(logic [11 : 0] n); 7. x = n % 4093; 8. endfunction 9. function logic [11 : 0] Rand(); 10. x = (x*7) % 4093; 11. Rand = x; 12. endfunction 13. endclass 14. 15. 16. 17. 18. 19. 20.
# # # # # # # # # # # # # # # # # # # # 700 807 1556 2706 2570 1618 3140 1515 2419 561 3927 2931 52 364 2548 1464 2062 2155 2806 3270

#!/usr/bin/perl -w use strict; my ($X, $a, %h, $n); my $M = 4093; for $a (1..20) { ($X, $n, %h) = (1, 1); until (exists $h{$X}) { $h{$X} = $n++; $X = ($X * $a) % $M; } print "$a, period ", $n - $h{$X}, "\n"; }

14. 1;

1, period 1 2, period 4092 3, period 341 4, period 2046 5, period 4092 6, period 4092 7, period 4092 8, period 1364 9, period 341 10, period 22 11, period 2046 12, period 2046 13, period 1364 14, period 682 15, period 4092 16, period 1023 17, period 31 18, period 4092 19, period 4092 20, period 372

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module test_OO; OOPRNG4093 A; initial begin A = new(100); repeat(20) $display(A.Rand); end endmodule

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Homework
Implement the PRNG in RTL code.
Synthesizable systemverilog or verilog code 12 bit Wishbone interface
Wishbone write calls Srand Ignore writen value outside of [1..4092] Wishbone read calls Rand

Conclusions
Inheritance and virtual function are useful

Use + operator instead of net list adder Try to avoid * % > < operators Document your design in doc (not docx) file before starting coding. Send your .doc, .sv, tb.sv with your student id in subject to svsc@xfzhou.almostmy.com
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tools to design very nice classes. The base class shall be describing something in higher level, or something abstract Leave callbacks in your class. Be more friendly with design reuse

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References

IEEE Standard for SystemVerilog Unified Hardware Design, Specification, and Verification Language, IEEE, IEEE Std 1800TM 2005, 22 November 2005. S. Sutherland, S. Davidmann and P. Flake, SystemVerilog for Design, Kluwer Academic Publishers, 2004. C. Spear, SystemVerilog for Verification, Springer, 2006. S. Vijayaraghavan and M. Ramanathan, A Practical Guide for SystemVerilog Assertions, Springer, 2005 SystemVerilog Tutorials, Doulos Ltd., http://www.doulos.com/knowhow/sysverilog/tutorial/ SystemVerilog Tutorial, electroSofts.com, http://electrosofts.com/systemverilog/ Jerry Bankds, J.S. Carson II, etc, Discrete-Event System Simulation (4th Ed), Chapter 7 Random-Number Generation (, 20059)
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Thank You

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