Chapter 2.

- DC Biasing - BJTs
Objectives To Understand : Concept of Operating point and stability Analyzing Various biasing circuits and their comparison with respect to stability BJT A Review Invented in 1948 by Bardeen, Brattain and Shockley Contains three adjoining, alternately doped semiconductor regions: Emitter (E), Base (B), and Collector (C) The middle region, base, is very thin Emitter is heavily doped compared to collector. So, emitter and collector are not interchangeable.

Three operating regions Linear region operation: Base emitter junction forward biased Base collector junction reverse biased Cutoff region operation: Base emitter junction reverse biased Base collector junction reverse biased Saturation region operation: Base emitter junction forward biased Base collector junction forward biased

Three operating regions of BJT Cut off: VCE = VCC, IC 0 Active or linear : VCE VCC/2 , IC IC max/2 Saturation: VCE 0 , IC IC max

Q-Point (Static Operation Point)

The values of the parameters IB, IC and VCE together are termed as operating point or Q ( Quiescent) point of the transistor.

Q-Point The intersection of the dc bias value of IB with the dc load line determines the Qpoint. It is desirable to have the Q-point centered on the load line. Why? When a circuit is designed to have a centered Q-point, the amplifier is said to be midpoint biased. Midpoint biasing allows optimum ac operation of the amplifier.

Introduction - Biasing The analysis or design of a transistor amplifier requires knowledge of both the dc and ac response of the system.In fact, the amplifier increases the strength of a weak signal by transferring the energy from the applied DC source to the weak input ac signal The analysis or design of any electronic amplifier therefore has two components: The dc portion and The ac portion During the design stage, the choice of parameters for the required dc levels will affect the ac response. What is biasing circuit? Once the desired dc current and voltage levels have been identified, a network must be constructed that will establish the desired values of IB, IC and VCE, Such a network is known as biasing circuit. A biasing network has to preferably make use of one power supply to bias both the junctions of the transistor.

Purpose of the DC biasing circuit To turn the device ON To place it in operation in the region of its characteristic where the device operates most linearly, i.e. to set up the initial dc values of IB, IC, and VCE

Important basic relationship VBE = 0.7V IE = ( + 1) IB IC IC = IB

Biasing circuits: Fixed bias circuit Emitter bias Voltage divider bias DC bias with voltage feedback Miscellaneous bias

Fixed bias

The simplest transistor dc bias configuration. For dc analysis, open all the capacitance.

DC Analysis Applying KVL to the input loop: VCC = IBRB + VBE From the above equation, deriving for IB, we get, IB = [VCC VBE] / RB The selection of RB sets the level of base current for the operating point. Applying KVL for the output loop: VCC = ICRC + VCE Thus, VCE = VCC ICRC

In circuits where emitter is grounded, VCE = VE VBE = VB

Design and Analysis Design: Given IB, IC , VCE and VCC, or IC , VCE and , design the values of RB, RC using the equations obtained by applying KVL to input and output loops. Analysis: Given the circuit values (VCC, RB and RC), determine the values of IB, IC , VCE using the equations obtained by applying KVL to input and output loops.

Problem Analysis Given the fixed bias circuit with VCC = 12V, RB = 240 k, RC = 2.2 k and = 75. Determine the values of operating point. Equation for the input loop is: IB = [VCC VBE] / RB where VBE = 0.7V, thus substituting the other given values in the equation, we get IB = 47.08uA IC = IB = 3.53mA VCE = VCC ICRC = 4.23V When the transistor is biased such that IB is very high so as to make IC very high such that ICRC drop is almost VCC and VCE is almost 0, the transistor is said to be in saturation. IC sat = VCC / RC in a fixed bias circuit.

Verification Whenever a fixed bias circuit is analyzed, the value of ICQ obtained could be verified with the value of ICSat ( = VCC / RC) to understand whether the transistor is in active region. In active region, ICQ = ( ICSat /2)

Load line analysis A fixed bias circuit with given values of VCC, RC and RB can be analyzed ( means, determining the values of IBQ, ICQ and VCEQ) using the concept of load line also. Here the input loop KVL equation is not used for the purpose of analysis, instead, the output characteristics of the transistor used in the given circuit and output loop KVL equation are made use of.

The method of load line analysis is as below:

1. Consider the equation VCE = VCC ICRC This relates VCE and IC for the given IB and RC 2. Also, we know that, VCE and IC are related through output characteristics We know that the equation, VCE = VCC ICRC represents a straight line which can be plotted on the output characteristics of the transistor. Such line drawn as per the above equation is known as load line, the slope of which is decided by the value of RC ( the load). Load line

The two extreme points on the load line can be calculated and by joining which the load line can be drawn. To find extreme points, first, Ic is made 0 in the equation: VCE = VCC ICRC . This gives the coordinates (VCC,0) on the x axis of the output characteristics. The other extreme point is on the y-axis and can be calculated by making VCE = 0 in the equation VCE = VCC ICRC which gives IC( max) = VCC / RC thus giving the coordinates of the point as (0, VCC / RC). The two extreme points so obtained are joined to form the load line. The load line intersects the output characteristics at various points corresponding to different IBs. The actual operating point is established for the given IB.

Q point variation As IB is varied, the Q point shifts accordingly on the load line either up or down depending on IB increased or decreased respectively. As RC is varied, the Q point shifts to left or right along the same IB line since the slope of the line varies. As RC increases, slope reduces ( slope is -1/RC) which results in shift of Q point to the left meaning no variation in IC and reduction in VCE . Thus if the output characteristics is known, the analysis of the given fixed bias circuit or designing a fixed bias circuit is possible using load line analysis as mentioned above.

Emitter Bias It can be shown that, including an emitter resistor in the fixed bias circuit improves the stability of Q point. Thus emitter bias is a biasing circuit very similar to fixed bias circuit with an emitter resistor added to it.

Input loop

Writing KVL around the input loop we get, VCC = IBRB + VBE + IERE We know that, IE = (+1)IB (2) Substituting this in (1), we get,

(1)

VCC = IBRB + VBE + (+1)IBRE VCC VBE = IB(RB + (+1) RE) Solving for IB: IB = (VCC VBE ) /[(RB + (+1) RE)] 6

The expression for IB in a fixed bias circuit was, IB = (VCC VBE ) /RB Equivalent input loop:

REI in the above circuit is (+1)RE which means that, the emitter resistance that is common to both the loops appears as such a high resistance in the input loop. Thus Ri = (+1)RE ( more about this when we take up ac analysis)

Output loop

Collector emitter loop Applying KVL, VCC = ICRC + VCE + IERE

IC is almost same as IE

Thus, VCC = ICRC + VCE + ICRE = IC (RC + RE) +VCE VCE = VCC - IC (RC + RE) Since emitter is not connected directly to ground, it is at a potential VE, given by, VE = IERE VC = VCE + VE OR VC = VCC ICRC Also, VB = VCC IBRB OR VB = VBE + VE Problem: Analyze the following circuit: given = 75, VCC = 16V, RB = 430k, RC = 2k and RE = 1k

Solution: IB = (VCC VBE ) /[(RB + (+1) RE)] = ( 16 0.7) / [ 430k + (76) 1k] = 30.24A IC = ( 75) (30.24A) = 2.27mA VCE = VCC - IC (RC + RE) = 9.19V VC = VCC ICRC = 11.46V VE = VC VCE = 2.27V VB = VBE + VE = 2.97V VBC = VB VC = 2.97 11.46 = - 8.49V

Improved bias stability Addition of emitter resistance makes the dc bias currents and voltages remain closer to their set value even with variation in transistor beta temperature

Stability In a fixed bias circuit, IB does not vary with and therefore whenever there is an increase in , IC increases proportionately, and thus VCE reduces making the Q point to drift towards saturation.In an emitter bias circuit, As increases, IB reduces, maintaining almost same IC and VCE thus stabilizing the Q point against variations. Saturation current In saturation VCE is almost 0V, thus Thus, saturation current Load line analysis The two extreme points on the load line of an emitter bias circuit are, (0, VCC / [ RC + RE ]) on the Y axis, and ( VCC, 0) on the X axis. Voltage divider bias
+V CC

VCC = IC ( RC + RE ) IC,sat = VCC / ( RC + RE )

RC R1 v out v in C1 C2

R2 RE C3

This is the biasing circuit wherein, ICQ and VCEQ are almost independent of . The level of IBQ will change with so as to maintain the values of ICQ and VCEQ almost same, thus maintaining the stability of Q point. Two methods of analyzing a voltage divider bias circuit are: Exact method can be applied to any voltage divider circuit Approximate method direct method, saves time and energy, can be applied in most of the circuits. Exact method In this method, the Thevenin equivalent network for the network to the left of the base terminal to be found.

To find Rth:

From the above circuit, Rth = R1| | R2 = R1 R2 / (R1 + R2)

10

To find Eth

From the above circuit, Eth = VR2 = R2VCC / (R1 + R2)

In the above network, applying KVL ( Eth VBE) = IB [ Rth +( + 1) RE ] IB = ( Eth VBE) / [ Rth +( + 1) RE ] Analysis of Output loop KVL to the output loop: VCC = ICRC + VCE + IERE IE IC Thus, VCE = VCC IC (RC + RE)

Note that this is similar to emitter bias circuit.

11

Problem For the circuit given below, find IC and VCE. Given the values of R1, R2, RC, RE and = 140 and VCC = 18V. For the purpose of DC analysis, all the capacitors in the amplifier circuit are opened.

Solution Considering exact analysis: 1. Let us find Rth = R1| | R2 = R1 R2 / (R1 + R2) = 3.55K 2. Then find 3. Then find IB Eth = VR2 = R2VCC / (R1 + R2) = 1.64V IB = ( Eth VBE) / [ Rth +( + 1) RE ] = 4.37A 4. Then find 5. Then find IC = IB = 0.612mA VCE = VCC IC (RC + RE) = 12.63V

12

Approximate analysis: The input section of the voltage divider configuration can be represented by the network shown in the next slide. Input Network

The emitter resistance RE is seen as (+1)RE at the input loop. If this resistance is much higher compared to R2, then the current IB is much smaller than I2 through R2. This means, Ri >> R2 OR (+1)RE 10R2 OR RE 10R2 This makes IB to be negligible. Thus I1 through R1 is almost same as the current I2 through R2. Thus R1 and R2 can be considered as in series. Voltage divider can be applied to find the voltage across R2 ( VB) VB = VCCR2 / ( R1 + R2) Once VB is determined, VE is calculated as, VE = VB VBE After finding VE, IE is calculated as, IE = VE / RE IE IC VCE = VCC IC ( RC + RE)

13

Problem Given: VCC = 18V, R1 = 39k , R2 = 3.9k , RC = 4k , RE = 1.5k and = 140. Analyse the circuit using approximate technique. In order to check whether approximate technique can be used, we need to verify the condition, RE 10R2 Here, Thus the condition Solution Thus approximate technique can be applied. RE = 210 k and 10R2 = 39 k RE 10R2 satisfied

1. Find VB = VCCR2 / ( R1 + R2) = 1.64V 2. Find VE = VB 0.7 = 0.94V 3. Find IE = VE / RE = 0.63mA = IC 4. Find VCE = VCC IC(RC + RE) = 12.55V Comparison Exact Analysis IC = 0.612mA VCE = 12.63V Approximate Analysis IC = 0.63mA VCE = 12.55V

Both the methods result in the same values for IC and VCE since the condition RE 10R2 is satisfied. It can be shown that the results due to exact analysis and approximate analysis have more deviation if the above mentioned condition is not satisfied. For load line analysis of voltage divider network, Ic,max = VCC/ ( RC+RE) when VCE = 0V and VCE max = VCC when IC = 0.

14

DC bias with voltage feedback

Input loop

Applying KVL for Input Loop: VCC = IC1RC + IBRB + VBE + IERE Substituting for IE as ( +1)IB and solving for IB, IB = ( VCC VBE) / [ RB + ( RC + RE)] Output loop

15

Neglecting the base current, KVL to the output loop results in, VCE = VCC IC ( RC + RE)

DC bias with voltage feedback

Input loop

Applying KVL to input loop: VCC = IC|RC + IBRB + VBE + IERE IC| IC and IC IE Substituting for IE as ( +1)IB [ or as IB] and solving for IB, IB = ( VCC VBE) / [ RB + ( RC + RE)] Output loop

16

Neglecting the base current, and applying KVL to the output loop results in, VCE = VCC IC ( RC + RE) In this circuit, improved stability is obtained by introducing a feedback path from collector to base. Sensitivity of Q point to changes in beta or temperature variations is normally less than that encountered for the fixed bias or emitter biased configurations. Problem: Given: VCC = 10V, RC = 4.7k, RB = 250 and RE = 1.2k. = 90. Analyze the circuit. IB = ( VCC VBE) / [ RB + ( RC + RE)] = 11.91A IC = ( IB ) = 1.07mA VCE = VCC IC ( RC + RE) = 3.69V In the above circuit, Analyze the circuit if = 135 ( 50% increase). With the same procedure as followed in the previous problem, we get IB = 8.89A IC = 1.2mA VCE = 2.92V 50% increase in resulted in 12.1% increase in IC and 20.9% decrease in VCEQ

Problem 2: 17

Determine the DC level of IB and VC for the network shown:

Solution: Open all the capacitors for DC analysis. RB = 91 k + 110 k = 201k IB = ( VCC VBE) / [ RB + ( RC + RE)] = (18 0.7) / [ 201k + 75( 3.3+0.51)] = 35.5A IC = IB = 2.66mA VCE = VCC (ICRC) = 18 ( 2.66mA)(3.3k) = 9.22V Load line analysis The two extreme points of the load line IC,max and VCE, max are found in the same as a voltage divider circuit. IC,max = VCC / (RC + RE) Saturation current VCE, max Cut off voltage

Miscellaneous bias configurations 18

There are a number of BJT bias configurations that do not match the basic types of biasing that are discussed till now. Miscellaneous bias (1) Analyze the circuit in the next slide. Given = 120

Solution This circuit is same as DC bias with voltage feedback but with no emitter resistor. Thus the expression for IB is same except for RE term. IB = (VCC VBE) / ( RB + RC) = ( 20 0.7) / [680k + (120)(4.7k)] = 15.51A IC = IB = 1.86mA VCE = VCC ICRC = 11.26V = VCE VB = VBE = 0.7V VBC = VB VC = 0.7V 11.26V = - 10.56V

Miscellaneous bias (2) 19

Equivalent circuit

Input loop

Output loop 20

Solution The above circuit is fixed bias circuit. Applying KVL to input loop: VEE = VBE + IBRB IB = ( VEE VBE) / RB = 83A IC = IB = 3.735mA VC = -ICRC = - 4.48V VB = - IBRB = - 8.3V Miscellaneous bias (3) Determine VCE,Q and IE for the network. Given = 90 ( Note that the circuit given is common collector mode which can be identified by No resistance connected to the collector output taken at the emitter)

21

Input loop

Writing KVL to input loop: VEE = IBRB + VBE + (+1)IBRE IB = (VEE VBE ) / [RB + (+1) RE] = ( 20 0.7) / [ 240K + (91)(2K)] = 45.73A IC = IB = 4.12mA

22

Output loop

Applying KVL to the output loop: VEE = VCE + IERE IE = (+1) IB = 4.16mA, VEE = 20V VCE = VEE IERE = 11.68V Miscellaneous bias (4) Find VCB and IB for the Common base configuration given: Given: = 60

Input loop

23

Applying KVL to input loop IE = ( VEE VBE ) / RE = 2.75mA IE = IC = 2.75mA IB = IC / = 45.8A Output loop

Applying KVL to output loop: VCC = ICRC + VCB VCB = VCC ICRC = 3.4V Miscellaneous bias (5) Determine VC and VB for the network given below. Given = 120 Note that this is voltage divider circuit with split supply. ( +VCC at the collector and VEE at the emitter)

24

Thevinin equivalent at the input

Rth= (8.2k)(2.2k) / [ 8.2k+2.2k] = 1.73k I = (VCC + VEE) / [R1 + R2] = ( 20 + 20) / ( 8.2K + 2.2K) = 3.85mA Eth = IR2 VEE = - 11.53V Equivalent circuit

25

Applying KVL: VEE Eth VBE ( +1)IBRE IBRth = 0 IB = ( VEE Eth VBE ) / [( +1) RE + Rth ] = 35.39A IC = IB = 4.25mA VC = VCC ICRC = 8.53V VB = - Eth IBRth = - 11.59V Design Operations: Designing a circuit requires Understanding of the characteristics of the device The basic equations for the network Understanding of Ohms law, KCL, KVL If the transistor and supplies are specified, the design process will simply determine the required resistors for a particular design. Once the theoretical values of the resistors are determined, the nearest standard commercial values are normally chosen. Operating point needs to be recalculated with the standard values of resistors chosen and generally the deviation expected would be less than or equal to 5%. Problem: Given ICQ = 2mA and VCEQ = 10V. Determine R1 and RC for the network shown:

Solution

26

To find R1: 1. 2. Find VB. And to find VB, find VE because, VB = VE + VBE Thus, VE = IERE and IE IC = 2mA = (2mA)(1.2k) = 2.4V 3. VB =2.4 + 0.7 = 3.1V 4. Also, VB = VCCR2 /(R1 + R2) 3.1 = (18)(18k) / R1+18k Thus, R1 = 86.52k

To find RC : Voltage across RC = VCC ( VCE + IERE) = 18 [ 10 + (2mA)1.2k] = 5.6V RC = 5.6/2mA = 2.8K Nearest standard values are, R1 = 82k + 4.7 k = 86.7 k where as calculated value is 86.52 k . RC = 2.7k in series with 1k = 2.8k both would result in a very close value to the design level. Problem 2 The emitter bias circuit has the following specifications: ICQ = 1/2Isat, Isat = 8mA, VC = 18V, VCC = 18V and = 110. Determine RC , RE and RB. Solution: ICQ = 4mA VRC = (VCC VC) = 10V RC = VRC / ICQ, = 10/4mA = 2.5k To find RE: ICsat = VCC / (RC + RE) To find RB: Find IB where, IB = IC / = 36.36A Also, for an emitter bias circuit, IB = (VCC VBE) / RB+( +1) RE Thus, RB = 639.8 k Standard values: RC = 2.4 k, RE = 1 k, RB = 620 k

27

8mA = 28 / ( 2.5k + RE) Thus, RE = 1k Transistor switching networks: Through proper design transistors can be used as switches for computer and control applications. When the input voltage VB is high ( logic 1), the transistor is in saturation ( ON). And the output at its collector = VCE is almost 0V( Logic 0) Transistor as a switch When the base voltage VB is low( logic 0), i.e, 0V, the transistor is cutoff( Off) and IC is 0, drop across RC is 0 and therefore voltage at the collector is VCC.( logic 1) Thus transistor switch operates as an inverter. This circuit does not require any DC bias at the base of the transistor. Design When Vi ( VB) is 5V, transistor is in saturation and ICsat Just before saturation, IB,max = IC,sat / DC Thus the base current must be greater than IB,max to make the transistor to work in saturation. Analysis

28

When Vi = 5V, the resulting level of IB is IB = (Vi 0.7) / RB = ( 5 0.7) / 68k = 63A ICsat = VCC / RC = 5/0.82k = 6.1mA Verification ( IC,sat / ) = 48.8A Thus IB > ( IC,sat / ) which is required for a transistor to be in saturation. A transistor can be replaced by a low resistance Rsat when in saturation ( switch on) Rsat = VCE sat/ ICsat (VCE sat is very small and ICsat is IC,max is maximum current) A transistor can be replaced by a high resistance Rcutoff when in cutoff ( switch on) Problem Determine RB and RC for the inverter of figure:

IC sat = VCC / RC 10mA = 10V/ RC RC = 1k IB just at saturation = IC sat / = 10mA / 250 = 40A Choose IB> IC sat / , 60 A

29

IB = (Vi 0.7) / RB 60 A = ( 10 0.7) / RB RB = 155k Choose RB = 150k, standard value, re calculate IB, we get IB = 62 A which is also > IC sat / Thus, RC = 1k and RB = 155k Switching Transistors Transistor ON time = delay time + Rise time Delay time is the time between the changing state of the input and the beginning of a response at the output. Rise time is the time from 10% to 90% of the final value. Transistor OFF time = Storage time + Fall time For an ON transistor, VBE should be around 0.7V For the transistor to be in active region, VCE is usually about 25% to 75% of VCC. If VCE = almost VCC, probable faults: the device is damaged connection in the collector emitter or base emitter circuit loop is open. One of the most common mistake in the lab is usage of wrong resistor value. Check various voltages with respect to ground. Calculate the current values using voltage readings rather than measuring current by breaking the circuit. Problem 1 Check the fault in the circuit given.

30

Problem - 2

PNP transistors The analysis of PNP transistors follows the same pattern established for NPN transistors. The only difference between the resulting equations for a network in which an npn transistor has been replaced by a pnp transistor is the sign associated with particular quantities. PNP transistor in an emitter bias

31

Applying KVL to Input loop: VCC = IBRB +VBE+IERE Thus, IB = (VCC VBE) / [RB + (+1) RE] Applying KVL Output loop: VCE = - ( VCC ICRC) Bias stabilization The stability of a system is a measure of the sensitivity of a network to variations in its parameters. In any amplifier employing a transistor the collector current IC is sensitive to each of the following parameters. increases with increase in temperature. Magnitude of VBE decreases about 2.5mV per degree Celsius increase in temperature. ICO doubles in value for every 10 degree Celsius increase in temperature. T (degree Celsius) Ico (nA) VBE (V)

- 65 25 100 175 Stability factors S (ICO) = IC / IC0 S (VBE) = IC / VBE S () = IC /

0.2 x 10-3 0.1 20 3.3 x 103

20 50 80 120

0.85 0.65 0.48 0.3

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Networks that are quite stable and relatively insensitive to temperature variations have low stability factors. The higher the stability factor, the more sensitive is the network to variations in that parameter. S( ICO) Analyze S( ICO) for emitter bias configuration fixed bias configuration Voltage divider configuration

For the emitter bias configuration, S( ICO) = ( + 1) [ 1 + RB / RE] / [( + 1) + RB / RE] If RB / RE >> ( + 1) , then S( ICO) = ( + 1) For RB / RE <<1, S( ICO) 1 Thus, emitter bias configuration is quite stable when the ratio RB / RE is as small as possible. Emitter bias configuration is least stable when RB / RE approaches ( + 1) . Fixed bias configuration S( ICO) = ( + 1) [ 1 + RB / RE] / [( + 1) + RB / RE] = ( + 1) [RE + RB] / [( + 1) RE + RB] By plugging RE = 0, we get S( ICO) = + 1 This indicates poor stability. Voltage divider configuration S( ICO) = ( + 1) [ 1 + RB / RE] / [( + 1) + RB / RE] Here, replace RB with Rth S( ICO) = ( + 1) [ 1 + Rth / RE] / [( + 1) + Rth / RE] Thus, voltage divider bias configuration is quite stable when the ratio Rth / RE is as small as possible.

33

Physical impact In a fixed bias circuit, IC increases due to increase in IC0. [IC = IB + (+1) IC0] IB is fixed by VCC and RB. Thus level of IC would continue to rise with temperature a very unstable situation. In emitter bias circuit, as IC increases, IE increases, VE increases. Increase in VE reduces IB. IB = [VCC VBE VE] / RB. A drop in IB reduces IC.Thus, this configuration is such that there is a reaction to an increase in IC that will tend to oppose the change in bias conditions. In the DC bias with voltage feedback, as IC increases, voltage across RC increases, thus reducing IB and causing IC to reduce. The most stable configuration is the voltage divider network. If the condition RE >>10R2, the voltage VB will remain fairly constant for changing levels of IC. VBE = VB VE, as IC increases, VE increases, since VB is constant, VBE drops making IB to fall, which will try to offset the increases level of IC. S(VBE) S(VBE) = IC / VBE For an emitter bias circuit, S(VBE) = - / [ RB + ( + 1)RE] If RE =0 in the above equation, we get S(VBE) for a fixed bias circuit as, S(VBE) = - / RB. For an emitter bias, S(VBE) = - / [ RB + ( + 1)RE] can be rewritten as, S(VBE) = - (/RE )/ [RB/RE + ( + 1)] If ( + 1)>> RB/RE, then S(VBE) = - (/RE )/ ( + 1) = - 1/ RE

The larger the RE, lower the S(VBE) and more stable is the system. Total effect of all the three parameters on IC can be written as, IC = S(ICO) ICO + S(VBE) VBE + S() General conclusion: The ratio RB / RE or Rth / RE should be as small as possible considering all aspects of design. 34

CHAPTER.4: Transistor at low frequencies

Introduction Amplification in the AC domain BJT transistor modeling The re Transistor Model The Hybrid equivalent Model

Introduction There are three models commonly used in the small signal ac analysis of transistor networks: The re model The hybrid model The hybrid equivalent model

Amplification in the AC domain The transistor can be employed as an amplifying device, that is, the output ac power is greater than the input ac power. The factor that permits an ac power output greater than the input ac power is the applied DC power. The amplifier is initially biased for the required DC voltages and currents. Then the ac to be amplified is given as input to the amplifier. If the applied ac exceeds the limit set by dc level, clipping of the peak region will result in the output. Thus, proper (faithful) amplification design requires that the dc and ac components be sensitive to each others requirements and limitations. The superposition theorem is applicable for the analysis and design of the dc and ac components of a BJT network, permitting the separation of the analysis of the dc and ac responses of the system. BJT Transistor modeling The key to transistor small-signal analysis is the use of the equivalent circuits (models). A MODEL IS A COMBINATION OF CIRCUIT ELEMENTS LIKE VOLTAGE OR CURRENT SOURCES, RESISTORS, CAPACITORS etc, that best approximates the behavior of a device under specific operating conditions. Once the model (ac equivalent circuit) is determined, the schematic symbol for the device can be replaced by the equivalent circuit and the basic methods of circuit analysis applied to determine the desired quantities of the network. Hybrid equivalent network employed initially. Drawback It is defined for a set of operating conditions that might not match the actual operating conditions. re model: desirable, but does not include feedback term Hybrid model: model of choice. 35

AC equivalent of a network AC equivalent of a network is obtained by: Setting all dc sources to zero and replacing them by a short circuit equivalent Replacing all capacitors by short circuit equivalent Removing all elements bypassed by the short circuit equivalents Redrawing the network in a more convenient and logical form.

re model In re model, the transistor action has been replaced by a single diode between emitter and base terminals and a controlled current source between base and collector terminals. This is rather a simple equivalent circuit for a device

36

The Hybrid equivalent model For the hybrid equivalent model, the parameters are defined at an operating point. The quantities hie, hre,hfe, and hoe are called hybrid parameters and are the components of a small signal equivalent circuit. The description of the hybrid equivalent model will begin with the general two port system.

The set of equations in which the four variables can be related are: Vi = h11Ii + h12Vo Io = h21Ii + h22Vo The four variables h11, h12, h21 and h22 are called hybrid parameters ( the mixture of variables in each equation results in a hybrid set of units of measurement for the h parameters. Set Vo = 0, solving for h11, h11 = Vi / Ii Ohms This is the ratio of input voltage to the input current with the output terminals shorted. It is called Short circuit input impedance parameter. If Ii is set equal to zero by opening the input leads, we get expression for h12: h12 = Vi / Vo , This is called open circuit reverse voltage ratio. Again by setting Vo to zero by shorting the output terminals, we get h21 = Io / Ii known as short circuit forward transfer current ratio. Again by setting I1 = 0 by opening the input leads, h22 = Io / Vo . This is known as open circuit output admittance. This is represented as resistor ( 1/h22) h11 = hi = input resistance h12 = hr = reverse transfer voltage ratio h21 = hf = forward transfer current ratio h22 = ho = Output conductance

37

Hybrid Input equivalent circuit

Hybrid output equivalent circuit

Complete hybrid equivalent circuit

38

Common Emitter Configuration - hybrid equivalent circuit

Essentially, the transistor model is a three terminal two port system. The h parameters, however, will change with each configuration. To distinguish which parameter has been used or which is available, a second subscript has been added to the h parameter notation. For the common base configuration, the lowercase letter b is added, and for common emitter and common collector configurations, the letters e and c are used respectively.

Common Base configuration - hybrid equivalent circuit

Configuration Common emitter Common base Common Collector

Ii Ib Ie Ib

Io Ic Ic Ie

Vi Vbe Veb Vbe

Vo Vce Vcb Vec

39

Normally hr is a relatively small quantity, its removal is approximated by hr 0 and hrVo = 0, resulting in a short circuit equivalent. The resistance determined by 1/ho is often large enough to be ignored in comparison to a parallel load, permitting its replacement by an open circuit equivalent.

h-Parameter Model v/s. re Model

hie = re
40

hfe = ac
Common Base: re v/s. h-Parameter Model

Common-Base configurations - h-Parameters

hib= re hfb= - = -1
Problem Given IE = 3.2mA, hfe = 150, hoe = 25S and hob = 0.5 S . Determine The common emitter hybrid equivalent The common base re model

Solution: We know that, hie = re and re = 26mV/IE = 26mV/3.2mA = 8.125 re = (150)(8.125) = 1218.75k ro = 1 /hoe = 1/25S = 40k

41

re = 8.125 ro = 1/ hob = 1/0.5S = 2M 1 Small signal ac analysis includes determining the expressions for the following parameters in terms of Zi, Zo and AV in terms of re ro and RB, RC Also, finding the phase relation between input and output The values of , ro are found in datasheet The value of re must be determined in dc condition as re = 26mV / IE

Common Emitter - Fixed bias configuration

Removing DC effects of VCC and Capacitors

42

re model

Small signal analysis fixed bias From the above re model, Zi = [RB [RB re] ohms

If RB > 10 re, then,

re] re

Then, Zi re Zo is the output impedance when Vi =0. When Vi =0, ib =0, resulting in open circuit equivalence for the current source.

Zo = [RC ro ] ohms AV Vo = - Ib( RC || ro) From the re model, Ib = Vi / re thus, Vo = - (Vi / re) ( RC || ro) AV = Vo / Vi = - ( RC || ro) / re

43

If ro >10RC, AV = - ( RC / re) The negative sign in the gain expression indicates that there exists 180o phase shift between the input and output.

Common Emitter - Voltage-Divider Configuration

The re model is very similar to the fixed bias circuit except for RB is R1 case of voltage divider bias. Expression for AV remains the same. Zi = R1 R2 re Zo = RC From the re model, Ib = Vi / re thus, Vo = - (Vi / re) ( RC || ro) AV = Vo / Vi = - ( RC || ro) / re

R2 in the

44

o If ro >10RC, AV = - ( RC / re) Common Emitter - Unbypassed Emitter-Bias Configuration

Applying KVL to the input side: Vi = Ib re + IeRE Vi = Ib re +( +1) IbRE Input impedance looking into the network to the right of RB is Zb = Vi / Ib = re+ ( +1)RE Since >>1, ( +1) =

45

Thus,

Zb = Vi / Ib = (re+RE)

Since RE is often much greater than re, Zb = RE, Zi = RB||Zb

Zo is determined by setting Vi to zero, Ib = 0 and Ib can be replaced by open circuit equivalent. The result is, Zo = RC AV : We know that, Vo = - IoRC = - IbRC = - (Vi/Zb)RC AV = Vo / Vi = - (RC/Zb)

Substituting,

Zb = (re + RE) AV = Vo / Vi = - [RC /(re + RE)]

RE >>re,

AV = Vo / Vi = - [RC /RE]

Phase relation: The negative sign in the gain equation reveals a 180o phase shift between input and output.

Emitter follower

re model
46

Zi = RB || Zb Zb = re+ ( +1)RE Zb = (re+ RE) Since RE is often much greater than re, Zb = RE To find Zo, it is required to find output equivalent circuit of the emitter follower at its input terminal. This can be done by writing the equation for the current Ib. Ib = Vi / Zb Ie = ( +1)Ib = ( +1) (Vi / Zb)

We know that, Zb = re+ ( +1)RE substituting this in the equation for Ie we get, Ie = ( +1) (Vi / Zb) = ( +1) (Vi / re+ ( +1)RE ) Ie = Vi / [re/ ( +1)] + RE

Since ( +1) = , Ie = Vi / [re+ RE] Using the equation Ie = Vi / [re+ RE] , we can write the output equivalent circuit as,

47

 As per the equivalent circuit, Zo = RE||re Since RE is typically much greater than re, Zo re AV Voltage gain: Using voltage divider rule for the equivalent circuit, Vo = Vi RE / (RE+ re) AV = Vo / Vi = [RE / (RE+ re)] Since (RE+ re) RE, AV [RE / (RE] 1 Phase relationship

As seen in the gain equation, output and input are in phase.

Common base configuration

48

re model

Small signal analysis Input Impedance: Output Impedance: Zi = RE||re Zo = RC

To find, Output voltage, Vo = - IoRC Vo = - (-IC)RC = IeRC

o Ie = Vi / re, substituting this in the above equation, Vo = (Vi / re) RC Vo = (Vi / re) RC Voltage Gain: AV: AV = Vo / Vi = (RC/ re) 1; Current gain Ai = Io / Ii Io = - Ie = - Ii Io / Ii = - -1 Phase relation: Output and input are in phase. AV = (RC/ re)

h-Parameter Model vs. re Model

49

CB re vs. h-Parameter Model

Common-Base h-Parameters

h ib = re h fb = 1
Small signal ac analysis includes determining the expressions for the following parameters in terms of Zi, Zo and AV in terms of re ro and RB, RC Also, finding the phase relation between input and output The values of , ro are found in datasheet The value of re must be determined in dc condition as re = 26mV / IE

Common Emitter Fixed bias configuration

50

Removing DC effects of VCC and Capacitors

re model

51

Small signal analysis fixed bias Input impedance Zi: From the above re model, is, Zi = [RB If RB > 10 re, then, [RB Then, re] re re] ohms

Zi re

Ouput impedance Zoi: Zo is the output impedance when Vi = 0. When Vi = 0, ib = 0, resulting in open circuit equivalence for the current source.

Zo = [RC

ro ] ohms

52

Voltage Gain Av: Vo = - Ib( RC || ro) From the re model, thus, Ib = Vi / re Vo = - (Vi / re) ( RC || ro) AV = Vo / Vi = - ( RC || ro) / re If ro >10RC, Phase Shift: The negative sign in the gain expression indicates that there exists 180o phase shift between the input and output. AV = - ( RC / re)

Common Emitter - Voltage-Divider Configuration

Equivalent Circuit: 53

The re model is very similar to the fixed bias circuit except for RB is R1 of voltage divider bias. Expression for AV remains the same. Zi = R1 Zo = RC
:

R 2 in the case

R2

re

Voltage Gain, AV: From the re model, Ib = Vi / re Vo = - Io ( RC || ro), Io = Ib thus, If ro >10RC, Problem: Given: = 210, ro = 50k. Determine: re, Zi, Zo, AV. For the network given: Vo = - (Vi / re) ( RC || ro) AV = Vo / Vi = - ( RC || ro) / re AV = - ( RC / re)

54

To perform DC analysis, we need to find out whether to choose exact analysis or approximate analysis. This is done by checking whether RE > 10R2, if so, approximate analysis can be chosen. Here, RE = (210)(0.68k) = 142.8k. 10R2 = (10)(10k) = 100k. Thus, RE > 10R2. VB = VccR2 / (R1+R2) = (16)(10k) / (90k+10k) = 1.6V VE = VB 0.7 = 1.6 0.7 = 0.9V IE = VE / RE = 1.324mA re = 26mV / 1.324mA = 19.64 Therefore using approximate analysis,

55

Effect of ro can be neglected if ro 10( RC). In the given circuit, 10RC is 22k, ro is 50K. Thus effect of ro can be neglected. Zi = ( R1||R2||RE) = [90k||10k||(210)(0.68k)] = 8.47k Zo = RC = 2.2 k AV = - RC / RE = - 3.24 If the same circuit is with emitter resistor bypassed, Then value of re remains same. Zi = ( R1||R2||re) = 2.83 k Zo = RC = 2.2 k AV = - RC / re = - 112.02

Common Emitter Un bypassed Emitter - Fixed Bias Configuration

Equivalent Circuit: 56

Applying KVL to the input side: Vi = Ibre + IeRE Vi = Ibre +( +1) IbRE Input impedance looking into the network to the right of RB is Zb = Vi / Ib = re+ ( +1)RE Since >>1, Thus, ( +1) = Zb = Vi / Ib = (re+RE) Zb = RE, Zi = RB||Zb Zo is determined by setting Vi to zero, Ib = 0 and Ib can be replaced by open circuit equivalent. The result is, We know that, Zo = RC Vo = - IoRC = - IbRC = - (Vi/Zb)RC AV = Vo / Vi = - (RC/Zb) Substituting RE >>re, Zb = (re + RE) AV = Vo / Vi = - [RC /(re + RE)] AV = Vo / Vi = - [RC /RE]

Since RE is often much greater than re,

57

Phase relation: The negative sign in the gain equation reveals a 180o phase shift between input and output.

Problem:

58

Given: = 120, ro = 40k. Determine: re, Zi, Zo, AV. To find re, it is required to perform DC analysis and find IE as re = 26mV / IE To find IE, it is required to find IB. We know that, IB = (VCC VBE) / [RB + (+1)RE] IB = (20 0.7) / [470k + (120+1)0.56k] = 35.89A IE = (+1)IB = 4.34mA re = 26mV / IE = 5.99 Effect of ro can be neglected, if ro 10( RC + RE)

59

10( RC + RE) = 10( 2.2 k + 0.56k) = 27.6 k and given that ro is 40 k, thus effect of ro can be ignored. Z i = RB|| [ ( re + RE)] = 470k || [120 ( 5.99 + 560 )] = 59.34 Zo = RC = 2.2 k AV = - RC / [ ( re + RE)] = - 3.89 Analyzing the above circuit with Emitter resistor bypassed i.e., Common Emitter IB = (VCC VBE) / [RB + (+1)RE] IB = (20 0.7) / [470k + (120+1)0.56k] = 35.89A IE = (+1)IB = 4.34mA re = 26mV / IE = 5.99 Zi = RB|| [re] = 717.70 Zo = RC = 2.2 k AV = - RC / re = - 367.28 ( a significant increase) Emitter follower

re model

60

Zi = RB || Zb Zb = re+ ( +1)RE Zb = (re+ RE) Since RE is often much greater than re, input terminal. This can be done by writing the equation for the current Ib. Ib = Vi / Zb Ie = ( +1)Ib = ( +1) (Vi / Zb) We know that, Zb = re+ ( +1)RE substituting this in the equation for Ie we get, Ie = ( +1) (Vi / Zb) = ( +1) (Vi / re+ ( +1)RE ) dividing by ( +1), we get, Ie = Vi / [re/ ( +1)] + RE Since ( +1) = , Ie = Vi / [re+ RE] Using the equation Ie = Vi / [re+ RE], we can write the output equivalent circuit as, Zb = RE To find Zo, it is required to find output equivalent circuit of the emitter follower at its

61

As per the equivalent circuit, Zo = RE||re Since RE is typically much greater than re, Zo re AV Voltage gain: Using voltage divider rule for the equivalent circuit, Vo = Vi RE / (RE+ re) AV = Vo / Vi = [RE / (RE+ re)] Since (RE+ re) RE, AV [RE / (RE] 1 Phase relationship As seen in the gain equation, output and input are in phase.

62

Common base configuration

re model

Small signal analysis Zi = RE||re Zo = RC To find Vo = - IoRC Vo = - (-IC)RC = IeRC Substituting this in the above equation, Ie = Vi / re, Vo = (Vi / re) RC Vo = (Vi / re) RC AV = Vo / Vi = (RC/ re)

63

 1; Current gain Ai :

AV = (RC/ re) Ai = Io / Ii Io = - Ie = - Ii Io / Ii = - -1

Phase relation: Output and input are in phase.

Common Emitter - Collector Feedback Configuration

64

re Model

Input Impedance: Zi Zi = Vi / Ii, Ii = Ib I, thus it is required to find expression for I in terms of known resistors. I = (Vo Vi)/ RF Vo = - IoRC Io = Ib + I Normally, thus, I << Ib Io = Ib , Vo = - IoRC Vo = - Ib RC, Replacing Thus, Vo = - (Vi RC) / re = - (Vi RC) / re Substituting (2) in (1): I = (Vo Vi)/ RF = (Vo / RF) - (Vi/ RF) = - [(Vi RC) / RF re] - (Vi/ RF) 65 (2) Ib by Vi / re (1)

I = - Vi/RF[ (RC / re )+1] We know that, and, Thus, Vi = Ibre, Ib = Ii + I I = - Vi/RF[ (RC / re ) +1] Vi = ( Ii + I ) re = Ii re + I re = Ii re - (Vi re)( 1/RF)[ (RC / re )+1] Taking Vi terms on left side: Vi + (Vi re)( 1/RF)[ (RC / re )+1] = Ii re Vi[1 + (re)( 1/RF)[ (RC / re ) +1] = Ii re Vi / Ii = re / [1 + (re)( 1/RF)[ (RC / re ) +1] But, [ (RC / re )+1] RC / re (because RC >> re) Thus, Zi = Vi / Ii = re / [1 + (re)( 1/RF)[ (RC / re )] = re / [1 + ()(RC/RF)] Thus, Zi = re / [(1/) + (RC/RF)]

To find Output Impedance Zo:

Zo = RC || RF ( Note that ib = 0, thus no effect of re on Zo)

66

Voltage Gain AV: Vo = - IoRC = - IbRC ( neglecting the value of I ) = - (Vi/ re)RC AV = Vo / Vi = - (RC/re) Phase relation: - sign in AV indicates phase shift of 180 between input and output. Collector DC feedback configuration

re model

Zi = RF1 ||re Zo = RC||RF2||ro, for ro10RC, Zo = RC||RF2

67

To find Voltage Gain AV : Vo = - Ib(RF2||RC||ro), Ib = Vi / re Vo = - (Vi / re)(RF2||RC||ro) Vo / Vi = - (RF2||RC||ro) / re, for ro10RC, AV = Vo / Vi = - (RF2||RC) / re Determining the current gain For each transistor configuration, the current gain can be determined directly from the voltage gain, the defined load, and the input impedance. We know that, current gain (Ai) = Io / Ii Io = (Vo / RL) and Ii = Vi / Zi Thus, Ai = - (Vo /RL) / (Vi / Zi) = - (Vo Zi / Vi RL) Ai = - AV Zi / RL Example: For a voltage divider network, we have found that, Zi = re AV = - RC / re and RL = RC Thus, Ai = - AV Zi / RL = - (- RC / re )(re) / RC Ai = For a Common Base amplifier, Zi = re, AV = RC / re, RL = RC Ai = - AV Zi / RL = - (RC / re )(re) / RC =-1 Effect of RL and RS: Voltage gain of an amplifier without considering load resistance (RL) and source resistance (RS) is AVNL. Voltage gain considering load resistance ( RL) is AV < AVNL Voltage gain considering RL and RS is AVS, where AVS<AVNL< AV For a particular design, the larger the level of RL, the greater is the level of ac gain.

68

Also, for a particular amplifier, the smaller the internal resistance of the signal source, the greater is the overall gain. Fixed bias with RS and RL:

AV = - (RC||RL) / re Z i = RB|| re Zo = RC||ro To find the gain AVS, ( Zi and RS are in series and applying voltage divider rule) Vi = VSZi / ( Zi+RS) Vi / VS = Zi / ( Zi+RS) AVS = Vo / VS = (Vo/Vi) (Vi/VS) AVS = AV [Zi / ( Zi+RS)] Voltage divider with RS and RL

69

Voltage gain: Input Impedance: Output Impedance:

AV = - [RC||RL] / re Zi = R1||R2|| re Zo = RC||RL||ro

Emitter follower with RS and RL

re model:

Voltage Gain: Input Impedance: Output Impedance

AV = (RE||RL) / [RE||RL+re] Zi = RB || Zb Zb = (RE||RL) Zo = re

Input Impedance seen at Base:

Two port systems approach This is an alternative approach to the analysis of an amplifier. This is important where the designer works with packaged with packaged products rather than individual elements.

70

An amplifier may be housed in a package along with the values of gain, input and output impedances. But those values are no load values and by using these values, it is required to find out the gain and various impedances under loaded conditions. This analysis assumes the output port of the amplifier to be seen as a voltage source. The value of this output voltage is obtained by Thevinising the output port of the amplifier. Eth = AVNLVi Model of two port system

Applying the load to the two port system

Applying voltage divider in the above system: Vo = AVNLViRL / [ RL+Ro] Including the effects of source resistance RS

71

Applying voltage divider at the input side, we get: Vi = VSRi /[RS+Ri] Vo = AVNLVi Vi = VSRi /[RS+Ri] Vo = AVNL VSRi /[RS+Ri] Vo/ VS = AVS = AVNLRi /[RS+Ri] Two port system with RS and RL

We know that, at the input side Vi = VSRi /[RS+Ri] Vi / VS = Ri /[RS+Ri] At the output side, Vo = AVNLViRL / [ RL+Ro] Vo / Vi = AVNLRL / [ RL+Ro] Thus, considering both RS and RL: AV = Vo / Vs = [Vo / Vi] [Vi / Vs] AV = (AVNLRL / [ RL+Ro]) (Ri / [RS+Ri]) Example: Given an amplifier with the following details: RS = 0.2 k, AVNL = - 480, Zi = 4 k, Zo = 2 k Determine: AV with RL =1.2k AV and Ai with RL= 5.6 k, AVS with RL = 1.2

72

Solution: AV = AVNLRL / (RL + Ro) = (- 480)1.2k / (1.2k+2k) = - 180 With RL = 5.6k, AV = - 353.76 This shows that, larger the value of load resistor, the better is the gain. AVS = [Ri /(Ri+RS)] [ RL / (RL+Ro)] AVNL = - 171.36 Ai = - AVZi/RL, here AV is the voltage gain when RL = 5.6k. Ai = - AVZi/RL = - (-353.76)(4k/5.6k) = 252.6 Hybrid model

This is more accurate model for high frequency effects. The capacitors that appear are stray parasitic capacitors between the various junctions of the device. These capacitances come into picture only at high frequencies. Cbc or Cu is usually few pico farads to few tens of pico farads. rbb includes the base contact, base bulk and base spreading resistances. rbe ( r), rbc, rce are the resistances between the indicated terminals. rbe ( r) is simply re introduced for the CE re model. rbc is a large resistance that provides feedback between the output and the input. r = re gm = 1/re ro = 1/hoe hre = r / (r + rbc)

73

CHAPTER.6 :TRANSISTOR FREQUENCY RESPONSE To understand Decibels, log scale, general frequency considerations of an amplifier. low frequency analysis - Bode plot low frequency response BJT amplifier Miller effect capacitance high frequency response BJT amplifier

Introduction It is required to investigate the frequency effects introduced by the larger capacitive elements of the network at low frequencies and the smaller capacitive elements of the active device at high frequencies. Since the analysis will extend through a wide frequency range, the logarithmic scale will be used. Logarithms To say that logaM = x means exactly the same thing as saying ax = M .

For example: What is log28? "To what power should 2 be raised in order to get 8?" Since 8 is 23 the answer is "3." So log28 = 3 Basic Rules Logarithmic Rule 1:

Logarithmic Rule 2:

Logarithmic Rule 3:

74

Natural Logarithm (or base e) There is another logarithm that is also useful (and in fact more common in natural processes). Many natural phenomenon are seen to exhibit changes that are either exponentially decaying (radioactive decay for instance) or exponentially increasing (population growth for example). These exponentially changing functions are written as ea, where a represents the rate of the exponential change. In such cases where exponential changes are involved, we usually use another kind of logarithm called natural logarithm. The natural log can be thought of as Logarithm Base-e. This logarithm is labeled with ln (for "natural log"), where, e = 2.178.

Semi Log graph

Decibels The term decibel has its origin in the fact that the power and audio levels are related on a logarithmic basis. The term bel is derived from the surname of Alexander Graham Bell. Bel is defined by the following equation relating two power levels, P1 and P2: G = [log10 P2 / P1] bel It was found that, the Bel was too large a unit of measurement for the practical purposes, so the decibel (dB) is defined such that 10 decibels = 1 bel.

75

Therefore,

GdB = [10 log10 P2 / P1 ] dB

The decimal rating is a measure of the difference in magnitude between two power levels. For a specified output power P2, there must be a reference power level P1. The reference level is generally accepted to be 1mW. GdBm = [10 log10 P2 / 1mW ] dBm GdB = [10 log10 P2 / P1 ] dB = [10 log10 (V22 / Ri ) / (V12 / Ri )] dB = 10 log10 (V2 / V1)2 GdB = [20 log10 V2 / V1 ] dB One of the advantages of the logarithmic relationship is the manner in which it can be applied to cascaded stages wherein the overall voltage gain of a cascaded system is the sum of individual gains in dB. AV = (Av1)(Av2)(Av3). AVdB = (Av1dB)+(Av2dB)+(Av3dB). Problem1: Find the magnitude gain corresponding to a voltage gain of 100dB. GdB = [20 log10 V2 / V1 ] dB = 100dB = 20 log10 V2 / V1 ; V2 / V1 = 105 = 100,000 Problem 2: The input power to a device is 10,000W at a voltage of 1000V. The output power is 500W and the output impedance is 20. Find the power gain in decibels. Find the voltage gain in decibels. GdB = 10 log10 (Po/Pi) = 10 log10 (500/10k) = -13.01dB GV = 20 log10 (Vo/Vi) = 20 log10 (PR/1000) = 20 log10 [(500)(20)/1000] = - 20dB ( Note: P = V2/R; V = PR) 76

Problem 3 : An amplifier rated at 40 W output is connected to a 10 speaker. a. Calculate the input power required for full power output if the power gain is 25dB. b. Calculate the input voltage for rated output if the amplifier voltage gain is 40dB. a. 25 = 10 log10 40/Pi Pi = 40 / antilog(2.5) = 126.5mW b. GV = 20log10Vo/Vi ; 40 = 20log10Vo/Vi Vo /Vi = antilog 2 = 100 Also, Thus, Vo = PR = (40)(10) = 20V Vi = Vo / 100 = 20/100 = 200mV

General Frequency considerations At low frequencies the coupling and bypass capacitors can no longer be replaced by the short circuit approximation because of the increase in reactance of these elements. The frequency dependent parameters of the small signal equivalent circuits and the stray capacitive elements associated with the active device and the network will limit the high frequency response of the system. An increase in the number of stages of a cascaded system will also limit both the high and low frequency response. The horizontal scale of frequency response curve is a logarithmic scale to permit a plot extending from the low to the high frequency

For the RC coupled amplifier, the drop at low frequencies is due to the increasing reactance of CC and CE, whereas its upper frequency limit is determined by either the parasitic capacitive elements of the network or the frequency dependence of the gain of the active device. In the frequency response, there is a band of frequencies in which the magnitude of the gain is either equal or relatively close to the midband value. 77

To fix the frequency boundaries of relatively high gain, 0.707AVmid is chosen to be the gain at the cutoff levels. The corresponding frequencies f1 and f2 are generally called corner, cutoff, band, break, or half power frequencies. The multiplier 0.707 is chosen because at this level the output power is half the midband power output, that is, at mid frequencies, PO mid = | Vo2| / Ro = | AVmidVi|2 / RO And at the half power frequencies, POHPF = | 0.707 AVmidVi|2 / Ro = 0.5| AVmid Vi|2 / Ro

And,

POHPF = 0.5 POmid

The bandwidth of each system is determined by f2 f1 A decibel plot can be obtained by applying the equation, (AV / AVmid )dB = 20 log10 (AV / AVmid)

Most amplifiers introduce a 180 phase shift between input and output signals. At low frequencies, there is a phase shift such that Vo lags Vi by an increased angle. At high frequencies, the phase shift drops below 180. Low frequency analysis Bode plot In the low frequency region of the single stage BJT amplifier, it is the RC combinations formed by the network capacitors CC and CE, the network resistive parameters that determine the cutoff frequencies.

78

Frequency analysis of an RC network

Analysis of the above circuit indicates that, XC = 1/2fC 0

Thus, Vo = Vi at high frequencies. At f = 0 Hz, XC = , Vo = 0V. Between the two extremes, the ratio, AV = Vo / Vi will vary. As frequency increases, the capacitive reactance decreases and more of the input voltage appears across the output terminals. The output and input voltages are related by the voltage divider rule: Vo = RVi / ( R jXC) the magnitude of Vo = RVi / R2 + XC2 Vo =RVi / R2 = (1/2) Vi AV = Vo / Vi = (1/2) = 0.707

For the special case where XC = R,

The frequency at which this occurs is determined from, XC = 1/2f1C = R where, f1 = 1/ 2RC AV = Vo / Vi = R / (R jXC) = 1/ ( 1 j(1/CR) = 1 / [ 1 j(f1 / f)]

Gain equation is written as,

In the magnitude and phase form, AV = Vo / Vi = [1 / 1 + (f1/f)2 ] tan-1 (f1 / f)

79

In the logarithmic form, the gain in dB is AV = Vo / Vi = [1 / 1 + (f1/f)2 ] = 20 log 10 [1 / 1 + (f1/f)2 ] = - 20 log 10 [ 1 + (f1/f)2] = - 10 log10 [1 + (f1/f)2]

For frequencies where f << f1 or (f1/ f)2 the equation can be approximated by AV (dB) = - 10 log10 [ (f1 / f)2] = - 20 log10 [ (f1 / f)] at f << f1

At f = f1 ; f1 / f = 1 and 20 log101 = 0 dB

At f = f1; f1 / f = 2 20 log102 = - 6 dB

At f = f1; f1 / f = 4 20 log102 = - 12 dB

At f = 1/10 f1; f1 / f = 10 20 log1010 = - 20dB

The above points can be plotted which forms the Bode plot. Note that, these results in a straight line when plotted in a logarithmic scale. Although the above calculation shows at f = f1, gain is 3dB, we know that f1 is that frequency at which the gain falls by 3dB. Taking this point, the plot differs from the straight line and gradually approaches to 0dB by f = 10f1.

Observations from the above calculations: When there is an octave change in frequency from f1 / 2 to f1, there exists corresponding change in gain by 6dB. When there is an decade change in frequency from f1 / 10 to f1, there exists corresponding change in gain by 20 dB.

80

Low frequency response BJT amplifier A voltage divider BJT bias configuration with load is considered for this analysis. For such a network of voltage divider bias, the capacitors CS, CC and CE will determine the low frequency response.

Let us consider the effect of each capacitor independently. CS:

fLs =

1 2 (Rs + Ri)Cs

Ri = R1 || R2 || re
At mid or high frequencies, the reactance of the capacitor will be sufficiently small to permit a short circuit approximations for the element. The voltage Vi will then be related to Vs by Vi |mid = VsRi / (Ri+Rs)

81

At f = FLS, Vi = 70.7% of its mid band value. The voltage Vi applied to the input of the active device can be calculated using the voltage divider rule: Vi = RiVs / ( Ri+ Rs jXCs)

Effect of CC:

Since the coupling capacitor is normally connected between the output of the active device and applied load, the RC configuration that determines the low cutoff frequency due to CC appears as in the figure given below.

1 fLC = 2 ( Ro + RL)Cc
Ro = Rc|| ro Effect of CE:

fLE =

1 2 ReCE

Re = RE || (

R s

+ re)

R s = Rs || R1 || R2

82

The effect of CE on the gain is best described in a quantitative manner by recalling that the gain for the amplifier without bypassing the emitter resistor is given by: AV = - RC / ( re + RE) Maximum gain is obviously available where RE is 0. At low frequencies, with the bypass capacitor CE in its open circuit equivalent state, all of RE appears in the gain equation above, resulting in minimum gain. As the frequency increases, the reactance of the capacitor CE will decrease, reducing the parallel impedance of RE and CE until the resistor RE is effectively shorted out by CE. The result is a maximum or midband gain determined by AV = - RC / re. The input and output coupling capacitors, emitter bypass capacitor will affect only the low frequency response. At the mid band frequency level, the short circuit equivalents for these capacitors can be inserted. Although each will affect the gain in a similar frequency range, the highest low frequency cutoff determined by each of the three capacitors will have the greatest impact. Problem: Determine the lower cutoff freq. for the network shown using the following parameters: Cs = 10 F, CE = 20 F, Cc = 1 F Rs = 1k , R1= 40k , R2 = 10k , RE = 2k , RC = 4k , RL = 2.2k , = 100, ro = , Vcc = 20V

83

Solution: a. To determine re for the dc conditions, let us check whether RE > 10R2 Here, RE = 200k, 10R2 = 100k. The condition is satisfied. Thus approximate analysis can be carried out to find IE and thus re. VB = R2VCC / ( R1+R2) = 4V VE = VB 0.7 = 3.3V IE = 3.3V / 2k = 1.65mA re = 26mV / 1.65mA = 15.76

Mid band gain:

AV = Vo / Vi = -RC||RL / re = - 90 Input impedance Zi = R1 || R2|| re = 1.32K Cut off frequency due to input coupling capacitor ( fLs) fLs = 1/ [2(Rs +Ri)CC1 = 6.86Hz. fLc = 1 / [2(RC + RL) CC = 1 / [ 6.28 (4k + 2.2k)1uF] = 25.68 Hz

Effect of CE:
RS = RS||R1||R2 = 0.889 Re = RE || (RS/ + re) = 24.35 fLe = 1/2 ReCE = 327 Hz

fLe = 327 Hz fLC = 25.68Hz fLs = 6.86Hz

In this case, fLe is the lower cutoff frequency. In the high frequency region, the capacitive elements of importance are the interelectrode ( between terminals) capacitances internal to the active device and the wiring capacitance between leads of the network. The large capacitors of the network that controlled the low frequency response are all replaced by their short circuit equivalent due to their very low reactance level. For inverting amplifiers, the input and output capacitance is increased by a capacitance level sensitive to the inter-electrode capacitance between the input and output terminals of the device and the gain of the amplifier. 84

Miller Effect Capacitance

Any P-N junction can develop capacitance. This was mentioned in the chapter on diodes. In a BJT amplifier this capacitance becomes noticeable between: the BaseCollector junction at high frequencies in CE BJT amplifier configurations. It is called the Miller Capacitance. It effects the input and output circuits.

Ii = I1 + I2 Using Ohms law yields I1 = Vi / Zi, I1 = Vi / R1 and I2 = (Vi Vo) / Xcf = ( Vi AvVi) / Xcf I2 = Vi(1 Av) / Xcf Substituting for Ii, I1 and I2 in eqn(1), Vi / Zi = Vi / Ri + [(1 Av)Vi] /Xcf 1/ Zi = 1/Ri + [(1 Av)] /Xcf 1/ Zi = 1/Ri + 1/ [Xcf / (1 Av)] 1/ Zi = 1/Ri + 1/ XCM Where, XCM = [Xcf / (1 Av)] = 1/[ (1 Av) Cf] CMi = (1 Av) Cf CMi is the Miller effect capacitance. Eqn (1)

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For any inverting amplifier, the input capacitance will be increased by a Miller effect capacitance sensitive to the gain of the amplifier and the inter-electrode ( parasitic) capacitance between the input and output terminals of the active device.

Miller Output Capacitance (CMo)

Applying KCL at the output node results in: Io = I1+I2 I1 = Vo/Ro and I2 = (Vo Vi) / XCf

CMo Cf

The resistance Ro is usually sufficiently large to permit ignoring the first term of the equation, thus Io (Vo Vi) / XCf Substituting Vi = Vo / AV, Io = (Vo Vo/Av) / XCf = Vo ( 1 1/AV) / XCf Io / Vo = (1 1/AV) / XCf Vo / Io = XCf / (1 1/AV) = 1 / Cf (1 1/AV) = 1/ CMo CMo = ( 1 1/AV)Cf CMo Cf [ |AV| >>1] 86

If the gain (Av) is considerably greater than 1:

CMo Cf
High frequency response BJT Amplifier
At the high frequency end, there are two factors that define the 3dB cutoff point: The network capacitance ( parasitic and introduced) and the frequency dependence of hfe()

Network parameters
In the high frequency region, the RC network of the amplifier has the configuration shown below.

Vi

Vo

At increasing frequencies, the reactance XC will decrease in magnitude, resulting in a short effect across the output and a decreased gain. Vo = Vi(-jXC) / R -jXC Vo / Vi = 1/[ 1+j(R/XC)] ; XC = 1/2fC AV = 1/[ 1+j(2fRC)]; AV = 1/[ 1+jf/f2]

o This results in a magnitude plot that drops off at 6dB / octave with increasing frequency.

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Network with the capacitors that affect the high frequency response

Capacitances that will affect the high-frequency response: Cbe, Cbc, Cce internal capacitances Cwi, Cwo wiring capacitances CS, CC coupling capacitors CE bypass capacitor

The capacitors CS, CC, and CE are absent in the high frequency equivalent of the BJT amplifier.The capacitance Ci includes the input wiring capacitance, the transition capacitance Cbe, and the Miller capacitance CMi.The capacitance Co includes the output wiring capacitance Cwo, the parasitic capacitance Cce, and the output Miller capacitance CMo.In general, the capacitance Cbe is the largest of the parasitic capacitances, with Cce the smallest. As per the equivalent circuit, fH = 1 / 2RthiCi Rthi = Rs|| R1||R2||Ri Ci = Cwi+Cbe+CMi = CWi + Cbe+(1- AV) Cbe

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At very high frequencies, the effect of Ci is to reduce the total impedance of the parallel combination of R1, R2, Ri, and Ci.The result is a reduced level of voltage across Ci, a reduction in Ib and the gain of the system. For the output network, fHo = 1/(2RThoCo) RTho = RC||RL||ro Co = Cwo+Cce+CMo At very high frequencies, the capacitive reactance of Co will decrease and consequently reduce the total impedance of the output parallel branches. The net result is that Vo will also decline toward zero as the reactance Xc becomes smaller.The frequencies fHi and fHo will each define a -6dB/octave asymtote. If the parasitic capacitors were the only elements to determine the high cutoff frequency, the lowest frequency would be the determining factor.However, the decrease in hfe(or ) with frequency must also be considered as to whether its break frequency is lower than fHi or fHo.

hfe (or ) variation

The variation of hfe( or ) with frequency will approach the following relationship hfe = hfe mid / [1+(f/f)] f is that frequency at which hfe of the transistor falls by 3dB with respect to its mid band value. The quantity f is determined by a set of parameters employed in the hybrid model. In the hybrid model, rb includes the base contact resistance base bulk resistance base spreading resistance

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Hybrid model

The resistance ru(rbc) is a result of the fact that the base current is somewhat sensitive to the collector to base voltage. Since the base to emitter voltage is linearly related to the base current through Ohms law and the output voltage is equal to the difference between the base the base to emitter voltage and collector to base voltage, we can say that the base current is sensitive to the changes in output voltage. Thus, f = 1/[2r(C+Cu)] r = re = hfe mid re

Therefore, f = 1/[2 hfemid re(C+Cu)] OR f = 1/[2 mid re(C+Cu)]

The above equation shows that, f is a function of the bias configuration. As the frequency of operation increases, hfe will drop off from its mid band value with a 6dB / octave slope. Common base configuration displays improved high frequency characteristics over the common emitter configuration. Miller effect capacitance is absent in the Common base configuration due to non inverting characteristics. A quantity called the gain bandwidth product is defined for the transistor by the condition, | hfemid / [1+j(f/f)| = 1 So that, |hfe|dB = 20 log10 | hfemid / [1+j(f/f)| = 20 log101 = 0 dB 90

The frequency at which |hfe|dB = 0 dB is indicated by fT. | hfemid / [1+j(f/f)| = 1 hfemid / 1+ (fT/f)2 hfemid / (fT/f) =1

( by considering fT>>f) Thus, But, fT = hfemid f OR fT = mid f f = 1/[2 mid re(C+Cu)] fT = (mid) 1/[2 mid re(C+Cu)]

fT = 1/[2 re(C+Cu)] Problem:

For the amplifier with voltage divider bias, the following parameters are given: RS = 1k , R1 = 40k, R2 = 10k, Rc = 4k, RL = 10k Cs = 10F, Cc = 1 F, CE= 20 F = 100, ro = , VCC = 10 C = 36pF, Cu = 4pF, Cce=1pF, Cwi=6pF, Cwo=8pF

a. Determine fHi and fHo b. Find f and fT Solution: To find re, DC analysis has to be performed to find IE.
VB = R2VCC / R1+R2 = 2V VE = 2 0.7 = 1.3V IE = 1.3/1.2K = 1.083mA re = 26mV / 1.083mA

re = 24.01,
re = 2.4k Ri = RS||R1||R2||re

Ri = 1.85k
AV = Vo/Vi = - (Rc ||RL) / re

AV = - 119

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RThi = Rs||R1||R2||Ri

RThi = 0.6k To determine fHi and fHo:

fHi = 1/[2RThiCi] ; Ci = Cwi+Cbe+(1 AV)Cbc = 6pF + 36pF + (1 (-119)) 4pF

Ci = 522pF
fHi = 1/2RThiCi

fHi = 508.16kHz
RTho = Rc||RL

RTho = 2.86k
Co = Cwo+Cce+C Mo = 8pF+1pF+(1 (1/-119))4pF

Co = 13.03pF
fHo = 1/2RThoCo

fHo = 8.542MHz
f = 1/[2 mid re(C+Cu)]

f = 1.66MHz
fT = f

fT = 165.72MHz Summary Frequency response of BJT Amplifiers

Logarithm of a number gives the power to which the base must be brought to obtain the same number Since the decibel rating of any equipment is a comparison between levels, a reference level must be selected for each area of application. For Audio system, reference level is 1mW The dB gain of a cascaded system is the sum of dB gains of each stage. It is the capacitive elements of a network that determine the bandwidth of a system. The larger capacitive elements of the design determine the lower cutoff frequencies. Smaller parasitic capacitors determine the high cutoff frequencies. The frequencies at which the gain drops to 70.7% of the mid band value are called cutoff, corner, band, break or half power frequencies.

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The narrower the bandwidth, the smaller is the range of frequencies that will permit a transfer of power to the load that is atleast 50% of the midband level. A change in frequency by a factor of 2, is equivalent to one octave which results in a 6dB change in gain. For a 10:1 change in frequency is equivalent to one decade results in a 20dB change in gain. For any inverting amplifier, the input capacitance will be increased by a Miller effect capacitance determined by the gain of the amplifier and the inter electrode ( parasitic) capacitance between the input and output terminals of the active device. CMi = (1 AV)Cf

Also,

CMo Cf (if AV >>1)

A 3dB drop in will occur at a frequency defined by f, that is sensitive to the DC operating conditions of the transistor. This variation in defines the upper cutoff frequency of the design.

Problems: 1. The total decibel gain of a 3 stage system is 120dB. Determine the dB gain of each stage, if the second stage has twice the decibel gain of the first and the third has 2.7 times decibel gain of the first. Also, determine the voltage gain of the each stage.
Given: We have Given, Therefore, GdBT = 120dB GdBT = GdB1+GdB2+GdB3 GdB2 = 2GdB1 GdB3 = 2.7GdB1 120dB = 5.7GdB1 GdB1 = 21.05, GdB2 = 42.10 GdB3 =56.84 We have GdB = 10 log[Vo / Vi] Vo / Vi = antilog ( GdB/10) G1 = 127.35 G2 = 16.21k G3 = 483.05k 2. If the applied ac power to a system is 5W at 100mV and the output power is 48W, determine

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a. The power gain in decibels b. The output voltage c. The voltage gain in decibels, if the output impedance is 40k. d. The input impedance Given: Pi = 5W.Vi = 100mV, Po = 48w Ro = 40k a. GdB =10 log [48/ 5] = 69.82 b. Po = Vo2 /Ro, Vo = PoRo = 1385.64V c. Voltage gain in dB = 20 log [1385.64/100m] = 82.83 d. Ri = Vi2 / Pi = 2k

General steps to solve a given problem:

Normally, the amplifier circuit with all the values of biasing resistors, value of and values inter electrode capacitances ( Cbe, Cbc and Cce) will be given. It is required to calculate: fLS, fLC and fLE Also, fHi, fHo, f and fT Step1: Perform DC analysis and find the value of IE, and re Find the value of Ri ( Zi) using the value of re Find the value of AVmid

Step 2: Find fLS using the formula 1/2(Ri+RS)CS Step 3: Find fLC using the formula 1/2(RC+RL)CC Step 4: Determine the value of fLE using the formula 1/2ReCE where, Re = RE || [(RS)/ + re] RS = RS||R1||R2

Step 5: Determine fHi using the formula 1/2RThiCi where RThi = R1||R2||RS||re Ci = Cwi + Cbe + (1-AV)Cbc

Step 6: Determine fHo using the formula 1/2RThoCo where RTho = RC||RL||ro Co = Cwo + Cce+ C bc

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Step 7: Determine f using the formula 1/[2 mid re(C+Cu)] Step 8: Determine fT using the formula fT = mid f

Problem: Determine the following for the given network:

1. fLs 2. fLc 3. fLE 4. 5. 6. fHi fHo f and fT

Given: VCC = 20V, RB = 470k, RC = 3k, RE = 0.91k, RS = 0.6k, RL = 4.7k CS = CC = 1F, CE = 6.8 F

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Cwi = 7pF, Cwo=11pF, Cbe = 6pF, Cbe = 20pF and Cce = 10pF

Solution:
IB = (VCC VBE) / [RB + ( +1)RE]

IB = 3.434mA
IE = IB

IE = 3.434mA
re = 26mV / IE

re = 7.56
AV = - (RC||RL) / re

AV = -242.2
Zi = RB|| re

Zi = 754.78
fLS = 1/2(Ri+RS)CS

fLS = 117.47Hz
fLC = 1/2(RC+RL)CC

fLC = 20.66 Hz
fLE = 1/2ReCE ; where, Re = [(RS /)+ re] || RE RS = RB || RS

fLE = 1.752kHz
Ci = Cwi + Cbe + (1 AV) Cbc

Ci = 1.48nF
RThi = RS || RB|| re

RThi = 334.27
fHi = 1 / 2(1.48nF)(334.37)

fHi = 321.70 KHz

Co = CWo + Cce + (1 1/AV) Cbc

Co = 27.02pF
RTho = RC || RL

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RTho = 1.83K
fHo = 1 / 2(27.02p)(1.83k)

fHo = 3.21MHz
f = 1 / 2 (100) (7.56)( 20p + 6p)

f = 8.09MHz
fT = f

fT = 803MHz

Equations - Logarithms
1. a = bx, x = logba 2. GdB = 10 log P2 / P1 3. GdB = 20 log V2 / V1

Equations Low frequency response 1. AV = 1 / [1 j(f1/f)],

where, f1 = 1/2RC

Equations BJT low frequency response

1. fLs = 1 / [2(RS+Ri)CS] , where, Ri = R1||R2||re 2. 3. fLC = 1 /[2(Ro+RL)CC], fLE = 1 / 2ReCE, where, Ro = RC||ro where, Re = RE || ( RS/ +re) and RS = RS||R1||R2

Miller effect Capacitance

CMi = (1 AV)Cf, CMO = ( 1 1/AV)Cf

BJT High frequency response:

1. AV = 1/ [1 + j(f/f2)]

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2. fHi = 1 / 2RThiCi, where, RThi = RS||R1||R2||Ri, Ci = CWi+Cbe+ CMi 3. fHO = 1/ 2RThoCo, where, RTho = RC||RL||ro Co = CWo+Cce+ CMo 4. f = 1/[2 mid re(C+Cu)] 5. fT = f

Chapter.8: Oscillators

Objectives:
To understand The basic operation of an Oscillator the working of low frequency oscillators RC phase shift oscillator Wien bridge Oscillator the working of tuned oscillator Colpitts Oscillator, Hartley Oscillator Crystal Oscillator the working of UJT Oscillator

Basic operation of an Oscillator

An amplifier with positive feedback results in oscillations if the following conditions are satisfied: The loop gain ( product of the gain of the amplifier and the gain of the feedback network) is unity The total phase shift in the loop is 0 If the output signal is sinusoidal, such a circuit is referred to as sinusoidal oscillator.

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When the switch at the amplifier input is open, there are no oscillations. Imagine that a voltage Vi is fed to the circuit and the switch is closed. This results in Vo = AV Vi and Vo = Vf is fed back to the circuit. If we make Vf = Vi, then even if we remove the input voltage to the circuit, the output continues to exist. Vo = AV Vi Vo = Vf AV Vi = Vf If Vf has to be same as Vi, then from the above equation, it is clear that, AV =1. Thus in the above block diagram, by closing the switch and removing the input, we are able to get the oscillations at the output if AV =1, where AV is called the Loop gain. Positive feedback refers to the fact that the fed back signal is in phase with the input signal. This means that the signal experiences 0 phase shift while traveling in the loop. The above condition along with the unity loop gain needs to be satisfied to get the sustained oscillations. These conditions are referred to as Barkhausen criterion. Another way of seeing how the feedback circuit provides operation as an oscillator is obtained by noting the denominator in the basic equation Af = A / (1+A). When A = -1 or magnitude 1 at a phase angle of 180, the denominator becomes 0 and the gain with feedback Af becomes infinite.Thus, an infinitesimal signal ( noise voltage) can provide a measurable output voltage, and the circuit acts as an oscillator even without an input signal.

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Phase shift oscillator

The phase shift oscillator utilizes three RC circuits to provide 180 phase shift that when coupled with the 180 of the op-amp itself provides the necessary feedback to sustain oscillations. The gain must be at least 29 to maintain the oscillations. The frequency of resonance for the this type is similar to any RC circuit oscillator: fr = 1/26RC

FET phase shift oscillator

The amplifier stage is self biased with a capacitor bypassed source resistor Rs and a drain bias resistor RD . The FET device parameters of interest are gm and rd. |A| = gmRL, where RL = (RDrd / RD + rd) At the operating frequency, we can assume that the input impedance of the amplifier is infinite. This is a valid approximation provided, the oscillator operating frequency is low enough so that FET capacitive impedances can be neglected.

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The output impedance of the amplifier stage given by RL should also be small compared to the impedance seen looking into the feedback network so that no attenuation due to loading occurs.

RC Phase shift Oscillator - BJT version

If a transistor is used as the active element of the amplifier stage, the output of the feedback network is loaded appreciably by the relatively low input resistance ( hie) of the transistor. An emitter follower input stage followed by a common emitter amplifier stage could be used.If a single transistor stage is desired, the use of voltage shunt feedback is more suitable. Here, the feedback signal is coupled through the feedback resistor R in series with the amplifier stage input resistance ( Ri). f = (1/2RC)[1/ 6 + 4(RC / R)] hfe > 23 + 29 (R/RC) + 4 (RC / R)

Problem:
It is desired to design a phase shift oscillator using an FET having gm = 5000S, rd = 40 k , and a feedback circuit value of R = 10 k. Select the value of C for oscillator operation at 5 kHz and RD for A > 29 to ensure oscillator action.

Solution:

f = 1/26RC ; C = 1/26Rf = 1.3nF |A| = gm RL Let A = 40; RL = |A| / gm = 8 k

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IC phase shift Oscillator

Wien Bridge

When the bridge is balanced, (R2 / R1) = (R3 / R4) + ( C2 / C1) f = 1/[2 R3C1R4C2]

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Wien bridge Oscillator

R and C are used for frequency adjustment and resistors R1 and R2 form part of the feedback path. If R3 = R4 =R, C1 = C2 = C, the resulting frequency is f = 1/2RC and R2 / R1 = 2

Tuned Oscillators

A variety of circuits can be built using the above diagram, by providing tuning in both the input and output sections of the circuit. Analysis of the above diagram shows that the following types of Oscillators are obtained when the reactance elements are as designated: Oscillator type Colpitts Oscillator Hartley Oscillator Tuned input, Tuned Output X1 C L LC X2 C L LC X3 L C 103

Colpitts Oscillator

The Colpitts oscillator utilizes a tank circuit (LC) in the feedback loop. The resonant frequency can be determined by the formula below. Since the input impedance affects the Q, an FET is a better choice for the active device.

fr = 1/2LCT CT = C1C2 / C1 + C2

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An Op amp Colpitts Oscillator circuit can also be used wherein the Op amp provides the basic amplification needed and the Oscillator frequency is set by an LC feedback network.

Hartley Oscillator

The Hartley oscillator is similar to the Colpitts. The tank circuit has two inductors and one capacitor. The calculation of the resonant frequency is the same.

f = 1/2LTC LT = L1 + L2 + 2M where, M is mutual coupling

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Crystal Oscillator
A Crystal Oscillator is basically a tuned circuit Oscillator using a piezoelectric crystal as a resonant circuit. The crystal ( usually quartz) has a greater stability in holding constant at whatever frequency the crystal is originally cut to operate. Crystal Oscillators are used whenever great stability is required, such as communication transmitters and receivers.

Characteristics of a Quartz Crystal

A quartz crystal exhibits the property that when mechanical stress is applied across one set of its faces, a difference of potential develops across the opposite faces. This property of a Crystal is called Piezoelectric effect. Similarly, a voltage applied across one set of faces of the Crystal causes mechanical distortion in the Crystal shape. When alternating voltage is applied to a crystal, mechanical vibrations are set up these vibrations having a natural resonant frequency dependent on the Crystal. Although the Crystal has electromechanical resonance, we can represent the Crystal action by equivalent electrical circuit as shown.

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 The inductor L and the capacitor C represent electrical equivalents of Crystal mass and compliance respectively, whereas resistance R is an electrical equivalent of the crystal structures internal friction. The shunt capacitance CM represents the capacitance due to mechanical mounting of the crystal. Because the crystal losses, represented by R, are small, the equivalent crystal Q factor is high typically 20,000. Values of Q up to almost 106 can be achieved by using Crystals. The Crystal can have two resonant frequencies. One resonant condition occurs when the reactances of the series RLC leg are equal. For this condition, the series resonant impedance is very low ( equal to R). The other resonant condition occurs at a higher frequency when the reactance of the series resonant leg equals the reactance of the capacitor CM. This is parallel resonance or antiresonance condition of the Crystal, At this frequency, the crystal offers very high impedance to the external circuit. To use the crystal properly, it must be connected in a circuit so that its low impedance in the series resonant operating mode or high impedance in the antiresonant operating mode is selected.

Series resonant circuits

To excite a crystal for operation in the series resonant mode, it may be connected as a series element in a feedback path. At the series resonant frequency of the crystal, its impedance is smallest and the amount of feedback is largest.

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 R3 can be replaced with RF choke. Resistors R1, R2 and RE provide a voltage divider stabililized dc bias circuit. Capacitor CE provides ac bypass of the emitter resistor, RFC coil provides for dc bias while decoupling any ac signal on the power lines from affecting the output signal. The voltage feedback from collector to base is a maximum when the crystal impedance is minimum ( in series resonant mode). The resulting circuit frequency of oscillation is set by the series resonant frequency of the crystal. The circuit frequency stability is set by the crystal frequency stability which is good.

Parallel resonant circuits

Since the parallel resonant impedance of a crystal is a maximum value, it is connected in shunt. The circuit is similar to a Colpitts circuit with Crystal connected as inductor element. Maximum voltage is developed across the crystal at its parallel resonant frequency. The voltage is coupled to the emitter by a capacitor voltage divider capacitors C1 and C2.

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Crystal Oscillator using op amp

An Op amp can be used in a crystal oscillator. The crystal is connected in the series resonant path and operates at the crystal series resonant frequency.

Unijunction Oscillator
Unijunction transistor( UJT) can be used in a single stage oscillator circuit to provide a pulse signal suitable for digital circuit applications. The UJT can be used in relaxation oscillator.

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The operation of the circuit is as follows: C1 charges through R1 until the voltage across it reaches the peak point. The emitter current then rises rapidly, discharging C1 through the base 1 region and R3. The sudden rise of current through R3 produces the voltage pulse. When the current falls to IV the UJT switches off and the cycle is repeated. Oscillator operating frequency fo = 1/{RTCTln[1/(1-)]} where, is intrinsic standoff ratio, typically the value of it is between 0.4 and 0.6. Using = 0.5, fo = 1.5 / RTCT Capacitor is charged through resistor RT toward supply voltage VBB. As long as the capacitor voltage VE is below a stand off voltage (VP) set by the voltage across B1-B2 and the transistor stand off ratio . VP = VB1VB2 VD. When the capacitor voltage exceeds this value, the UJT turns ON, discharging the capacitor. When the capacitor discharges, a voltage rise is developed across R3. The signal at the emitter of UJT / across the capacitor is saw tooth, at the base 1 are positive going pulses and at the base 2 are negative going pulses.

Summary:
Phase shift Oscillator, f = 1/2RC6 , = 1/29 Wien bridge Oscillator f = 1/2RC Colpitts Oscillator, f = 1/2 LCeq Ceq = C1C2/(C1+C2) Hartley Oscillator, f = 1/2 LeqC Leq = L1+L2+2M UJT Oscillator: f = 1/{RTCTln[1/(1-)]}

110