The circuit diagram of the Transistor Transistor Logic inverter is shown in Figure 2.1. This circuit overcomes the limitations of the single transistor inverter circuit. (i) An input transistor, T1, which performs a current steering function, can be thought of as a back-to-back diode arrangement. VCC
RB T1
RB
Figure 2.2 Equivalent of Input Current-Steering Transistor The transistor can operate in either forward or reverse mode to steer current to or from T2 . Since it has a forward current gain, it provides a higher discharge current to discharge the base of T2 when turning it off. (ii) The output transistor pair, T3 and T4 referred to as a totem-pole output, provides the ability to actively source or sink current and is useful for driving capacitive loads. Resistor, R 3 , serves to limit current. Under steady-state conditions, only one transistor is ON at a time.
T4 OFF
RL T4 ON
T3 ON
T3 OFF
RL
130 1.6k 4k
R3
RB
R1 T4
Input
T1
T2
T3
Output
Vi
1k
R2
VO
VO
4
VOH MIN
(2.86V)
VOL MAX
(0.2V)
D
0
Vi
0.5V
VIL MAX
(1.2V)
VIH MIN
(1.4V)
Figure 2.1 Schematic Diagram and Transfer Characteristic of a Standard TTL Inverter
(iii)
The diode, D, serves to increase the effective VBE of T4 which allows T4 to be turned OFF before T3 turns ON fully. This prevents large surge currents from flowing when both transistors conduct during transitions between logic states. The disadvantage is that the high logic voltage is reduced by an amount of the diode drop as shown in Figure 2.4.
T4
T3
VO
(iv) Finally, T2 is a phase splitter driving transistor to drive the output stage. It allows the logic condition to be phase-splitted in opposite directions so that the output transistors can be driven in anti-phase. This allows T3 to be ON when T4 is OFF and vice versa as shown in Figure 2.5.
RC VO1
T2
VO2
RE
The logical functioning of the circuit can be established by determining the state of conduction of each transistor in turn from input to output for all possible combinations of input states. Transistors can be taken as either ON or OFF. Note that the input transistor, T1, may conduct in either forward or reverse mode. Drawing up a table of conduction states accordingly with reference to Figure 2.1 gives: INPUT LO HI T1 ONfor ONrev T2 OFF ON T3 OFF ON T4 ON OFF D ON OFF OUPUT HI LO
The transfer characteristic can be deduced by applying a slowly increasing input voltage and determining the sequence of events which takes place with regard to changes in the states of conduction of each transistor and the critical points at which the onset of these changes occur. Consider the circuit and transfer characteristic of Figure 2.1.
Point A
With the input LO and the base current supplied to T1, this transistor can conduct in the forward mode. Since the only source of collector current is the leakage of T2 then T1 is driven into saturation. This ensures that T2 is OFF which, in turn, means that T3 is OFF. While there is no load present, there are leakage currents flowing in the output stage which allow the transistor T4 and the diode D to be barely conducting at cut-in.
VO = VCC VBE 4
CUT IN
VD
CUT IN
Point B
As the input voltage is slowly increased, the above condition prevails until, with T1 ON in saturation, the voltage at the base of T2 rises to the point of conduction. Then
Vi = VBE 2
CUT IN
VCE 1
SAT
Point B : Vi = 0.5V VO = 4V
Point C
As the input voltage is further increased, T2 becomes more conducting, turning fully ON. Base current to T2 is supplied by the forward biased base-collector junction of T1 which is still in saturation. Eventually, T3 reaches the point of conduction. This happens when
Vi = VBE 2
ON
+ VBE 3
CUT IN
VCE 1
SAT
VCE 2 = VCC VR VR
1
VO = VCC VR VBE 4 ON VD ON
1
Point D
As the input voltage is further increased, T2 conducts more heavily, eventually saturating. T3 also conducts more heavily and eventually reaches the point of saturation also. As T2 becomes more conducting, its collector current increases. This in turn increases the voltage drop across R1 which in turn means that the voltage across T2 i.e. VCE2 drops. This falls below the requirement for conduction in T4 and the diode, D, so that both of these turn OFF prior to the saturation of T3. When T3 reaches the edge of saturation:
Vi = VBE 2
SAT
+ VBE 3 VCE 1
ON
SAT
0.2V VO = 0.2V
Point D : Vi = 1.4V,
2.4
Noise Margins
Using points C and D on the transfer characteristic in Figure 3.1 to identify the critical points, we have
NM L = 1.0V NM H = 1.4V
NM L = 0.4V NM H = 0.4V