DESIGN AND CONSTRUCTION OF DATA TRANSMISSION ERROR CONTROL SYSTEM USING A MICRO-CONTROLLER PROJECT SUBMITTED BY ONOTAME ONORIODE JEROME

U2005/3015357 AND IKPE MICHAEL SYLVESTER U2005/3015296 TO THE DEPARTMENT OF EELECTRICAL/ELECTRONICS FACULTY OF ENGINEERING UNIVERSITY OF PORT HARCOURT IN PARTIAL FULFILMENT FOR THE AWARD OF A BACHELOR'S DEGREE OF ENGINEERING (B.ENG) IN ELECTRICAL/ELECTRONIC ENGINEERING, FACULTY OF ENGINEERING, UNIVERSITY OF PORT HARCOURT, NIGERIA NOVEMBER, 2010. ABSTRACT Data transmission error control system using a micro-controller is a method of d etecting and correcting errors in transmitted data. It has become a panache as compared with the retransmission me thod when an error is detected. This project offers a comprehensive analysis and implementation of the operation of a data transmission error control system using the Hamming code. It employs a 74LS147 decoder, micro-contr oller, transistors and diodes as the key elements in the control circuit. The analysis of the design methodolo gy was carried out in five stages viz: The power supply unit, the keypad unit, the error injection unit, the displ ay unit and the micro-controller programming unit. This project is convincingly recommendable for real life error simulation in data transmission, as it offers zero adverse effect to the ecological environment, an optimal control method, and serves as an improvement over retransmission method in this era of fast growing technological advancement. The whole process can be seen clearly from the flowchart below. DECLARATION I hereby declare that this project work is mine and that it has not been submitt ed before anywhere for the purpose of awarding a degree to the best of my knowledge. ONOTAME ONORIODE JEROME .......................... IKPE MICHAEL SYLVESTER ........................... CERTIFICATION This is to certify that the project work was carried out under my supervision by Onotame Onoriode Jerome (U2005/3015357) and Ikpe Michael Sylvester (U2005/3015296) of the department of electronics engineering during the 2009/2010 academic session. Sign:................................... sign:.................................. .... Engr, Mrs. Orakwe Engr, Dr. U. A. C. Kamalu (Project Supervisor) Head of Department Date:................................... Date:.................................. ... sign:.................................... sign:.................................

...... (External Examiner) Engr. Eteng (Project Coordinator) Date:.................................. Date:................................... ..... DEDICATION I dedicate this work, firstly, to the almighty God for his grace and protection upon my live during this period of study. Also, to my late father, Mr. Manson E. Onotame, for his words of encourag ement that have guided me till date. And lastly, to my lovely children, Jerome jnr. And Freda. ACKNOWLEDGEMENT I sincerely acknowledge, firstly, my lovely wife, Mrs Onotame Orhie Choice, for her love, care and words of inspiration that relieve me whenever a problem is encountered academically, my g uardians Engr. and Dr. Mrs. Oguni Blessing for their financial support throughout my stay in school. I also acknowledge Barrister Joshua Atikpakpa for his financial support, my siblings and all my friends for their wo rds of encouragement. Also, my little niece, Tracy, who has saved me a whole lot of money for typing this proje ct. Lastly, all my lecturers and fellow colleagues. LIST OF FIGURES FIGURE PAGE Fig 1.1: Block diagram of data transmission error control system Fig 3.1: Block diagram of data transmission error control system Fig 3.2: Block diagram of a regulated DC power supply Fig 3.3: Schematic diagram of 5V power supply Fig 3.4: The circuit diagram of the display unit Fig 3.5a: The schematic diagram of the keypad unit Fig 3.5b: The circuit diagram of the keypad unit Fig 3.6: The 74LS147 encoder pin configuration Fig 3.7: A single keypad unit Fig 3.8: The circuit diagram of the error detection unit Fig 3.9: The block diagram of AT89C52 microcontroller Fig 3.10: Diagram showing pin out of the microcontroller Fig 3.11: Schematic diagram of a configured AT89C52 microcontroller Fig 3.12: The complete circuit diagram of the data transmission error control sy stem LIST OF TABLES TABLES PAGE Table 3.1: The output value of the encoder when each key is depressed Table 4.1: The result of transformer test Table 4.2: The result of bridge rectifier test Table 4.3: The result of regulator test Table 4.4: The result of transistor test Table 4.5: The result of the PSU component test Table 4.6: The result of the microcontroller unit test TABLE OF CONTENTS TITLE. ABSTRACT.. CERTIFICATION.. DEDICATION ACKNOWLEDGEMENT LIST OF FIGURES

LIST OF TABLES.. TABLE OF CONTENTS.. CHAPTER 1: INTRODUCTION 1. PROJECT BACKGROUND a. STATEMENT OF PROBLEM b. SIGNIFICANCE OF PROJECT c. SCOPE OF THE PROJECT d. LIMITATIONS OF THE PROJECT e. OBJECTIVE OF THE PROJECT f. METHODOLOGY CHAPTER 2: LITERATURE REVIEW 2.1 TECHNIQUES OF ERROR DETECTION AND CORRECTION 2.2 DATA TRANSMISSION 2.2.1 CHARACTERISTICS OF DATA TRANSMISSION 2.2.2 COMPONENTS OF DATA TRANSMISSION 2.3 ERROR IN DATA TRANSMISSION 2.3.1 ERROR DETECTION 2.3.2 ERROR CORRECTION 2.4 MICROCONTROLLER 2.4.1 EVOLUTION OF THE MICROCONTROLLER 2.5 DISPLAYS CHAPTER 3: DESIGN ANALYSIS AND SPECIFICATION 3.1 THE POWER SUPPLY UNIT 3.2 THE DISPLAY UNIT 3.3 THE KEYPAD UNIT 3.4 ERROR INJECTION UNIT 3.5 MICROCONTROLLER UNIT 3.5.1 CONFIGURATION OF MICROCONTROLLER 3.6 PRINCIPLE OF OPERATION CHAPTER 4: HARDWARE CONSTRUCTION AND RESULT 4.1 STATIC TESTING OF COMPONENTS 4.1.1 TRANSFORMER TESTING 4.1.2 BRIDGE RECTIFIER TESTING 4.1.3 VOLTAGE REGULATOR TESTING 4.1.4 CAPACITOR TESTING 4.1.5 TRANSISTOR TESTING 4.2 SYSTEM INTEGRATION 4.2.1 MOUNTING AND CONNECTION OF COMPONENTS 4.3 TESTING OF SYSTEM 4.4 HOW TO DETECT THE ERROR 4.5 PERFORMANCE EVALUATION 4.6 PROBLEMS ENCOUNTERED 4.7 SOLUTIONS PROFFERED CHAPTER 5: CONCLUSION AND RECOMMENDATION 5.1 CONCLUSION 5.2 RECOMMENDATION REFERENCES APPENDIX CHAPTER 1 1.0 INTRODUCTION 1. BACKGROUND OF STUDY When data are transmitted over digital channel, the problem of noise such as sta tic on device, environmental interference, or scratches on electronics data storage media induces bit error. In a digital computer such bit error can cause a complete failure of data in the sense that if it is detected, no mor e computing can be done until the failure is located and corrected, while if it escape detection then it invalidat e all subsequent operation of the machine.[R.W.Hamming, 1950].

There are several techniques for generating check bits that can be added to a me ssage. Perhaps the simplest is to append a single bit, called the parity bit, which makes the total number of 1-bits in the code vector (message with parity bit appended) even (or odd). If a single bit gets altered in transmi ssion, this will change the parity from even to odd (or the reverse). The sender generates the parity bit by simply summing the message bits modulo 2that is, bye xclusive oring them together. It then appends the parity bit (or its complement) to the message. The receiver can check the message by summing all the message bits modu lo2 and checking that the sum agrees with the parity bit. Equivalently, the receiver can sum all the bits (message and parity) and check that the result is 0 (if even parity is being used). This simple parity techniqu e is often said to detect an error but cannot correct it. A technique that is believed to be quite good in terms of error detection and co rrection which is easy to implement in hardware, is the error detection and correction using a microcontroller. This system combines both the Parity Bit Che ck and the Hamming Code in its implementation. We shall assume that the transmitting equipment handles info rmation in the binary form of a sequence of 0s and 1s. This assumption is made both for mathematical convenience a nd because the binary system is the natural form for representing the open and close relays, flip-flop circuit, dots and dashes, and perforated tapes that are used in many forms of communication. Thus, each code s ymbol will be represented by sequence of 0s and 1s. (Moser, 1969 ). The codes used in this system (Parity and Hamming codes) are systematic codes; t hat is, codes in which each code symbol have exactly n binary digits, where m digits are associated with the information while the other k = n m digits are used for error detection and correction. This produces a redundan cy, R, defined as the ratio of binary digits used to the minimum number needed to convey the same information; that is, R = n/m. The system utilizes an ATMEL89C51 microcontroller with port 0 as the output port to the dis play unit, port 1 as input switches to input function into the microcontroller unit, port 2 as output port to decoder (74LS164) and port 3 as port to input data into the microcontroller from the encoder. The program is als o written in assembly language. However, the theory will be reviewed briefly in subsequent chapters. 1.2 STATEMENT OF PROBLEM One of the major problem of the world today is the problem of doing things right a nd this is not an exception in communication. In transmitting of information (data) from one place to another, digital machines use codes which are simply set of symbols to which meaning of values are attache d. These codes are sometimes prone to channel noise which includes bits error hence a means for self checking is needed, this is error detection. In some situations, self checking is not enough because in a noisy transmission medium, a successful transmission (that is, retransmission) coUld take a long time or may never occur . The present trend is towards

electronic speed in digital computers where the basic elements are somewhat more reliable per operation than relay. Thus, it appears desirable to examine the next step beyond error detectio n, namely, error correction. 1.3 SIGNIFICANCE OF THE PROJECT The significance of data transmission error detection and correction system is c lear from the cost and time wasted in retransmission. The correctness of information is critical to precisio n theory and modern quest for optimization of our processes. The present trend is towards electronic speed in digital computers, also the ability to correct single bit errors comes at a cost which is less than sending the enti re message twice. Hence, the quest for computer and information analyst, electronic and telecommunication engineers to provide a better way of error detection and correction is important to the businessman who will not like to pay for the retransmission of the message or wait for it. 1.4 SCOPE OF THE PROJECT The scope of the project includes the following: Designing of electronic system to implement Hamming code theory of one bit error correction of two bit error detection. Developing and writing technical paper in view to explaining the methodology, pr ocedures, cost, timing, Construction details and challenges thereof. Developing a personal theoretical and technical mastery of EDAC 1.5 LIMITATION OF THE PROJECT The project is limited to the following: Subject to single bit error correction in data transmission. Subject to Electronic board simulation of errors 1.6 OBJECTIVES The objectives of this project include: Encoding a K-bit data word to form a code word by adding M-bit parity to check f or position of error and correcting it by using hamming code with the formula (2m - 1, 2m - 1 m, m) Detecting up two bit error by the use of hamming code Correction of a single bit error 1.7 METHODOLOGY The design of this project work can be effectively done through district units p rocesses or parts. Here, the system is broken down into units and each unit is effectively designed as shown in figure 1.1. The design however will be based on the following: One bit data error correction Two bit data error detection Data encoding Burning of an assembly language program on a micro chip which serves as the system processor. CHAPTER 2 LITERATURE REVIEW Data transmission error control is the detection and correction of error in tran smitted data caused by environmental interference, scratches on data storage media, e.t.c. The study of error control was led from a consideration of large scale computing machines in which a large number of opera tions must be performed without a single error in the end result. Also, the present trend is towards ele

ctronic speed on digital computers where the basic element are somewhat more reliable per operation. (R.W.Hamming, 1950) A lot of work has been done over the years to device a circuit for self-checking of an error in data transmission some of which are highlighted thus: On August 31st, 1971, Williams C. Carter and Peter R. Schneider were patented (0 4/747522) for the invention of a self-checking error checker for parity coded data. In their work, they stated that a self-checking error checker can be provided for parity coded data by preferably utiilising at least two single output exclusive OR logic trees connected to non-overlapping group of input data wherein every li ne is included in one of said group. They also said that the technique consists of adding one binary digit, th e check bit, to each binary coded message or word and setting its value such that the parity of 1s in the message is a constant. That is, the number of 1s in all message is odd or the number of 1s in all message is even. A chang e in value of any single bit in a message will clearly change its parity which indicates an error. In conclusion, they said that the circuit can only detect an error but cannot make correction of it. On Feb. 5, Lawson, Brian R. was patented (06/412487) for the invention of an M out of N code checker circuit. In his work, he stated that an M out of N code (M less than N) is a fixed weight code with a fixed number (M) of ones and a fixed number (N M) of zeros out of a total number (M) of word bits which is capable of detecting any single bit or unidirectional multibit err or in an input, control, word. He also stated that for an error to be undetected by such a checker circuit, there must be an equal number of zero goes to one errors as one goes to zero errors that also the circuit will fail to correct an error. This project is to boost the prior achievement in detecting error in data transm ission by using parity bit check and correcting the error by using Hamming code. 2.1 TECHNIQUES OF ERROR DETECTION AND CORRECTION Since the advent of telecommunication, telecommunication engineers have worked s o greatly to combat the problem of bit errors introduced into valid data due to static on device, enviro nmental interference or scratches on electronic data storage media. Among the earliest techniques are: The parity bit check: This code was in use in the early stage of telecommunicati on that is, between the early and late 40s (PETERSON W.W, 1972). A parity bit is a bit that is appended t o a bit stream to make the total number of 1 bits in a given set of bits always even or odd. Parity checks ar e the simplest error detecting system. For example, if we send some specific sequence of 1s and 1s, and then coun t the number of 1s that we sent and send an extra 1 if that count is odd (making the total even) or an e xtra 0 if that count is already even, a single bit error can be detected: The receiver can count up the number of 1 bi ts they received., perform the same calculation, and if the result is not even, they will know that an error oc curred. Parity checks have serious limitations: The receiver has no way of knowing which bit was wrong, and if two bits were changed in a value,(e.g. a pair of 1s are both changed to 0s) then the errors

would pass undetected. Longitudinal Redundancy Check (LRC): A simple parity value calculated on columns of data rather than rows, where each successive set of data is exclusive ORd (XORd) with the prio r set to form a new set of parity values. LRCs by themselves, can only detect errors, but have a slight advantage over stan dard parity bits in that they are less sensitive to burst errors in serially transmitted data. For example, wi th a drop-out burst error of 3 bits starting after the first bit of the first byte 10110001 even parity = 0 10000001 even parity = 0 (still) 11011011 even parity = 1 11011011 even parity = 1 ------------ -----------01101010 = LRC 01011010 = LRC Note that if the data were being transmitted in parallel, the advantage reverts to simple parity as the LRC becomes sensitive to burst errors. Hamming Code: Hamming worked in Bell Labs in the 1940s on the bell model V compu ter, an electrochemical relay-based machine with cycle times in seconds. Input was fed i n on punched cards, which would invariably have read errors. During weekdays, special code would find erro rs and flash light so the operator could correct the problem. During after-hours periods and on weekends, when there were no operators, the machine simply moved on to the next job. Hamming worked on weekends and grew increasingly frustrated with having to restart his program from scratch due to the unreliability of the card reader. Over the next few years, he worked on the problem of error-correction, developing an increasingly powerful array of algorithms. In 1950, he published what is known as the Hamming code which is still in use today in applications such as ECC memory. (R.W. Hamming, 1950) The use of simple parity allows detection of single bit err ors in a received message. Correction of such errors requires more information since the position of the ba d bit must be identified if it is to be corrected. (If a bad bit can be found, then it can be corrected by simply com plementing its value.) Correction is not possible with one parity bit since any bit error in any position produces exactly the same information bad parity. If more bits are included with a message, and if those bits can be arr anged such that different error bits produce different error results, then bad bits will be identified. In a sev en bit message, for instance, there are seven possible single bit errors, so three error control bits could potentially specify not only that an error occurred, but also, which bit caused the error. The Hamming code allows error co rrection because the minimum distance between any two valid code words is 3. For example, it takes 3 bit chan ges (errors) to move from one valid code word, say 000 to the other, 111. If the code word, 000, is transmitte d and a single bit error occurs, the received word must be one of (001, 010, 100), any of which is easily identified as an invalid code word, and which could only have been 000 before transmission. W. Wesley Peterson Fire Code: This code was developed in the 1970s. They are a tricky way of

providing the same results as row and column parity or CRC. They are very fast t o decode and check, and can be used to correct errors as well. Fire codes operate because of the careful sel ection of the CRC-generating polynomial. (X^23+1)(X^17+X^3+1) These special polynomials contain two prime-pol ynomial factors, each of which helps locate a detected error. Knowing the location of a transmitt ed error modulo and the degree of each of these prime-polynomial factors, you can apply the Chinese rema inder theorem to locate the exact bit error. Although the math sounds complex, you can easily implement it with high-speed D flip-flops and XOR gates. If a 32-bit fire-code-protected block contains two err ors separated by exactly 11 bits, the fire code fails to correct the errors. Each parity bit is the XOR o f parity for the data byte with which it is associated and parity for staggered bits from the eight previous byt es. Essentially, it is a clever way to obtain the same results as are provided by the use of row and column pari ty bits (After the last byte of data, one extra byte, with the extra parity bit, is needed to provide pa rity for all the remaining diagonals). (Simon Rockliff, 1991). Reed Solomon code: Reed-Solomon block codes are popular in communications and da ta-storage applications. Like fire codes, Reed-Solomon implementations append symbols to th e end of a transmission to locate and correct errors during decoding. Reed-Solomon code systems effectivenes s at high data rates results from operations taking place at the code-symbol rate or at a fixed number of tim es per code word. Either way, the number of operations is much smaller than the number of bits. Chips that imp lement these types of highspeed real-time correctors are commercially available, ass are DSP-software options. Each RS symbol is actually a group of M bits. Just one bit error anywhere in a g iven symbol spoils the whole symbol. Thats why RS codes are often called burst-error-correcting codes; Many RS c odes in use are shortened, i.e., the block size, or number of symbols used: N is smaller than the symbol size, or maximum number of symbols: 2M-1 would indicate. Since RS can be done on any message length and can add any number of extra check symbols, a particular RS code will be expressed as RS (N.N-R) code where N is the total number of symbols per codeword; R is the number of check symbols per codeword and; therefore, N-R is the number of actual information symbols per codeword. The typical RS decoder can correct up to (N-R)/2 symbol errors per blo ck. (S.B. Wicker, 1994) The M out of N Code: An M out of N code (M less than N) is a fixed weight code w ith a fixed number (M) of ones and a fixed number (N minus M) of zeros out of a total number (N) of word bits or lines. The M out of N codes is useful because they can detect all unidirectional errors. Us eful application for these codes is in digital data transfers, communications and storage. Additionally, th ese codes have been utilized in the arithmetic sections of digital computers, including the 2 out of 7 code i n the IBM 650 and a 2 out of

5 code in the IBM 7070 The data transmission error detection and correction method using a microcontrol ler: Looking above to all the technique for detecting and correcting error, it can be seen th at, some can only detect a single bit error, without correction while some can only correct. In this project work, the circuit is designed and programmed to detect and correct a single bit error at the same time. It combine s both the features of the parity bit check and the Hamming code technique. Useful application for this circuit is in digital data transfers, communications and storage. A detail of this is given in subsequent chapters. 2.2 DATA TRANSMISSION The widespread development of data communication systems, the data communication revolution has been driven by the ever increasing use of computer in many diverse applications in in dustries, commerce and more latterly, the home. For a long time, stand-alone computers provide an invaluable scientific and data processing work. But over the years, because of changing economic patterns of usage in comp uting, there has developed the need for people to communicate with remote computers. It has therefore, beco me more apparent that it is the merging of the two technologies of telecommunication and computing that will mak e the greatest economic and social impact in society. (R.W. Hamming Error Detection and Error Correction Code s Bell Systems Tech. Journal, vol 29, pp 147-160, April 1950.) Hence, data communication is the trans mission of data between two devices over some communication media such as wire cable. 2.2.1 CHARACTERISTICS OF DATA TRANSMISSION For data to be transmitted over a communication media, there are some characteri stics to be considered which include: Delivery: The system must deliver data to the correct destination. Accuracy: The system must deliver the data correctly and accurately to the desti nation. Timeless: The system must deliver data in a timely manner. 2.2.2 COMPONENTS OF DATA TRANSMISSION Some of the components of data transmission include: Message: This is the data to be transmitted which can consist of numbers, pictur es, video, audio, etc. Medium: This is the path through which the message travels. Sender: This is the device that sends the information. It could be a computer, w orkstation, telephone handset, etc. Receiver: This is the device that received the message. It could also be a compu ter, workstation, telephone handset, etc. Protocol: This is a set of rules that govern data communication. It represents a n agreement between two devices. 2.3 ERROR IN DATA TRANSMISSION In most communication channels, a certain level of noise and interference is una voidable. Even after the design of digital transmission systems has been optimized, bit error in transmis sion will arise with some small but non-zero probability. For example, typical bit error rate for system that us es copper wire are in the order of 10-6 that is, one in a million.(PETERSON W.W,1972.)

Hence, errors in data transmission and noise or unwanted signals which are induc ed into data stream due to environmental interference, static on device, scratches on electronic data stora ge media, etc. It varies in proportion from single bit errors, burst-bit error, to lost bit error. Single Bit Error: These are errors that occur due to a change in a single bit during data transmission. A------------------------transmission line------------------B 1010 0010 (single bit error) Burst Bit Error: This is a change in more than one bit when a stream of data is transmitted from one point to another. A------------------------transmission line------------------B 100101 011100 (burst bit error) Lost Bit Error: This is a situation in which there is no data received at all. A-----------------------transmission line--------------------B 2.3.1 ERROR DETECTION The study of error detection was led from a consideration of large scale computi ng machines in which a large number of operations must be performed without a single error in the end result. This problem of doing things right on a large scale is not essentially new; in a telephone central office, for example, a very large number of operations are performed while the errors leading to wrong numbers are kept well under control, though they have not been completely eliminated. This has been achieved, in part, through th e use of self-checking circuits. (R.W. Hamming, 1950) The information produced by an application is encoded so that the stream of data that is input into the channel satisfies a specified pattern or condition. The receiver checks the stre am of data coming out of the communication channel to see if the pattern is satisfied. If it is not, the rece iver can be certain that an error has occurred. This certainly stems from the fact that no such pattern would have bee n transmitted by the encoder. The simplest code is the single parity check codes which take k-information bits and add a single check bit to form a code word. The parity check ensures that th e total number of 1s in the code word is even, that is, the code word has even parity. The check bit in this case is called a parity bit. This error detection code is ASCII where characters are represented by 7 bits and the 8th b it consists of a parity bit. 2.3.2 ERROR CORRECTION In the telephone central office considered above, there are a number of parallel paths which are more or less independent of each other. In a digital machine, there is usually a single long path which passes through the piece of equipment many times before the answer is obtained. In some situations, self-checking is not enough. For example, in the model-5 relay computer built by Bell Telephone laboratories for the Aberdeen proving ground, observation in the early period indicated about two or three relay failu res per day in the 8900 relays of the two computers representing about one failure per two to three million relays operation. The self-checking feature meant that these failures did not introduce undetected error. But since the machines were run on an unattended basis overnight and on weekends, the errors meant that frequently, th e computation came to a halt.

(R.W. Hamming, 1950) The present trend is towards electronic speed in digital computers where the bas ic elements are somewhat more reliable per operation than relay. However, the incidence of isolated failure ev en when detected may seriously interfere with the normal use of such machines. Thus, it appears desirable to ex amine the next step beyond error detection, namely, Error Correction. The use of simple parity allows detection of single bit errors in a received mes sage. Correction of such errors requires more information since the position of the bad bit must be identified if it is to be corrected. (If a bad bit can be fo und, then it can be corrected by simply complementing its value.) Example of an error control method allowing correction of a single bit error is the Hamming code. 2.4 Microcontroller A microcontroller is a computer-on-a-chip. Micro suggests that the device is sma ll, and controller tells that the device might be used to control objects, processors or events. Another term to describe a microcontroller is an embedded controller, because the microcontroller and its support circuits are often built in to, or embedded in the device they control. Microcontrollers can be found in all kinds of devices t hese days. Any device that measures, stores, controls, calculates or display information in most cases comp rises of a microcontroller. In this project, the ATMEL microcontroller AT89C52 was used. The AT89C52 is a lo w-power high performance CMOS 8-bit microcontroller with 4kbytes in system programmable flash memory. The device is manufactured using ATMELs high density non-volatile memory technology and is comp atible with industry standard 8051 instruction set and pin out. The on chip flash allows the program memory to be reprogrammed in a system or by a conventional memory programmer. 2.4.1 Evolution of the microprocessor The first generation of the microprocessors (1971-1973) was designed using the p ositive-type metal oxide semiconductor (PMOS) technology. This technology possessed such features as; low cost, low spe ed, low current outputs and were incompatible with transistor-transistor logic (TTL). It was a 4 -bit microprocessor introduced by Intel Corporation as the first micro processor. It evolved from a development effort while designing a calculator chip. The second generation of microprocessors (1974-1978) includes Motorola 6800, Int el 8085 and Ziglog 280. These were 8-bit processors fabricated using NMOS (negative type) technology. Th e NMOS processors were faster, TTL compatible and had higher circuit density (more components on-board) than the first generation PMOS processors. The third generation microprocessors (1979) were 16-bit wide and included typica l processors like Intel 8086 and Motorola 68010. These were designed using the high density metal oxide semic onductor (HMOS) technology, whose merits over the NMOS type include: a speed-power product (in p icojoules) four times better than the NMOS, and circuit density almost twice that of the NMOS processors. The fourth generation (1980) microprocessors were introduced by Intel as the fir

st commercial 32-bit wide microprocessors. These processors were fabricated using low power version of HMO S technology called the HCMOS technology. Later on, 32-bit RISC (Reduced Instruction Set Computer) micro processor was introduced to maximize speed by reducing the number of clock cycles per instruction. RISC m icroprocessors enable the simultaneous execution or processing of instructions through a mechanism called pipelining. RISC-based architecture is the fastest microprocessor available today. Despite its relatively old age, the 8052 is one of the most popular microcontrol lers in use today. Many derivative microcontrollers have since emerged that are based on and compatible with 8052. Thus, the ability to program an 8052 is an important skill for anyone who plans to develop products that will take advantage of microcontrollers, such as in this project, Steiner (2006). It is worthy to mention that the microcontroller is an integration of the microprocessor, I/O (input-output) and memory on a single chip. Thus, the 8052 m icrocontroller has I/O ports called special function registers (SFR) that are not used for data storage, but for I/O operations (that is, reception and sending of current pulses through its ports), as well as three general memor y types viz: code memory, external RAM (off-chip) and On-chip memory. 2.5 Displays In 1908, F.W. Wood invented an 8-segment display, which displayed the number, 4, using a diagonal bar. They were used in unsophisticated displays like cardboard For Sale signs, where th e user either applied color to pre-printed segments, or sprayed color through a seven-segment digit template to compose figures such as product prices or telephone numbers. However, they did not achieve widespread us e until the advent of LEDs in the 1970s. This led to the design of seven-segment configurations. Seven-segment display is one of the simplest and most popular methods for displa ying numerical digits with decimal characters 0 through 9, and sometimes the hex characters A through F, To cci(2004). A seven segment display as its name indicates is composed of seven elements. Seven-segment displays can be constructed using any of a number of different tec hnologies. The three most common methods are: Fluorescent displays used in many line-powered devices such as microwave ovens a nd clocks. Liquid crystal display used in many battery powered devices such as watches and in digital instruments. Light emitting diodes used in either line-powered or battery-powered devices. Fluorescent displays require a fairly high driving voltage to operate, while liq uid crystal displays require special treatment. CHAPTER 3 DESIGN ANALYSIS AND SPECIFICATION In the implementation of this project,certain logical mathematical and analytica l steps were taken into consideration in determining the hardware component values required in each unit . These discreet units or parts are each made up of smaller components and the reason for the choice of each com

ponent is the focus of this section. The units are combined in a definite pattern to form the overall circui t design, and the direct relationship between the separate units is described using the block diagram shown below in f ig 3.1 and each block is broken down in details for a comprehensive explanation of every step involved in this work for ease of execution of the project with or without the designer. It should be noted that t he micro-controller unit is replaced in the block diagram with its sub-unit (CPU, encoding unit, error detecting unit and decoding unit) for clarity of how the project works. 3.1 POWER SUPPLY UNIT/CHOICE OF COMPONENTS This unit is the power source for the entire system. It involves four essential stages namely: transformation, rectification, filtering and regulation stages in that order. Two basic dc sourc es are required for the entire circuit viz: +9 volts and +5 volts. The +9 volts dc source is required for the operation of the brightness of the LEDs (that is the brightness control of the display unit), while the +5 volts dc source is required for the operation of all the digital integrated circuits (ICs) involved in the work. The required power sourc es will determine the particular transformer to be used. The components used in the power supply unit, and the ch oice of values are detailed as below. The block diagram showing the above components is shown in figure: The transformer is used both for isolation of mains voltage and transformation o f the voltage from one circuit to another. The required power supply voltage is 5V. a transformer of 240V/12V woul d be ideal to use. Recall that: Where VMAX VRMS = 16.97V Choice of bridge rectifier depends on the maximum voltage it can withstand under reverse voltage which is known as peak inverse voltage (PIV) and the maximum current. It is necessary tha t: .. (3.2) The maximum current that can be drawn by the rectifier is 100mA. Hence a bridge rectifier with PIV = 100V and IMAX =1A was used. If the output voltage of the rectifier is represented by VIP, then: (3.3) Where, VD = diode drop = 0.7 V Recall that for full wave rectification; .. (3.4) Where f = ripple frequency in Hz C = minimum capacitance in F IDC = desired power supply current in Amp. Equation 3.4 can be rearranged to give: .. (3.5) Assuming the ripple is to be kept below 3%, then substituting f = 50Hz, VIP =15. 57V and IDC = 100mA into equation 3.4:

F F The capacitor is expected to withstand comfortably the 15.57V. To achieve this, a capacitor of 1000F/25V was used. The capacitor does not stabilize the voltage nor provide the required 5V. Hence a 7805 voltage regulator was used to obtain the desired 5V. 1. THE DISPLAY UNIT The display unit is used to display transmitted and processed data in binary for m. The component used for the display unit include BC1815 general purpose transistor, 9-volt DC supply and 16 LEDs as shown in figure 3. 6 below. The brightness of the display unit is a function of the power consumed which in turn, is a function of current. From data specification of BC1815 general purpose transistor, the collector curr ent Ic, is 1mA. This current flows through the LED at transistor cut-off point. Hence, the maximum current al lowable for a single LED is 1mA. But since the LEDs cannot be run at their maximum current specification, it is assumed that the LEDs are run at approximately 93.7% of their maximum current rating. But 16 LEDs are used in the project hence the total current consumption is: 16 X (93.7/100 X 1) = 15mA Considering a single part of figure 3.4 shown below, Applying Basic electrical circuit theorem laws. Ohms Law and Kirchhoff voltage l aw with Ra being a fixed while Rv Variable. V Is * Rv Ic *Ra Vrleds = 0 -----------------------------------------------------1 Where Is is the supply current Ic collector current of the Transistor Vrleds is the voltage drop due the internal resistance of the LEDs Hence Making Rv the subject of equation 1 Rv = ( V- Ic*Ra-Vrleds)/Is --------------------------------------------------------2 But: Ic = 1mA Vrleds from specification sheet is equal to 0.2Vots Hence equation 2 will be Rv = (V -1*10^3 *Ra 0.2) / Is ------------------------------------------------------------3 But Ic = 1mA is the maximum the LEDs will withstand. Hence for 80% of LEDs opera tions we will have Ic = 0.8mA Therefore for the total 16 LEDs used with a total current of 15mA, total Ic = 15 X 0.8 = 12mA Hence, For 9volt supply Also If we assume the maximum drop on the Variable to be 0v, then BLUE RED- BROWN Since Ra is fixed Then from equation 5 Rv = 0.16/Is Again if Is = 0. 01mA (assumed between 0mA and 12mA)

5v is used to bias the transistor. Using Kirchhoff's law from the input side of the figure above, Vs Rb*Ib 0.2 = 0 ------------------------------------------------------11 Rb = ( Vs-0.2)/Ib ----------------------------------------------------12 From transistor equation, we have Ic = Ib Assuming a value of 10, Ic =10Ib Hence Ib = Ic/10 -----------------------------------------13 Substituting equation 13 into equation 12 Rb = (vs - 0.2 )/( Ic/10) --------------------------------------14 Rb = (10(vs - 0.2))/Ic ----------------------------------------15 For Vs = 5volt Ic = 12mA BC1815 3.3 Keypad Unit The keypad unit is used to input desired data for transmission based on the need for decimal to binary encoder. It is made of momentary switches with pull up resistor for logic state definitio n. Figure 3.7a and 3.7b below are the schematic and circuit diagrams of the keypad unit respectively. 3.5a Schematic diagram of the keypad unit The choice of encoder here is 74LS147 as shown in figure 3.6 below. Fig 3.6: The 74LS147 Encoder Pin Configuration This type of encoder has ten inputs one for each decimal digit - and four output s corresponding to the binary values. The relationship between the decimal number and its binary value is a fu nction of the pin configuration as shown in figure 3.6. This can be seen and explained from table 3.1 below. Table 3.1: The output value of the encoder when each key is depressed. Decimal Number Binary Representation at the Input of the Encoder Binary representation at the output of the encoder 1 1011 0001 2 1100 0010 3 1101 0011 4 0001 0100 5 0010 0101 6 0011 0110 7 0100 0111 8 0101 1000 9 1010 1001 From the table, it implies that whenever any decimal number is pressed, say 1, t he encoder receives a signal in its input pin 11 (1011) and produces an output 1(0001). This is applicable to any ot her decimal value whenever that key is depressed. It is called high priority active low decimal to binary e ncoder. Hence choice of switch that make up the keypad must be based on the characteristics of the encoder. Since it is active low, press-to make momentary switch is chosen and configured. To fully design the keypad, a single key will be used as shown in figure 3.8 bel ow. Fig 3.7 A single keypad unit Using Kirchhoff voltage law

We have 5 IR = 0 R = 5/I The IC consumes 4.2mA current Hence 3.4 Error injection unit This unit is used in this project to provide us a mean of simulating the errors that real time application will inject into any electronic and data storage systems. The switch to be employed is the m aintained switch. This switches can provide a zero digit in stand of digit 1. With this, the system will contain errors due to transmission. Figure 3.9 below shows the schematic diagram of the error-injecting unit From the circuit applying Kirchhoff voltage law to the circuit we will have. When the switch is depress 5 I*(Rb//R2) Vbe = 0 -----------------------------------------------1 Where Rb*R2/(Rb+R2) = Rt --------------------------------------------2 And Vbe = 0.2v Choosing I = 2.5mA ,From transistor data sheet at saturation mode we will have, And substituting equ 2 into equ 1 and the value of Vbe, we have 4.8 I ((Rb*R2)/(Rb+R2) = 0 ----------------------------------- 3 Cross multiplying with Rb +R2 We now have 4.8R1 + 4.8R2 - I*Rb*R2 = 0 -------------------------------- 4 Making Rb subject of formula Rb = 4.8R2/(I*R2 4.5) ------------------------------------------------5 Rb = 4.8 * 10000/(0.0025*10000 4.5) Considering the collector side of the circuit, Vcc IcR3 Vd = 0 Where Vd is the voltage drop in the diode which is equal to 0.2volts from data s pecification. 1=2.5mA. Hence, Ic = 10 * 2.5 * 10-3 = 0.025A 3.5 Micro-controller Unit/Configuration The micro-controller used in this design is the AT89C52 micro-controller, an Atm el series. Below is the block diagram of a typical microcomputer. Fig 3.9: A block diagram of the ATMEL89C52 Micro-controller The ATMEL89C52 is a low power high performance CMOS 8-bit micro-controller mainl y designed for sequential operation. It has 8Kbytes of flash programmable and erasable read onl y memory (EPROM) on a chip. This device is compatible with the industry standard AT89C52 instruction set and pin out. Therefore, the AT89C52 micro-controller shares a lot in common with the AT8952, and just like a ny other micro-controller, it can be likened to a microcomputer. The on chip flash memory allows the programs memory (code memory ) to be quickly reprogrammed using a non-volatile memory programmer such as the PG 30 2 with the ADT87 adapter. It has an 8-bit micro-processor, an on-chip flash memory, decoders (for decoding or locating data in memory), internal clock timers and counters for counting and for synchronising logic operations in the micro-controller. It can be connnected to off-chip memory device such as static RAM to increase its capacity, and has an external clock circuit called th e crystal oscillator. The AT89C52 is a powerful microcomputer that provides a highly flexible and cost effective s olution to many embedded control applications. The AT89C52 provides the following features:

8 Kbytes of on-chip flash memory (EPROM) 256 bytes of on-chip RAM 32 programming I/O lines Two 16 bit timer/counter Full duplex serial port On-chip oscillator and clock circuitry 40 pin enhanced flash controller High level language program compatible (EMBEDDED C and Assembly languages) Clock (0 20MHz) 6 interrupts-channels 100,000 erasable cycle enhanced flash programmable memory USART (Universal Synchronous Receiver and transmitter) Electrical Characteristics Maximum output current sunk by any I/O pin 25mA Maximum output current sourced by any I/O pin 25 mA the pin out of the micro-controller is shown in fig 3.10

Pin Description of the AT89C52 micro-controller Pin 1 to Pin 8 (Port 1) input/ouput lines. Pin 9 is the reset pin. Pin 10 to Pin 17 (port 3) control signal lines. Pin 18 and Pin 19 are connectedto the output of the crystal oscillators. Pin 20 is the circuit ground (GND) Pin 29, (PSEM) program store enable is pulse low when the CPU wants the program memory to put an instruction on the data bus. Pin 30 (ALE) address latch enable, is high while the CPU is putting the low addr ess byte on. Pin 31 is the Vcc Pin 32 to Pin 39 (Port 0) address/Data bits Pin 40 Vcc supply 5 volts. 3.5.1 CONFIGURATION OF THE AT89C52 MICRO-CONTROLLER Reset: of power supply to 0V when switched off, as well as rapid increase of power supp ly to its specified output voltage when switched on. The most common time delay used is 10mS. Hence, possib le choice of resistor and capacitor are 10k Crystal Oscillator: For maximum performance, instructions are executed at a rate of one machine instruction per oscillator cycle. A minimum of 12 oscillator cycles are required to execute a machine instruction in 8052, Thus, a 12MHz crystal oscillator (or 11.0592 MHz) is needed to synchronise machi ne cycle operations. At parallel resonance, Crrystal impedance is maximum. Hence it is used to give high impedance in resonant operating to avoid the signal from being grounded. Capacitors are usually used t o provide the maximum crystal impedance. Capacitances of 20pF or 30pF are not uncommon manufacturers' standards to achiev e high impedances in the Fig 3.11: Schematic Diagram of a Configured ATMEL89C52 Microcontroller 3.6 PRINCIPLE OF OPERATION The system operates in a very simple way that is easily understood. When power i s supplied to it, the system initialises, boots, and checks for communication between the transmitter and the receiver. This is done within a few seconds after which the system is ready for data to be enterred. The data to

be transmitted is entered through the keypad in decimal after which the binary encoder encodes it to its b inary form. As soon as the enter key is depressed, the transmitter screen displays a codeword of 8 bit-data which comprises of both the data word to be transmitted and the Hamming bit which serves as the check bit. The system transmits the data to the receiver. Transmission is only observed when a '1' is transmitted as the LED in that position which was initially on is switched off (an LED that is off indicates a 0 bit). During the process of transmitting, an error can be ejected deliberately in any of the bit positions t o see if the system will detect and correct it. The receiver receives the codeword and checks for an error by perfor ming the reverse process of the Hamming (decoding). If a single bit error occurs, the system displays the positi on of the error bit by blinking the LED in that position twice after which, it corrects the error by complementing i ts value. If the error is more than 1 bit, the system will continue blinking and go back to transmission mode after some time. After correcting the error, the system displays the original error through the receiver screen in bin ary form.

CHAPTER 4 HARDWARE CONSTRUCTION AND RESULTS This is a very important aspect of the project, because the workability and pres entation depends on thee actual construction work. Although the entire work involves both hardware and software, the prevalent parrt of the construction work is the emphasis here, which is the former. The source code (so ftware) for the micro-controller is detailed in the appendix. 4.1 Static Testing of Components Under this section, the various tests carried out on the components without powe r supply input are discussed. 4.1.1 Transformer Testing Resistance tests were carried out on the winding of the four transformers used i n this project. Below is a table of the results. Table 4.1: Result of Transformer Test VOLTAGE SIDE TERMINALS 240/12V LOW SECONDARY 5.3 HIGH PRIMARY 1.8K 4.1.2 Bridge Rectifier Testing The following continuity tests were carried out on the rectifier to affirm its p roper functioning. Below is the a of the results. Table 4.2: Bridge Rectifier Test + \ - AC1 AC2 +DC -DC AC1 - HIGH LOW HIGH AC2 HIGH - LOW HIGH +DC HIGH HIGH - HIGH -DC LOW LOW LOW Note: +Symbol means positive lead of Digital Voltmeter (DVM) -Symbol means negative lead of DVM HIGH means high resistance LOW means low resistance

4.1.3 Voltage Regulator (7805) Testing The following continuity tests were carried out on the regulator to affirm its p roper functioning. Below is the table of the result of the test. Table 4.3: Regulator Test + \ - IN GND OUT IN - HIGH HIGH GND LOW - LOW OUT LOW HIGH 4.1.4 Capacitors Testing The capacitors used in the work were tested with a digital voltmeter (DVM) in th e resistance mode. Their charging and discharging times were observed as their resistances increased to n ear infinity. 4.1.5 Transistors Testing Resistance tests were carried out on the terminals and the results obtained to c ertify their good states are shown below. Table 4.4 NPN Transistor Test Result +/- EMITTER BASE COLLECTOR EMITTER - HIGH HIGH BASE LOW - LOW COLLECTOR HIGH HIGH Table 4.5: Static Test of PSU Components S/N Component Procedure Result 1 Transformer (240/ 12V) Connect the wires of the primary and secondary, each pair in turn, to the meter probes. The meter should be in resistance mode or continuity mode Multimeter indicates low resistance values, although the primary resistance value (1.8 higher than that of the secondary (5. 2 Full Wave Bridge Rectifier Connect the meter probes between a pair of adjacent terminals of the four available, and reverse the probe terminals for each pair. In all eight (8) tests will be carried out, two tests for each pair of adjacent terminals For each pair of adjacent terminals

a low resistance value will be got in one direction, while a high resistance value will be got in the reverse direction. No two similar conditions should be obtained in both forward and reverse directions. 3 Electrolytic Capacitor With the meter in range, connect the two terminals of the capacitor to the probes. Check the reading and reverse the probes to test in the reverse direction. In one direction, a low resistance value is got, while in the other, the reverse is the case. 4 Voltage Regulator (7805) With the negative probe of the meter connected to the common (middle) terminal of the device, the positive terminal of the probe is connected first to the input terminal, then the output terminal. The resistance value of the input is usually lower than that of the output. 4.92K was obtained for input while 6. for the output terminal. Table 4.6: Static Tests in the Micro-controller Unit S/N Component Procedure Result 1 AT89C52 IC & LED A simple program is written with an

LED connected to pin 6. In addition, the reset circuit at pin 9 must be connected plus the external crystal oscillator at pins 18 and 19. Vcc and Ground are applied at pins 40 and 20 respectively. The LED lights up indicating that both components are in good working states. 2 Resistors Same as in table 4. 5 Same as in table 4.5 3 Capacitors Same as in table 4. 5 Same as in table 4.5 4 Crystal Oscillator During the testing of AT80C52 in step (1), the meter (in voltage mode) probes should be connected across pins 18 and 19. A voltage reading of 2.5V will be obtained. 4.2 System Integration A number of construction tools and equipment were used for the integration of th e five different units of the entire system. The assembling of the various modules involves: Soldering: It involves heating and Melting of lead to provide electrical connect ions among components on a Vero board. Soldering joints effectively provides both electrical and mecha nical connections of components with pins, wires and strip board. Before this process of soldering, i t is very important that all surfaces to be soldered are clean and completely free of grease and/or oxide fil ms. However, it is important to have an adequate soldering iron of the rating 240V, 60W. Packaging: An appropriate choice of enclosure is important to the packaging of a ny electronic system. The enclosure will not only provide protection for components, but should also be made attractive and add value to the functioning of the components. Therefore, the casing used for this design is made from well polished steel-alloy and persp ex. Furthermore, some equipment which were used in achieving this assembly include: Bread Board: This is used to test the circuit by constructing trial version on t he top side of the board. Lead sucker: This is used in the case of replacement of bad components to suck u

p molten solder so as to enhance ease of removal. Digital Multimeter: The meter serves several purposes such as measuring capacita nce, resistance of components, identifying of transistor terminals, and more importantly, for stati c testing of the components. Wire connectors: These thin cables enable electrical linking components and subcircuits together. Solder: The electronic components are joined or soldered together firmly to the Vero board with a fluxcore solder of lead (Pb). Vero board: This board allows permanent prototype. It is called pre-etched, havi ng all its traces on the other side with pre-drilled paths for ICs and other components. 4.2.1 Mounting and Connection of Components All connections made between components were either made via connecting wires or directly with solder. The following steps were very useful in achieving good connection of components used in the project. Soldering Iron was well tinned before commencing soldering. Good care was taken to avoid overheating of components. Good 60/40 tins man solder was used to make joints quickly with minimum heat. Solder sucker/extractor was used to remove improper and unintended joints. A DVM was used for continuity, resistance, isolation test, voltage and current m easurements. 4.3 Testing of System Before the system integration, each module was first tested separately and then sequentially each time a new unit is connected. Finally, the integrated work was tested before and after pack aging. This indeed, ensures ease of location of dry and weak solder joints and affirms the good working condition of all the components off and on the board. After the various modules have been integrated, the system was tes ted to see how it worked by powering it. 4.4 How To Detect The Error The data to be transmitted is entered through the keypad unit in its decimal for m which is converted to its binary value by the 74LS147 encoder. This four-bit binary value is transmitted t o the micro-controller which then encodes it to an 8-bit code word by adding extra four bits known as the par ity bit to ensure that the number of 1's in the codeword is even. If an error now occurs, the number of 1's in the codeword changes to odd. The encoding process is done in a special way by finding the parity bit and placing them in a specific position. From Hamming theory, the parity bit position are the positions that are powers of 2 i n the codeword. That is, 20, 21, 22, 23, etc. To find a Hamming bit (parity bit), number the bit positions in decimal and place the binary form of the data to be sent in the remaining position after identifying the parity position as explained above, then, exclusively 'OR' all the bit positions of the data work that are set. The result can now be placed in the parity position as illustrated below using the decimal number 5. 5 0101 data word to be sent. 8 7 6 5 4 3 2 1 bit positions P 0 1 0 P 1 P P code word

From the data codeword above, the bit positions that are set are 6(0110), 3(0011 ) hence, exclusively ORing this bit value implies 6 0 1 1 0 3 - 0 0 1 1 + 0 1 0 1 Therefore, the codeword above becomes 0 0 1 0 1 1 0 1 code word If an error occurs in any bit position of the codeword above, say position 2, th e number of 1's changes to odd and this position can be identified by exclusively ORing the parity bit value of the error word with the bit position of the data word that are set as illustrated below. 8 7 6 5 4 3 2 1 - bit positions 0 0 1 0 1 1 0 1 - correct code word 8 7 6 5 4 3 2 1 - bit position 0 0 1 0 1 1 1 1 - error code word From the error code word, the parity bit value and the bit position value of the data word that are set are 0111, 6(0110) and 3(0011) respectively. These are exclusively ORed together to get the error bit position. Hence: 0 1 1 1 0 1 1 0 0 0 1 1 + 0 0 1 0 2 4.5 Performance Evaluation The results obtained during the testing and after necessary troubleshooting were satisfactory. The system was able to detect and correct a single bit error in data. 4.6 Problems Encountered A number of problems were encountered during the execution of this project. Thes e include: Unavailability of appropriate component values Some of the distinct components got burnt while soldering and some got damaged d uring construction and had to be replaced as a learning process. The assembly code programming took time and serious reasoning before finally arr iving at the current result. 4.7 Solution Proffered Approximate values for components were used. More lectures had to be attended for assembly language programming. CHAPTER 5 CONCLUSION AND RECOMMENDATION 5.1 CONCLUSION The design and construction of the data transmission error control system using a micro-controller was indeed a great one. The end of the whole process was to see that the hardware an d software implementation are working as expected. This project has offered a great deal of insight into the f ields of communication and control engineering. The ability to detect and correct an error in data transmis sion was realized. Thus, the main objectives were achieved. The use of data transmission error control system using a micro-controller to de tect and correct an error in communication is indeed an important improvement over the common retransmission method which offers high cost and is time consuming. Its unique feature of correcting the error rather th

an just detecting it is an added advantage. With virtually zero adverse effect on the ecological state of the env ironment, this work is an important development in modern engineering projects that can be applied in real life. 5.2 RECOMMENDATION The data transmission error control system is hereby recommended for any technol ogical and communication industries, offices or homes to wipe out the cost and time effects of retransmis sion of data whenever an error is detected. This error control system is being perceived by the communication engi neers and the world at large as a necessary and vital technological upgrade in communication. Conclusively, further work and improvements are highly recommended to curb some of the stated limitation. A delve into detecting more than two bit errors and correcting more than one bit errors could be a promising area as it can totally wipe away retransmission. The use of high level languages as well as the addition of complex circuitry can also improve the design. REFERENCES APPENDIX MICROCONTROLLER PROGRAM (ASSEMBLY LANGUAGE) Software for the transmitting section org 00h initialization: mov p1,#00h mov p2,#00h mov p3,#00h mov p0,#00h mov A,#00h mov R1,#00h mov R2,#00h mov R3,#00h mov R4,#00h mov R5,#00h mov R6,#00h mov R7,#00h CALL BOOTING SM: CALL SIMULATION JNB P3.0, CHECKCOM JMP SM SIMULATION: NOP mov p1,#0fh JNB P3.0, CHECKCOM call DELAY23 JNB P3.0, CHECKCOM MOV P1,#78H CALL DELAY23 MOV P1,#00H RET DELAY23 : MOV R1,#250 MOV R2,#200 LAY23 : DJNZ R1,LAY23 JNB P3.0, CHECKCOM DJNZ R2,LAY23 RET BOOTING: SETB P1.0 CALL DELAY2 CLR P1.0

SETB P1.1 CALL DELAY2 CLR P1.1 SETB P1.2 CALL DELAY2 CLR P1.2 SETB P1.3 CALL DELAY2 CLR P1.3 SETB P1.4 CALL DELAY2 CLR P1.4 SETB P1.5 CALL DELAY2 CLR P1.5 SETB P1.6 CALL DELAY2 CLR P1.6 SETB P1.7 CALL DELAY2 MOV P1,#0FFH CALL DELAY2 MOV P1,#00H RET DELAY2 : MOV R1,#250 MOV R2,#200 LAY2 : DJNZ R1,LAY2 DJNZ R2,LAY2 RET CHECKCOM : NOP MOV P2,#0FFH SETB P3.1 JB P2.0,CP1 JMP CHECKCOM_NOK CP1 : JB P2.1,CP2 JMP CHECKCOM_NOK CP2 : JB P2.2,CP3 JMP CHECKCOM_NOK CP3 : JB P2.1,CP4 JMP CHECKCOM_NOK CP4 : JB P2.1,CP5 JMP CHECKCOM_NOK CP5 : JB P2.1,CP5 JMP CHECKCOM_NOK CP6 : JB P2.1,CP6 JMP CHECKCOM_NOK CP7 : JB P2.1,CHECKCOM2 JMP CHECKCOM_NOK CHECKCOM_NOK : MOV P1,#0FFH CALL DELAY4 MOV P1,#00H JMP CHECKCOM CHECKCOM2: CLR P3.1 SETB P3.2 JNB P2.0,CP11 JMP CHECKCOM_NOK CP11 : JNB P2.1,CP21

JMP CHECKCOM_NOK CP21 : JNB P2.2,CP31 JMP CHECKCOM_NOK CP31 : JNB P2.1,CP41 JMP CHECKCOM_NOK CP41 : JNB P2.1,CP51 JMP CHECKCOM_NOK CP51 : JNB P2.1,CP61 JMP CHECKCOM_NOK CP61 : JNB P2.1,CP71 JMP CHECKCOM_NOK CP71 : JNB P2.1,CHECKCOM_OK JMP CHECKCOM_NOK DELAY4 : MOV R1,#200 MOV R2,#200 LAY4 : DJNZ R1,LAY4 DJNZ R2,LAY4 RET DELAY4B : MOV R1,#200 MOV R2,#50 LAY4B : DJNZ R1,LAY4B DJNZ R2,LAY4B RET CHECKCOM_OK : CLR P3.1 CLR P3.2 SETb P3.3 MOV P1,#0FFH CALL DELAY4B MOV P1,#00H CALL DELAY4 MOV P1,#0FFH CALL DELAY4B MOV P1,#00H CALL DELAY4 MOV P1,#0FFH CALL DELAY4B MOV P1,#00H CALL DELAY4B CLR P3.3 JMP ENTER ENTER : MOV P0,#0FFH NOP MOV A,#0H START : JNB P3.0, TRANSMIT NOP JB P0.0,PORT1 MOV A,#1H CALL DISPLAY1 JMP START TRANSMIT : SETB P3.1 SETB P3.2 CALL DELAY2 MOV A,R7 MOV P2,A CALL DELAY2 CLR P3.1 CLR P3.2 CALL ENCODER

CALL DISPLAY6 CALL CLEARING CALL DISPLAY6 MOV P1,#00H JMP START PORT1 : NOP JB P0.1,PORT2 MOV A,#1H CALL DISPLAY1 JMP START PORT2 : NOP JB P0.1,PORT2 MOV A,#1H CALL DISPLAY1 JMP START PORT3 : NOP JB P0.1,PORT2 MOV A,#1H CALL DISPLAY1 JMP START PORT4 : NOP JB P0.1,PORT2 MOV A,#1H CALL DISPLAY1 JMP START PORT5 : NOP JB P0.1,PORT2 MOV A,#1H CALL DISPLAY1 JMP START PORT6 : NOP JB P0.1,PORT2 MOV A,#1H CALL DISPLAY1 JMP START PORT7 : NOP JB P0.1,PORT2 MOV A,#1H CALL DISPLAY1 JMP START DISPLAY1 : CALL EVALUATOR MOV P1,R7 CALL DELAYD RET DELAYD : MOV R1,#100 MOV R2,#100 LAYD: DJNZ R1,LAYD DJNZ R2,LAYD RET EVALUATOR : CJNE A,#1H, E2 MOV R7,#0001B JMP RET2 E2 : CJNE A,#2H,E3 MOV R7,#0010B JMP RET2 E3 : CJNE A,#3H,E4 MOV R7,#0011B

JMP RET2 E4 : CJNE A,#4H,E5 MOV R7,#0100B JMP RET2 E5 : CJNE A,#5H,E6 MOV R7,#0101B JMP RET2 E6 : CJNE A,#6H,E7 MOV R7,#0110B JMP RET2 E7 : CJNE A,#7H,E8 MOV R7,#0111B JMP RET2 E8 : CJNE A,#8H,E9 MOV R7,#1000B JMP RET2 E9 : CJNE A,#9H,E0 MOV R7,#1001B JMP RET2 E0 : CJNE A,#0H,RET3 MOV R7,#0000B JMP RET2 RET3 : MOV A,#0H RET2 : NOP RET ENCODER : CJNE A,#1H, EN2 MOV R6,#00000111B MOV B,R6 JMP EN2 MOV MOV JMP EN3 MOV MOV JMP EN4 MOV MOV JMP EN5 MOV MOV JMP EN6 MOV MOV JMP EN7 MOV MOV JMP EN8 MOV MOV JMP ENDENCODER : CJNE A,#2H, R6,#00011001B B,R6 ENDENCODER : CJNE A,#3H, R6,#00011110B B,R6 ENDENCODER : CJNE A,#4H, R6,#00101010B B,R6 ENDENCODER : CJNE A,#5H, R6,#00101101B B,R6 ENDENCODER : CJNE A,#6H, R6,#00110011B B,R6 ENDENCODER EN3

EN4

EN5

EN6

EN7

: CJNE A,#7H, EN8 R6,#00110100B B,R6 ENDENCODER : CJNE A,#8H, EN9 R6,#11000000B B,R6 ENDENCODER

EN9 : CJNE A,#9H, EN0 MOV R6,#01001100B MOV B,R6 JMP ENDENCODER EN0 : CJNE A,#0H, ENDENCODER MOV R6,#00000000B MOV B,R6 JMP ENDENCODER ENDENCODER: NOP RET DISPLAY6 : MOV R5,B MOV P1,R5 RET CLEARING : CLR P1.0 CALL DELAYD2 CLR P1.1 CALL DELAYD2 CLR P1.2 CALL DELAYD2 CLR P1.3 CALL DELAYD2 CLR P1.4 CALL DELAYD2 CLR P1.5 CALL DELAYD2 CLR P1.6 CALL DELAYD2 CLR P1.7 RET DELAYD2 : MOV R1,#100 MOV R2,#200 LAYD2: DJNZ R1,LAYD2 DJNZ R2,LAYD2 RET END Software for the Receiving section org 00h initialization: mov p1,#00h mov p2,#00h mov p3,#00h mov p0,#00h mov A,#00h mov R1,#00h mov R2,#00h mov R3,#00h mov R4,#00h mov R5,#00h mov R6,#00h mov R7,#00h CALL BOOTING JMP SM BOOTING: SETB P1.0 CALL DELAY2 CLR P1.0 SETB P1.1 CALL DELAY2 CLR P1.1 SETB P1.2

CALL DELAY2 CLR P1.2 SETB P1.3 CALL DELAY2 CLR P1.3 SETB P1.4 CALL DELAY2 CLR P1.4 SETB P1.5 CALL DELAY2 CLR P1.5 SETB P1.6 CALL DELAY2 CLR P1.6 SETB P1.7 CALL DELAY2 MOV P1,#0FFH CALL DELAY2 MOV P1,#00H RET DELAY2 : MOV R1,#250 MOV R2,#200 LAY2 : DJNZ R1,LAY2 DJNZ R2,LAY2 RET SM : NOP MOV P3,#0FFH SMA: JB P3.1,POSITIVE_CHECK SMB: JB P3.2,NEGETIVE_CHECK JMP SMA POSITIVE_CHECK:MOV P2,#0FFH JMP SMB NEGETIVE_CHECK :MOV P2,#00H COMCHECK:JB P3.3,COM_OK JMP SMA COM_OK : NOP MOV P1,#0FFH CALL DELAY4B MOV P1,#00H CALL DELAY4 MOV P1,#0FFH CALL DELAY4B MOV P1,#00H CALL DELAY4 MOV P1,#0FFH CALL DELAY4B MOV P1,#00H CALL DELAY4B JMP CH_TRANS DELAY4 : MOV R1,#200 MOV R2,#200 LAY4 : DJNZ R1,LAY4 DJNZ R2,LAY4 RET DELAY4B : MOV R1,#200 MOV R2,#50 LAY4B : DJNZ R1,LAY4B DJNZ R2,LAY4B

RET CH_TRANS: JB P3.1,CH_T2 JMP CH_TRANS CH_T2: JB P3.2,RECIEVING JMP CH_TRANS RECIEVING:MOV P2,#0FFH MOV A,P2 JNB P3.1,RE2 JMP RECIEVING RE2: JNB P3.2,SHOWDISPLAY JMP RECIEVING SHOWDISPLAY : CALL DECODER CALL DISPLAY_ERROR_CODE CALL DISPLAY_CORRECT_DATA JMP CH_TRANS DECODER : CJNE A,#1H, EN2 MOV R6,#00000111B JMP ENDENCODER EN2 : CJNE A,#2H, EN3 MOV R6,#00011001B JMP ENDENCODER EN3 : CJNE A,#3H, EN4 MOV R6,#00011110B JMP ENDENCODER EN4 : CJNE A,#4H, EN5 MOV R6,#00101010B JMP ENDENCODER EN5 : CJNE A,#5H, EN6 MOV R6,#00101101B JMP ENDENCODER EN6 : CJNE A,#6H, EN7 MOV R6,#00110011B JMP ENDENCODER EN7 : CJNE A,#7H, EN8 MOV R6,#00110100B JMP ENDENCODER EN8 : CJNE A,#8H, EN9 MOV R6,#11000000B JMP ENDENCODER EN9 : CJNE A,#9H, EN0 MOV R6,#01001100B JMP ENDENCODER EN0 : CJNE A,#0H, ENDENCODER MOV R6,#00000000B JMP ENDENCODER ENDENCODER: NOP RET DISPLAY_CORRECT_DATA : MOV P1,R6 CALL DELAY5 RET DELAY5 : MOV R1,#200 MOV R2,#250 LAY5 : DJNZ R1,LAY5 DJNZ R2,LAY5 RET DISPLAY_ERROR_CODE : CALL XOR_SYSTEM MOV B,R5

MOV R4,B CJNE R4,#0H,ED1 MOV P1,R6 ED1 :CJNE R4,#1H, ERROR_DATA MOV P1,R6 ERROR_DATA : MOV P1,#0H RET XOR_SYSTEM : MOV R5,P2 MOV B,R5 xRL A,R5 CJNE A,#00000001B,X2 MOV R5,#1H MOV P2,#00000001B JMP XEND X2 : CJNE A,#00000010B,X3 MOV R5,#2H MOV P2,#00000010B JMP XEND X3 : CJNE A,#00000100B,X4 MOV R5,#3H MOV P2,#00000100B JMP XEND X4 : CJNE A,#00001000B,X5 MOV R5,#4H MOV P2,#00001000B JMP XEND X5 : CJNE A,#00010000B,X6 MOV R5,#5H MOV P2,#00010000B JMP XEND X6 : CJNE A,#00100000B,X7 MOV R5,#6H MOV P2,#00100000B JMP XEND X7 : CJNE A,#01000000B,X8 MOV R5,#7H MOV P2,#01000000B JMP XEND X8 : CJNE A,#10000000B,X9 MOV R5,#8H MOV P2,#10000000B JMP XEND X9 : NOP MOV P2,#11111111B JMP XEND XEND : NOP RET END