DESIGN OF SEQUENCE DETECTOR USING MEALY AND MOORE TYPE STATE MACHINES.

(a)Mealy finite state machine:

Aim: To design a 1011 sequence detector with a mealy type finite state machine using verilog. Code:
module fsmmealy1011( clk,rst,inp,outp); input clk,rst,inp; output outp; reg [1:0]state; reg outp; always@(posedge clk or posedge rst) if(rst) begin state=2'b00; outp=0; end else begin case(state) 2'b00:if(inp) begin state=2'b01; outp=0; end else begin

state=2'b00; outp=0; end 2'b01:if(inp) begin state=2'b01; outp=0; end else begin state=2'b10; outp=0; end 2'b10:if(inp) begin state=2'b11; outp=0; end else begin state=2'b00; outp=0; end 2'b11:if(inp) begin state=2'b01; outp=1;

end else begin state=2'b10; outp=0; end default: begin state=2'b00; outp=0; end endcase end endmodule

Test bench:
module fsmsd_tb; reg clk,rst,inp; wire outp; reg [15:0] sequences; integer i; fsmmealy1011 test(clk,rst,inp,outp); initial begin clk=0; rst=1; i=0; sequences=16'b1010101110111001;

#5 rst=0; while(i<=15) begin inp=sequences[i]; #2 clk=1;#2 clk=0;i=i+1; end end endmodule

Result: A 1011 sequence detector using mealy type state machine has been designed and verified
using verilog.

Signal flow:

(b)Moore finite state machine:

Aim: To design a 1011 sequence detector with a moore type finite state machine using verilog. Code:
module fsmmoore1011( clk,rst,inp,outp); input clk,rst,inp; output outp; reg [2:0]state; reg outp; always@(posedge clk or posedge rst) if(rst) begin state=2'b000; outp=0; end else begin case(state) 3'b000:if(inp) begin state=3'b001; outp=0; end else begin state=3'b000; outp=0; end

3'b001:if(inp) begin state=3'b001; outp=0; end else begin state=3'b010; outp=0; end 3'b010:if(inp) begin state=3'b011; outp=0; end else begin state=3'b000; outp=0; end 3'b011:if(inp) begin state=3'b100; outp=0; end else begin

state=3'b010; outp=0; end 3'b100:if(inp) begin state=3'b001; outp=1; end else begin state=3'b011; outp=1; end default: begin state=3'b000; outp=0; end endcase end endmodule

Test bench:
module fsmmoore_tb; reg clk,rst,inp; wire outp; reg [15:0] sequences; integer i;

fsmmoore1011 test(clk,rst,inp,outp); initial begin clk=0; rst=1; i=0; sequences=16'b1010101110111001; #5 rst=0; while(i<=15) begin inp=sequences[i]; #2 clk=1;#2 clk=0;i=i+1; end end endmodule

Result: A 1011 sequence detector using moore type state machine has been designed and verified
using verilog.

Signal flow:

DESIGN OF SYNCHRONOUS COUNTERS: (a)Design of a synchronous up counter:

Aim:To design a 4-bit synchronous up counter using verilog. Code:
module upcounter(clk,reset,Y); input clk,reset; output reg [3:0]Y; initial Y=4'b0000; always@(posedge clk) begin if(!reset) Y<=Y+1; else Y<=0; end endmodule

Test bench:
module tb; reg clk,reset; wire [3:0]Y; upcounter pav(clk,reset,Y); initial begin {clk,reset}=0; end

always #50 {clk}=~{clk}; always #1500 {reset}={reset}+1; endmodule

Result:A 4-bit synchronous up counter has been designed and verified using verilog. Signal Flow:

(b)Design of a synchronous down counter:

Aim:To design a 4-bit synchronous down counter using verilog. Code:

module downcounter(clk,reset,Y); input clk,reset; output reg [3:0]Y; initial Y=4'b1111; always@(posedge clk) begin if(!reset) Y<=Y-1; else Y<=0; end endmodule module tb; reg clk,reset; wire [3:0]Y; downcounter pav(clk,reset,Y); initial begin {clk,reset}=0; end always #50 {clk}=~{clk}; always #1500 {reset}={reset}+1;

endmodule

Result:A 4-bit synchronous down counter has been designed and verified using verilog. Signal Flow:

PROGRAM TO REALIZE A 4-VARIABLE FUNCTION: (a)Sum of products form:

Aim:To realize the Boolean function (0,2,8,9,11,12,13,14) using verilog. Code:
module realizationSOP(X,Y); input [3:0]X; output Y; reg Y; always@(X) begin if(X==0||X==2||X==8||X==9||X==11||X==12||X==13||X==14) Y=1; else Y=0; end endmodule

Test bench:
module realizationSOP_tb; reg [3:0]X; wire Y; realizationSOP tb(X,Y); initial X=4'b0000; always begin X=X+1;

#50; end endmodule

Result: The given 4 variable SOP boolean function has been realized using verilog. Signal Flow:

(b)Product of sum form:

Aim: To realize the boolen function (0,1,3,5,7,11,15) using verilog. Code:

module realizationPOS(X,Y); input [3:0]X; output Y; reg Y; always@(X) begin if(X==0||X==1||X==3||X==5||X==7||X==11||X==15) Y=0; else Y=1; end endmodule module realizationPOS_tb; reg [3:0]X; wire Y;

Test bench:
realizationPOS tb(X,Y); initial X=4'b0000; always begin X=X+1; #100; end endmodule

Result: The given 4 variable POS boolean function has been realized using verilog. Signal Flow:

PROGRAM TO DESIGN AN 8X1 MULTIPLEXER USING TWO 4X1 MULTIPLEXERS:

Aim:To design an 8X1 MUX using two 4X1 multiplexers using verilog. Code:
module MUX4X1(I,Y,E,S); input [3:0]I; input E; input [1:0]S; output reg Y; always@(I or E or S) begin if(E) if(S[1]) if(S[0]) Y=I[3]; else Y=I[2]; else if(S[0]) Y=I[1]; else Y=I[0]; else Y=0; end endmodule

module MUX8X1(I,S,Y); input [7:0]I;

input [2:0]S; output Y; wire Y1,Y2; MUX4X1 a1(I[3:0],Y1,~S[2],S[1:0]); MUX4X1 a2(I[7:4],Y2,S[2],S[1:0]); or (Y,Y1,Y2); endmodule

Test bench:
module MUX8X1_tb; reg [7:0]I; reg [2:0]S; wire Y; MUX8X1 tb(I,S,Y); initial {I,S}=0; always begin {I,S}={I,S}+1; #20; end endmodule

Result:An 8X1 multiplexer has been designed using two 4X1 multiplexers and verified using
verilog.

Signal Flow:

PROGRAM TO DESIGN AN 8X3 PRIORITY ENCODER:

Aim:To design an 8X3 priority encoder using verilog. Code:

module priorityencoder8X3(X,Y,Z); input [7:0]X; output reg [2:0]Y; output reg Z; always@(X) begin Z=1; casex(X) 8'b1xxxxxxx:Y=3'b111; 8'b01xxxxxx:Y=3'b110; 8'b001xxxxx:Y=3'b101; 8'b0001xxxx:Y=3'b100; 8'b00001xxx:Y=3'b011; 8'b000001xx:Y=3'b010; 8'b0000001x:Y=3'b001; 8'b00000001:Y=3'b000; default: begin Z=0; Y=3'bxxx; end endcase end endmodule

Test bench:

module pen8X3_tb; reg [7:0]X; wire [2:0]Y; wire Z; priorityencoder8X3 tb(X,Y,Z); initial X=0; always begin X=X+1; #10; end endmodule

Result:An 8X3 priority encoder has been designed and verified using verilog. Signal Flow:

LOGIC SYNTHESIS OF BASIC GATES

AIM:To perform logic synthesis of basic logic gates

RTL schematic:

Technology schematic:

Critical path:

Netlist: (edif gates (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timestamp 2010 10 30 07 49 56) (program "LeonardoSpectrum Level 3" (version "2010a.7")) (author "Mentor Graphics"))) (external PRIMITIVES (edifLevel 0) (technology (numberDefinition ))) (external ami05_typ (edifLevel 0) (technology (numberDefinition )) (cell nor02ii (cellType GENERIC) (view NETLIST (viewType NETLIST) (interface

(port A0 (direction INPUT)) (port A1 (direction INPUT)) (port Y (direction OUTPUT))))) (cell and02 (cellType GENERIC) (view NETLIST (viewType NETLIST) (interface (port A0 (direction INPUT)) (port A1 (direction INPUT)) (port Y (direction OUTPUT))))) (cell or02 (cellType GENERIC) (view NETLIST (viewType NETLIST) (interface (port A0 (direction INPUT)) (port A1 (direction INPUT)) (port Y (direction OUTPUT))))) (cell inv02 (cellType GENERIC) (view NETLIST (viewType NETLIST) (interface (port A (direction INPUT)) (port Y (direction OUTPUT)))))) (library ravichandra_lib (edifLevel 0) (technology (numberDefinition )) (cell gates (cellType GENERIC) (view INTERFACE (viewType NETLIST) (interface (port a (direction INPUT))

(port b (direction INPUT)) (port y1 (direction OUTPUT)) (port y2 (direction OUTPUT)) (port y3 (direction OUTPUT)) (port y4 (direction OUTPUT))) (contents (instance ix9 (viewRef NETLIST (cellRef nor02ii (libraryRef ami05_typ )))) (instance ix5 (viewRef NETLIST (cellRef and02 (libraryRef ami05_typ )))) (instance ix3 (viewRef NETLIST (cellRef or02 (libraryRef ami05_typ )))) (instance ix117 (viewRef NETLIST (cellRef inv02 (libraryRef ami05_typ )))) (net a (joined (portRef a ) (portRef A1 (instanceRef ix5 )) (portRef A0 (instanceRef ix3 )) (portRef A (instanceRef ix117 )))) (net b (joined (portRef b ) (portRef A0 (instanceRef ix5 )) (portRef A1 (instanceRef ix3 )))) (net y1 (joined (portRef y1 ) (portRef Y (instanceRef ix5 )) (portRef A0 (instanceRef ix9 )))) (net y2

(joined (portRef y2 ) (portRef Y (instanceRef ix3 )) (portRef A1 (instanceRef ix9 )))) (net y3 (joined (portRef y3 ) (portRef Y (instanceRef ix9 )))) (net y4 (joined (portRef y4 ) (portRef Y (instanceRef ix117 )))))))) (design gates (cellRef gates (libraryRef ravichandra_lib )))

Area report: *******************************************************

Cell: gates View: INTERFACE Library: ravichandra_lib

******************************************************* Cell PadInC PadOut buf02 inv02 Library References ami05_typ ami05_typ ami05_typ ami05_typ 2x 4x 3x 1x 1x 2x 1 1 1 1 3 gates 1 gates 1 gates 2 gates Total Area

nand02_2x ami05_typ nor02ii ami05_typ

Number of ports : Number of nets : Number of instances :

6 15 13 0

Number of references to this view :

Total accumulated area : Number of gates : 7 13

Number of accumulated instances : NO wire table is found

PROGRAM TO GENERATE RECTANGULAR WAVEFORM

AIM: To generate rectangular wave form. VERILOG CODE:

module rectangle; parameter TON=10,TOFF=5; reg clk; initial clk=1'b0; always begin #TOFF clk=1'b0; #TON clk=1'b1; end endmodule

WAVEFORM

RESULT: Rectangular wave is generated using verilog hdl.

PROGRAM TO GENERATE SQUARE WAVEFORM

AIM:To generate square wave form. VERILOG CODE:

module square; parameter TON=5,TOFF=5; reg clk; initial clk=1'b0; always begin #TOFF clk=1'b0; #TON clk=1'b1; end endmodule

WAVEFORM:

RESULT:
Square waveform is generated using verilog hdl.