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CS623

CS623 CAD for VLSI

The following slides are adopted from UTD 3325 Slides

Lecture 30 : Delay Components in a Circuit


Shankar Balachandran Dept. of Computer Science and Engineering Indian Institute of Technology Madras shankar@cse.iitm.ac.in
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Combinational Circuit Timing Parameters

Timing parameters (contd)


Vin Vmax 0.5Vmax 0 Vout Vmax 0.9Vmax 0.5Vmax 0.1Vmax tpLH tpHL time

Rise Time (tr), the time required for a signal to transition from 10% of its maximum value to 90% of its maximum value. Fall Time (tf), the time required for a signal to transition from 90% of its maximum value to 10% of its maximum value. Propagation Delay (tpLH, tpHL), the delay measured from the time the input is at 50% of its full swing value to the time the output reaches its 50% value.
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0 tr tf

time

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Example: Gate delay


Determine the worst case propagation delay through these circuits.
2 ns 4 ns 2 gd 5 gd

Timing Analysis of Combinational Circuits

Using gates with finite propagation delays, tpLH and tpHL instead of zero gate delays used in functional analysis.
Gate tpLH tpHL INV 3 ns 2 ns XOR 5 ns 4 ns

t p = 2 + 4 = 6 ns

3 gd

3 gd 2 gd

6 gd

t p = max {( 2 + 5 ) , ( 3 + 5 ) , ( 3 )} = 8 gd

5 gd 3 gd
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t p = max {( 2 + 5 ) , ( 3 + 5 ) , ( 3 ) , ( 6 + 3 )} = 9 gd

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01 Transition on Vin Vin V1 V2 V3 Vout
t=0 4 2 3 2 5 8 ns

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Setup and Hold Times


Gate INV XOR tpLH 3 ns 5 ns tpHL 2 ns 4 ns

Setup time, tsu, is the time period prior to the clock becoming active (edge or level) during which the flip-flop inputs must remain stable. Hold time, th, is the time after the clock becomes inactive during which the flip-flop inputs must remain stable. Setup time and hold time define a window of time during which the flip-flop inputs cannot change quiescent interval.

Vin V1 V2 V3
3 2 3 4 5

10 Transition on Vin

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9 ns
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Vout

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Propagation Delay
Propagation delay, tpHL and tpLH , has the same meaning as in combinational circuit beware propagation delays usually will not be equal for all input to output pairs. There can be two propagation delays: tC-Q (clockQ delay) and tD-Q (dataQ delay). For a level or pulse triggered latch:
Data input should remain stable till the clock becomes inactive. Clock should remain active till the input change is propagated to Q output. That is, active period of the clock,
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Latch & Flip-flop Timing Parameters

tw > max {tpLH, tpHL}


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Latch and Flip-flop Timings


CLK

Characterizing Timing
Setup time, hold time Propagation delays
tD-Q

th tsu tC-Q
Q

Flip-flop tsu th tsu th Latch


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tD-C tC-Q Flip-Flop

tD-C tC-Q Latch

Q
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tC-Q
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tC-Q tD-Q

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More Precise FF Setup & Hold Times


CLK t D Q t
350 300 Minimum Data-Output

Sequential Circuit Timing


Once the functionality of a sequential network is designed, its timing parameters must be determined. Timing problems can be very subtle because timing parameters can vary with device age and other operating conditions.

Clk-Output [ps]

250 200 150 100

Setup

Hold

Sampling Window
50 0 -200 -150 -100 -50 0 50 100 150 200

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Data-Clk [ps]

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Timing Parameters
Global setup time (Tsu) Global hold time (Th) Maximum clock frequency Clock skew.
These parameters are derived using the circuit (known) delays described below.
tio delay from input of IFL to output of OFL tif delay from circuit inputs of flip-flop inputs tfo delay from flip-flop outputs to circuit outputs tff delay from flip-flop outputs to flip-flop inputs tc-q clock to Q propagation delay of flip-flops tsu setup time of flip-flops
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Global Setup and Hold Times


Changes that occur at inputs can be delayed by as much as maximum tif by the time they reach the flip-flop inputs. Hence, we want to setup circuit inputs relative to clock edge appearing at the flip-flops. Th Tsu
tc th tif tsu tif
CLK (at clock source) CK (at FF clock input) X (at sequential circuit input)

D (at FF input)

Tsu = tsumax + tifmax tcmin


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th hold time of flip-flops tc clock delay; time required for clock to reach all flip-flops
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Similarly, hold time of the circuit inputs relative to the system clock at the source is given by Th = thmax tif min + tcmax
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Clock Frequency
The limiting factor on the clocking rate is the propagation delay through the IFL block:

Clock Frequency
The limiting factor on the clocking rate is the propagation delay through the combinational logic block (input forming logic):

Dj

Qj

Comb. logic

CKj

Di
CKi CLK tff

Qi

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Changes on the Qs must propagate through the IFL before they can affect the next state

Changes on the Qs must propagate through the combinational logic before they can affect the next state
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Maximum Clock Frequency


CKi Qi

Maximum Clock Frequency


Dj Qj

CKi Qi

tC-Q
Dj

tff

tsu

Comb. logic

CKj

Di
CKi

Qi

tC-Q
Dj

tff

tsu

Tck (=Tclk)
Edge Triggering

CLK

tff

Tck (=Tclk)
Edge Triggering

For an edge-triggered circuit: minimum clock period is,

For an edge-triggered circuit: minimum clock period is,

Tclk tC Q ,max + t ff ,max + tsu,max


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Tclk t C Qmax + t ffmax + t sumax


Maximum Clock Frequency:

Maximum Clock Frequency:


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f clk

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1 Tclk

f clk
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1 Tclk

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Timing Violations
Tclk tC Qmax + t f f max + tsumax
The clock period (Tclk) has a lower bound of tff.max . If the clock period is equal to (tff.max + tC-Q.max) then the flip-flop state changes can violate setup times. Remedy :

Clock Skew
The previous discussion assumes that clock signals arrive at all flip-flops simultaneously - this is not a good assumption since it is not true in practice. Because of different wire lengths over which the clock signals travel and the load at the destination, there is a slight difference in clock arrival times at different flip-flop inputs. Clock skew, tskew, is the difference in time between triggering edges seen at different flip-flops. Clock skew affects minimum Tclk.
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Use faster flip-flops (decrease tC-Q )


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Use a slower clock (increase clock period, Tclk)

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Use faster gates (decrease tff )

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Max. Clock Frequency with Skew


CKi CKj Qj

Max. Clock Frequency with Skew


tskew tp tff tsu
CLK tff

Dj

Qj

CKi CKj
tskew

tskew tC-Q tff tsu

Comb. logic

CKj

Di
CKi

Qi

Qj

Di

Di

Tck (=Tclk)

Therefore, for an edge-triggered circuit with clock skew,

Therefore, for an edge-triggered circuit with clock skew,

Tck (=Tclk)

Tclk tskew,max + t p ,max + t ff ,max + t su ,max


Clock skew is a significant factor in determining the speed of high-performance sequential circuits. The larger the skew, the slower the circuit will operate.
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Tclk t skewmax + tC Qmax + t ffmax + tsumax


Clock skew is a significant factor in determining the speed of high-performance synchronous circuits. The larger the skew, the slower the circuit will operate.

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Maximum Allowable Clock Skew


Can any skew be countered simply by slowing down the clock? No
If the skew is too large, state change caused by an edge at FFi will change the state of FFj erroneously when the clock edge finally gets there!
Dj Qj

Timing Analysis Example


For the circuit given below determine all the sequential circuit timing parameters.

CKi

tskew tC-Q th

tC Q + t ff t skew + th

Comb. logic

CKj

Di
CKi

Qi

tskew CKj

Qi

CLK

tff

tff
Dj
state of Dj before clock becomes active state of Dj after clock becomes active

In the worst case, if tff = 0 then,

tskewallowed = tC Qmin thmax


flip-flops propagation delay must be greater than its hold time.

For a D flip-flop use: tsu = 2ns, th = 15ns and tC-Q = 20ns For a NAND gate use: tp,max = 10ns and tp,min = 3ns
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tif ,max = 3t p ,max,nand = 30ns tif ,min = 2t p ,min,nand = 6ns t ff ,max = 2t p ,max,nand = 20ns t ff ,min = 2t p ,min,nand = 6ns tc ,max = 2t p ,max,nand = 20ns tc ,min = 2t p ,min,nand = 6ns
Tsu = t su ,max + tif ,max tc ,min = 2 + 30 6 = 26ns Th = th ,max tif ,min + tc ,max = 20 + 15 6 = 29ns Tclk tC Q ,max + t ff ,max + tsu ,max = 20 + 20 + 2 = 42ns f clk ,max = 1/ 42ns = 23.8MHz tskew,max = tC Q ,min + t ff ,min th ,max = 20 + 6 15 = 11ns
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1-Phase Clock w/ Level Triggering

For a D flip-flop use: tsu = 2ns, th = 15ns, tC-Q = 20ns For a NAND gate use: tp,max = 10ns, tp,min = 3ns

Positive clock skew

Latch must be open for less than the shortest combinational logic delay but more than the worst setup time.

t w td q min + tlmin thmax t skewmax t skewmax


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and

tlmin t w td q min + thmax + t skewmax


d q min

Why is clock skew irrelevant in this example?


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( (t

t w > t sumax or

+ tl min t w thmax

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Sequential Systems Using Latches


Latches can be used to create sequential systems. However, since these are level-triggered clocking must be done carefully must ensure that state changes only once per clock cycle. tw < tff.min+ tD-Q.min
Dj Qj CLK Qi
tskew

Clocking Constraints with Latches


CKi CKj Dj Qj Di

tw tsu tw tskew

Comb. logic

CKj

Di
CKi

Comb. logic > (tD-Q.max + tff.max+ tsu.max)


CLK tff

CKj

tD-Q

Di
CKi

Qi

tskew

Qi

tff th

CLK

tff

Dj

Use narrow-width clock whose pulse width is less than the fastest possible path through the combinational logic.
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tw < t D Qmin + t ffmin thmax tskewmax tw > tsumax


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To guarantee correct next state, make sure that the clock period is longer than the worst-case propagation delay through the combinational logic.
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Clocking Frequency with Latches


Tclk
CKi CKj Qj Dj

Dj

tskew tw tsu tD-Q tff tsu

Comb. logic

CKj

Di
CKi

Qi

tskew

Qj

CLK

tff

Di

Tclk > tskewmax + tw tsumin + t D Qmax + t ffmax + tsumax


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