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LTC2309

1
2309fd
BLOCK DIAGRAM
FeAtuRes
AppLICAtIOns
DesCRIptIOn
8-Channel, 12-Bit SAR ADC
with I
2
C Interface
n
IndustrialProcessControl
n
MotorControl
n
AccelerometerMeasurements
n
Battery-OperatedInstruments
n
Isolatedand/orRemoteDataAcquisition
n
PowerSupplyMonitoring
Integral Nonlinearity
vs Output Code
n
12-Bit Resolution
n
Low Power: 1.5mW at 1ksps, 35W Sleep Mode
n
14ksps Throughput Rate
n
Low Noise: SNR = 73.4dB
n
GuaranteedNoMissingCodes
n
Single5VSupply
n
2-WireI
2
CCompatibleSerialInterfacewithNine
AddressesPlusOneGlobalforSynchronization
n
FastConversionTime:1.3s
n
InternalReference
n
Internal8-ChannelMultiplexer
n
InternalConversionClock
n
UnipolarorBipolarInputRanges(SoftwareSelectable)
n
GuaranteedOperationfrom40Cto125C
(TSSOPPackage)
n
24-Pin4mm4mmQFNand20-PinTSSOPPackages
TheLTC

2309isalownoise,lowpower,8-channel,12-bit
successive approximation ADC with an I
2
C compatible
serialinterface.ThisADCincludesaninternalreference
andafullydifferentialsample-and-holdcircuittoreduce
common mode noise. The LTC2309 operates from an
internalclocktoachieveafast1.3sconversiontime.
The LTC2309 operates from a single 5V supply and
draws just 300A at a throughput rate of 1ksps. The
ADC enters nap mode when not converting, reducing
thepowerdissipation.
TheLTC2309isavailableinbothasmall24-pin4mm
4mmQFNanda20-pinTSSOPpackage.Theinternal2.5V
referenceand8-channelmultiplexerfurtherreducePCB
boardspacerequirements.
The low power consumption and small size make the
LTC2309idealforbattery-operatedandportableapplica-
tions,whilethe2-wireI
2
Ccompatibleserialinterfacemakes
thisADCagoodmatchforspace-constrainedsystems.
L,LT,LTC,LTM,LinearTechnologyandtheLinearlogoareregisteredtrademarksand
EasyDriveisatrademarkofLinearTechnologyCorporation.Allothertrademarksarethe
propertyoftheirrespectiveowners.
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
2309 TA01
I
2
C
PORT
ANALOG
INPUT
MUX
ANALOG INPUTS
0V TO 4.096V UNIPOLAR
2.048V BIPOLAR
REFCOMP
INTERNAL
2.5V REF
V
DD
5V
GND
LTC2309
0.1F
12-BIT
SAR ADC
+

2.2F
10F 0.1F
10F
V
REF
SDA
SCL
AD1
AD0
OUTPUT CODE
0
I
N
L

(
L
S
B
)
0
0.25
0.50
4096
2309 G01
0.25
0.50
1.00
1024 2048 3072
0.75
1.00
0.75
LTC2309
2
2309fd
ABsOLute MAxIMuM RAtInGs (Notes 1, 2)
ORDeR InFORMAtIOn
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2309CUF#PBF LTC2309CUF#TRPBF 2309 24-Lead(4mm4mm)PlasticQFN 0Cto70C
LTC2309IUF#PBF LTC2309IUF#TRPBF 2309 24-Lead(4mm4mm)PlasticQFN 40Cto85C
LTC2309CF#PBF LTC2309CF#TRPBF LTC2309F 20-LeadPlasticTSSOP 0Cto70C
LTC2309IF#PBF LTC2309IF#TRPBF LTC2309F 20-LeadPlasticTSSOP 40Cto85C
LTC2309HF#PBF LTC2309HF#TRPBF LTC2309F 20-LeadPlasticTSSOP 40Cto125C
ConsultLTCMarketingforpartsspecifiedwithwideroperatingtemperatureranges.*Thetemperaturegradeisidentifiedbyalabelontheshippingcontainer.
ConsultLTCMarketingforinformationonnon-standardleadbasedfinishparts.
Formoreinformationonleadfreepartmarking,goto:http://www.linear.com/leadfree/
Formoreinformationontapeandreelspecifications,goto:http://www.linear.com/tapeandreel/
SupplyVoltage
V
DD
.......................................................... 0.3Vto6V
AnalogInputVoltage(Note3)
CH0-CH7,COM,V
REF
,
REFCOMP.................... (GND0.3V)to(V
DD
+0.3V)
DigitalInputVoltage
(Note3)............................ (GND0.3V)to(V
DD
+0.3V)
DigitalOutputVoltage...... (GND0.3V)to(V
DD
+0.3V)
PowerDissipation.............................................. 500mW
OperatingTemperatureRange
LTC2309C................................................ 0Cto70C
LTC2309I............................................. 40Cto85C
LTC2309H.......................................... 40Cto125C
StorageTemperatureRange.................. 65Cto150C
LeadTemperature(Soldering,10sec)
TSSOP.............................................................. 300C
24
25
23 22 21 20 19
7 8 9
TOP VIEW
UF PACKAGE
24-LEAD (4mm s 4mm) PLASTIC QFN
10 11 12
6
5
4
3
2
1
13
14
15
16
17
18 CH3
CH4
CH5
CH6
CH7
COM
GND
SDA
SCL
AD1
AD0
V
DD
C
H
2
C
H
1
C
H
0
V
D
D
G
N
D
G
N
D
V
R
E
F
R
E
F
C
O
M
P
G
N
D
G
N
D
G
N
D
V
D
D

T
JMAX
=150C,
JA
=37C/W
EXPOSEDPAD(PIN25)ISGND,MUSTBESOLDEREDTOPCB
F PACKAGE
20-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
REFCOMP
GND
V
DD
AD0
AD1
SCL
SDA
GND
GND
V
DD
V
REF
COM
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0

T
JMAX
=150C,
JA
=90C/W,
JC
=20C/W
pIn COnFIGuRAtIOn
LTC2309
3
2309fd
COnVeRteR AnD MuLtIpLexeR CHARACteRIstICs
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution(NoMissingCodes) l 12 Bits
IntegralLinearityError (Note6) l 0.45 1 LSB
DifferentialLinearityError l 0.35 1 LSB
BipolarZeroError (Note7) l 1 8 LSB
BipolarZeroErrorDrift 0.002 LSB/C
BipolarZeroErrorMatch 0.1 3 LSB
UnipolarZeroError (Note7) l 0.4 6 LSB
UnipolarZeroErrorDrift 0.002 LSB/C
UnipolarZeroErrorMatch 0.2 1 LSB
BipolarFull-ScaleError ExternalReference(Note8)
REFCOMP=4.096V
l
l
0.5
0.4
10
9
LSB
LSB
BipolarFull-ScaleErrorDrift ExternalReference 0.05 LSB/C
BipolarFull-ScaleErrorMatch 0.4 3 LSB
UnipolarFull-ScaleError QFNExternalReference(Note8)
TSSOPExternalReference(Note8)
l
l
0.4
0.5
10
12
LSB
LSB
REFCOMP=4.096V l 0.3 6 LSB
UnipolarFull-ScaleErrorDrift ExternalReference 0.05 LSB/C
UnipolarFull-ScaleErrorMatch 0.3 2 LSB
The l denotes the specifications
which apply over the full operating temperature range, otherwise specifications are at T
A
= 25C. (Notes 4, 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
+
AbsoluteInputRange(CH0toCH7) (Note9) l 0.05 REFCOMP V
V
IN

AbsoluteInputRange(CH0toCH7,COM) Unipolar(Note9)
Bipolar(Note9)
l
l
0.05
0.05
0.25REFCOMP
0.75REFCOMP
V
V
V
IN
+
V
IN

InputDifferentialVoltageRange V
IN
=V
IN
+
V
IN

(Unipolar)
V
IN
=V
IN
+
V
IN

(Bipolar)
l
l
0toREFCOMP
REFCOMP/2
V
V
I
IN
AnalogInputLeakageCurrent l 1 A
C
IN
AnalogInputCapacitance SampleMode
HoldMode
55
5
pF
pF
CMRR InputCommonModeRejectionRatio 70 dB
AnALOG Input The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal-to-(Noise+Distortion)Ratio f
IN
=1kHz l 71 73.3 dB
SNR Signal-to-NoiseRatio f
IN
=1kHz l 71 73.4 dB
THD TotalHarmonicDistortion f
IN
=1kHz,First5Harmonics l 88 77 dB
SFDR SpuriousFreeDynamicRange f
IN
=1kHz l 79 90 dB
Channel-to-ChannelIsolation f
IN
=1kHz 109 dB
FullLinearBandwidth (Note11) 700 kHz
3dBInputLinearBandwidth 25 MHz
ApertureDelay 13 ns
TransientResponse Full-ScaleStep 240 ns
DYnAMIC ACCuRACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25C. A
IN
= 1dBFS. (Notes 4, 10)
LTC2309
4
2309fd
pOWeR ReQuIReMents
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
REF
OutputVoltage I
OUT
=0(QFN)
I
OUT
=0(TSSOP)
l
l
2.47
2.46
2.50
2.50
2.53
2.54
V
V
V
REF
OutputTempco I
OUT
=0 25 ppm/C
V
REF
OutputImpedance 0.1mAI
OUT
0.1mA 8 k
V
REFCOMP
OutputVoltage I
OUT
=0 4.096 V
V
REF
LineRegulation V
DD
=4.75Vto5.25V 0.8 mV/V
InteRnAL ReFeRenCe CHARACteRIstICs The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at T
A
= 25C. (Note 4)
I
2
C Inputs AnD DIGItAL Outputs The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at T
A
= 25C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
HighLevelInputVoltage l 2.85 V
V
IL
LowLevelInputVoltage l 1.5 V
V
IHA
HighLevelInputVoltageforAddressPinsA1,A0 l 4.75 V
V
ILA
LowLevelInputVoltageforAddressPinsA1,A0 l 0.25 V
R
INH
ResistancefromA1,A0,toV
DD
toSetChip
AddressBitto1
l 10 k
R
INL
ResistancefromA1,A0toGNDtoSetChip
AddressBitto0
l 10 k
R
INF
ResistancefromA1,A0toGNDorV
DD
toSet
ChipAddressBittoFloat
l 2 M
I
I
DigitalInputCurrent V
IN
=V
DD
l 10 10 A
V
HYS
HysteresisofSchmittTriggerInputs (Note9) l 0.25 V
V
OL
LowLevelOutputVoltage(SDA) I=3mA l 0.4 V
t
OF
OutputFallTimeV
H
toV
IL(MAX)
(Note12) l 20+0.1C
B
250 ns
t
SP
InputSpikeSuppression l 50 ns
C
CAX
ExternalCapacitanceLoadOn-ChipAddressPins
(A1,A0)forValidFloat
l 10 pF
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
SupplyVoltage l 4.75 5 5.25 V
I
DD
SupplyCurrent 14kspsSampleRate l 2.3 3 mA
NapMode SLPBit=0,ConversionDone l 210 350 A
SleepMode SLPBit=1,ConversionDone l 7 15 A
P
D
PowerDissipation 14kspsSampleRate l 11.5 15 mW
NapMode SLPBit=0,ConversionDone l 1.05 1.75 mW
SleepMode SLPBit=1,ConversionDone l 35 75 W
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25C. (Note 4)
LTC2309
5
2309fd
I
2
C tIMInG CHARACteRIstICs The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SCL
SCLClockFrequency l 400 kHz
t
HD(SDA)
HoldTime(Repeated)STARTCondition l 0.6 s
t
LOW
LOWPeriodoftheSCLPin l 1.3 s
t
HIGH
HIGHPeriodoftheSCLPin l 0.6 s
t
SU(STA)
Set-UpTimeforaRepeatedSTARTCondition l 0.6 s
t
HD(DAT)
DataHoldTime l 0 0.9 s
t
SU(DAT)
DataSet-UpTime l 100 ns
t
r
RiseTimeforSDA/SCLSignals (Note12) l 20+0.1C
B
300 ns
t
f
FallTimeforSDA/SCLSignals (Note12) l 20+0.1C
B
300 ns
t
SU(STO)
Set-UpTimeforSTOPCondition l 0.6 s
t
BUF
BusFreeTimeBetweenaSTOPandSTARTCondition l 1.3 s
ADC tIMInG CHARACteRIstICs The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SMPL
ThroughputRate(SuccessiveReads) l 14 ksps
t
CONV
ConversionTime (Note9) l 1.3 1.8 s
t
ACQ
AcquisitionTime (Note9) l 240 ns
t
REFWAKE
REFCOMPWake-UpTime(Note13) C
REFCOMP
=10F,C
REF
=2.2F 200 ms
Note 1:StressesbeyondthoselistedunderAbsoluteMaximumRatings
maycausepermanentdamagetothedevice.ExposuretoanyAbsolute
MaximumRatingconditionforextendedperiodsmayaffectdevice
reliabilityandlifetime.
Note 2:Allvoltagevaluesarewithrespecttoground.
Note 3:WhenthesepinvoltagesaretakenbelowgroundoraboveV
DD
,
theywillbeclampedbyinternaldiodes.Theseproductscanhandleinput
currentsgreaterthan100mAbelowgroundoraboveV
DD
withoutlatchup.
Note 4:V
DD
=5V,f
SMPL
=14kspsinternalreferenceunlessotherwise
noted.
Note 5:Linearity,offsetandfull-scalespecificationsapplyfora
single-endedanaloginputwithrespecttoCOM.
Note 6:Integralnonlinearityisdefinedasthedeviationofacodefroma
straightlinepassingthroughtheactualendpointsofthetransfercurve.
Thedeviationismeasuredfromthecenterofthequantizationband.
Note 7:Bipolarzeroerroristheoffsetvoltagemeasuredfrom0.5LSB
whentheoutputcodeflickersbetween000000000000and11111111
1111.Unipolarzeroerroristheoffsetvoltagemeasuredfrom+0.5LSB
whentheoutputcodeflickersbetween000000000000and00000000
0001.
Note 8:Full-scalebipolarerroristheworst-caseofFSor+FSuntrimmed
deviationfromidealfirstandlastcodetransitionsandincludestheeffect
ofoffseterror.Unipolarfull-scaleerroristhedeviationofthelastcode
transitionfromidealandincludestheeffectofoffseterror.
Note 9:Guaranteedbydesign,notsubjecttotest.
Note 10:AllspecificationsindBarereferredtoafull-scale2.048Vinput
witha2.5Vreferencevoltage.
Note 11:Fulllinearbandwidthisdefinedasthefull-scaleinputfrequency
atwhichtheSINADdegradesto60dBor10bitsofaccuracy.
Note 12:C
B
=capacitanceofonebuslineinpF(10pFC
B
400pF).
Note 13:REFCOMPwake-uptimeisthetimerequiredfortheREFCOMP
pintosettlewithin0.5LSBat12-bitresolutionofitsfinalvalueafter
wakingupfromSLEEPmode.
LTC2309
6
2309fd
tYpICAL peRFORMAnCe CHARACteRIstICs
Integral Nonlinearity
vs Output Code
1kHz Sine Wave
8192 Point FFT Plot
Supply Current
vs Sampling Frequency Offset Error vs Temperature Full-Scale Error vs Temperature
Supply Current vs Temperature Sleep Current vs Temperature
Analog Input Leakage Current
vs Temperature
T
A
= 25C, V
DD
= 5V, f
SMPL
= 14ksps, unless otherwise noted.
Differential Nonlinearity
vs Output Code
OUTPUT CODE
0
I
N
L

(
L
S
B
)
0
0.25
0.50
4096
2309 G01
0.25
0.50
1.00
1024 2048 3072
0.75
1.00
0.75
OUTPUT CODE
0
D
N
L

(
L
S
B
)
0
0.25
0.50
4096
2309 G02
0.25
0.50
1.00
1024 2048 3072
0.75
1.00
0.75
FREQUENCY (kHz)
0
140
M
A
G
N
I
T
U
D
E

(
d
B
)
120
100
80
0
40
1 3 4 7
2309 G03
20
60
2 5 6
SNR = 73.4dB
SINAD = 73.3dB
THD = 88dB
SAMPLING FREQUENCY (ksps)
0.1
0
S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
1.5
2.0
2.5
1 10 100
3209 G04
1.0
0.5
TEMPERATURE (C)
50
O
F
F
S
E
T

E
R
R
O
R

(
L
S
B
)
1.5
25
2309 G05
0
1.0
25 0 50
0.5
2.0
2.0
1.0
0.5
0.5
75 100 125
UNIPOLAR
BIPOLAR
TEMPERATURE (C)
50 25
6
F
U
L
L
-
S
C
A
L
E

E
R
R
O
R

(
L
S
B
)
2
4
0 50 75
2309 G06
4
2
0
25 100 125
UNIPOLAR
BIPOLAR
TEMPERATURE (C)
50
1.0
S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
1.2
1.6
1.8
2.0
3.0
2.4
0 50 75
2309 G07
1.4
2.6
2.8
2.2
25 25 100 125
TEMPERATURE (C)
50
0
L
E
A
K
A
G
E

C
U
R
R
E
N
T

(
n
A
)
100
300
400
500
1000
700
0 50 75
2309 G09
200
800
900
600
25 25 100 125
CH (ON)
CH (OFF)
TEMPERATURE (C)
50 25
0
S
L
E
E
P

C
U
R
R
E
N
T

(

A
)
4
10
0 50 75
2309 G08
2
8
6
25 100 125
LTC2309
7
2309fd
pIn FunCtIOns
CH3-CH7 (Pins 1-5):Channel3toChannel7Analog
Inputs. CH3-CH7 can be configured as single-ended
or differential input channels. See the Analog Input
Multiplexersection.
COM (Pin 6): Common Input. This is the reference
point for all single-ended inputs. It must be free of
noiseandshouldbeconnectedtogroundforunipolar
conversionsandmidwaybetweenGNDandREFCOMP
forbipolarconversions.
V
REF
(Pin 7):2.5VReferenceOutput.BypasstoGND
withaminimum2.2Fceramiccapacitor.Theinternal
referencemaybeoverdrivenbyanexternal2.5Vrefer-
enceatthispin.
REFCOMP (Pin 8): Reference Buffer Output. Bypass
to GND with 10F and 0.1F ceramic capacitors in
parallel.Nominaloutputvoltageis4.096V.Theinternal
referencebufferdrivingthispinisdisabledbyground-
ingV
REF
,allowingREFCOMPtobeoverdrivenbyan
externalsource.
GND (Pins 9-11, 18-20):Ground.AllGNDpinsmust
beconnectedtoasolidgroundplane.
V
DD
(Pins 12, 13, 21):5VSupply.TherangeofV
DD
is
4.75Vto5.25V.BypassV
DD
toGNDwitha10Fceramic
capacitorinparallelwiththree0.1Fceramiccapacitors,
onelocatedascloseaspossibletoeachpin.
AD0 (Pin 14): Chip Address Control Pin. This pin is
configuredasathree-state(LOW,HIGH,floating)ad-
dresscontrolbitforthedeviceI
2
Caddress.SeeTable2
foraddressselection.
AD1 (Pin 15): Chip Address Control Pin. This pin is
configured as a three-state (LOW, HIGH, floating)
address control bit for the device I
2
C address. See
Table2foraddressselection.
SCL (Pin 16):SerialClockPinoftheI
2
CInterface.The
LTC2309canonlyactasaslaveandtheSCLpinonly
accepts an external serial clock. Data is shifted into
theSDApinontherisingedgesoftheSCLclockand
outputthroughtheSDApinonthefallingedgesofthe
SCLclock.
SDA (Pin 17):BidirectionalSerialDataLineoftheI
2
C
Interface.Intransmittermode(read),theconversion
resultisoutputattheSDApin,whileinreceivermode
(write),theD
IN
wordisinputattheSDApintocon-
figuretheADC.Thepinishighimpedanceduringthe
datainputmodeandisanopen-drainoutput(requires
anappropriatepull-updevicetoV
DD
)duringthedata
outputmode.
CH0-CH2 (Pins 22-24):Channel0toChannel2Analog
Inputs. CH0-CH2 can be configured as single-ended
or differential input channels. See the Analog Input
Multiplexersection.
Exposed Pad (Pin 25): Ground. Must be soldered
directlytogroundplane.
(QFN)
LTC2309
8
2309fd
pIn FunCtIOns
REFCOMP (Pin 1): Reference Buffer Output. Bypass
to GND with 10F and 0.1F ceramic capacitors in
parallel.Nominaloutputvoltageis4.096V.Theinternal
referencebufferdrivingthispinisdisabledbyground-
ingV
REF
,allowingREFCOMPtobeoverdrivenbyan
externalsource.
GND (Pins 2, 8 , 9): Ground. All GND pins must be
connectedtoasolidgroundplane.
V
DD
(Pins 3, 10):5VSupply.TherangeofV
DD
is4.75V
to5.25V.BypassV
DD
toGNDwitha10Fceramicca-
pacitorinparallelwithtwo0.1Fceramiccapacitors,
onelocatedascloseaspossibletoeachpin.
AD0 (Pin 4):ChipAddressControlPin.Thispiniscon-
figuredasathree-state(LOW,HIGH,floating)address
controlbitforthedeviceI
2
Caddress.SeeTable2for
addressselection.
AD1 (Pin 5): Chip Address Control Pin. This pin is
configured as a three-state (LOW, HIGH, floating)
address control bit for the device I
2
C address. See
Table2foraddressselection.
SCL (Pin 6):SerialClockPinoftheI
2
CInterface.The
LTC2309canonlyactasaslaveandtheSCLpinonly
accepts an external serial clock. Data is shifted into
theSDApinontherisingedgesoftheSCLclockand
outputthroughtheSDApinonthefallingedgesofthe
SCLclock.
SDA (Pin 7):BidirectionalSerialDataLineoftheI
2
C
Interface.Intransmittermode(read),theconversion
resultisoutputattheSDApin,whileinreceivermode
(write),theD
IN
wordisinputattheSDApintocon-
figuretheADC.Thepinishighimpedanceduringthe
datainputmodeandisanopen-drainoutput(requires
anappropriatepull-updevicetoV
DD
)duringthedata
outputmode.
CH0-CH7 (Pins 11-18):Channel0toChannel7Analog
Inputs. CH0-CH7 can be configured as single-ended
or differential input channels. See the Analog Input
Multiplexersection.
COM (Pin 19): Common Input. This is the reference
point for all single-ended inputs. It must be free of
noiseandshouldbeconnectedtogroundforunipolar
conversionsandmidwaybetweenGNDandREFCOMP
forbipolarconversions.
V
REF
(Pin 20):2.5VReferenceOutput.BypasstoGND
withaminimum2.2Fceramiccapacitor.Theinternal
referencemaybeoverdrivenbyanexternal2.5Vrefer-
enceatthispin.
(TSSOP)
LTC2309
9
2309fd
FunCtIOnAL BLOCK DIAGRAM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
2308 BD
I
2
C
PORT
ANALOG
INPUT
MUX
REFCOMP
INTERNAL
2.5V REF
V
DD
GND
12-BIT
SAR ADC
LTC2309
8k
GAIN = 1.6384x
+

V
REF
SDA
SCL
AD1
AD0
tIMInG DIAGRAM
Definition of Timing for Fast/Standard Mode Devices on the I
2
C Bus
SDA
SCL
S Sr P S
t
HD(SDA)
S = START, Sr = REPEATED START, P = STOP
t
HD(DAT)
t
SU(STA)
t
SU(STO)
t
SU(DAT)
t
LOW
t
HD(SDA)
t
SP
t
BUF
t
r
t
f
t
r
t
f
t
HIGH
2309 TD
LTC2309
10
2309fd
AppLICAtIOns InFORMAtIOn
Overview
TheLTC2309isalownoise,8-channel,12-bitsucces-
siveapproximationregister(SAR)A/Dconverterwithan
I
2
Ccompatibleserialinterface.TheLTC2309includesa
precisioninternalreferenceandaconfigurable8-chan-
nelanaloginputmultiplexer(MUX).TheADCmaybe
configuredtoacceptsingle-endedordifferentialsignals
andcanoperateineitherunipolarorbipolarmode.A
sleepmodeoptionisalsoprovidedtofurtherreduce
powerduringinactiveperiods.
The LTC2309 communicates through a 2-wire I
2
C
compatible serial interface. Conversions are initiated
bysignalingaSTOPconditionaftertheparthasbeen
successfullyaddressedforaread/writeoperation.The
devicewillnotacknowledge(NACK)anexternalrequest
untiltheconversionisfinished.Afteraconversionis
finished, the device is ready to accept a read/write
request. Once the LTC2309 is addressed for a read
operation, the device begins outputting the conver-
sionresultunderthecontroloftheserialclock(SCL).
Thereisnolatencyintheconversionresult.Thereare
12bitsofoutputdatafollowedby4trailingzeros.Data
is updated on the falling edges of SCL, allowing the
usertoreliablylatchdataontherisingedgeofSCL.A
writeoperationmayfollowthereadoperationbyusing
arepeatSTARToraSTOPconditionmaybegivento
startanewconversion.Byselectingawriteoperation,
theADCcanbeprogrammedwitha6-bitD
IN
word.The
D
IN
wordconfigurestheMUXandprogramsvarious
modesofoperationoftheADC.
During a conversion, the internal 12-bit capacitive
chargeredistributionDACoutputissequencedthrough
asuccessiveapproximationalgorithmbytheSARstart-
ing from the most significant bit (MSB) to the least
significantbit(LSB).Thesampledinputissuccessively
compared with binary weighted charges supplied by
thecapacitiveDACusingadifferentialcomparator.At
theendofaconversion,theDACoutputbalancesthe
analoginput.TheSARcontents(a12-bitdataword)
thatrepresentthesampledanaloginputareloadedinto
12outputlatchesthatallowthedatatobeshiftedout
viatheI
2
Cinterface.
Programming the LTC2309
The various modes of operation of the LTC2309 are
programmedbya6-bitD
IN
word.TheSDIinputdata
bitsareloadedontherisingedgeofSCLduringawrite
operation,withtheS/Dbitloadedonthefirstrisingedge
andtheSLPbitonthesixthrisingedge(seeFigure8b
in the I
2
C Interface section). The input data word is
definedasfollows:

S/D O/S S1 S0 UNI SLP


S/D=SINGLE-ENDED/DIFFERENTIALBIT
O/S=ODD/SIGNBIT
S1=CHANNELSELECTBIT1
S0=CHANNELSELECTBIT0
UNI=UNIPOLAR/BIPOLARBIT
SLP=SLEEPMODEBIT
Analog Input Multiplexer
The analog input MUX is programmed by the S/D,
O/S,S1andS0bitsoftheD
IN
word.Table1liststhe
MUX configurations for all combinations of the con-
figurationbits.Figure1ashowsseveralpossibleMUX
configurationsandFigure1bshowshowtheMUXcan
bereconfiguredfromoneconversiontothenext.
Driving the Analog Inputs
The analog inputs of the LTC2309 are easy to drive.
Eachoftheanaloginputscanbeusedasasingle-ended
input relative to the COM pin (CH0-COM, CH1-COM,
etc.)orindifferentialinputpairs(CH0andCH1,CH2
andCH3,CH4andCH5,CH6andCH7).Figure2shows
howtodriveCOMforsingle-endedinputsinunipolar
andbipolarmodes.RegardlessoftheMUXconfigura-
tion,the+andinputsaresampledatthesame
instant.Anyunwantedsignalthatiscommontoboth
inputswillbereducedbythecommonmoderejection
ofthesample-and-holdcircuit.Theinputsdrawonly
onesmallcurrentspikewhilechargingthesample-and-
holdcapacitorsduringtheacquiremode.Inconversion
LTC2309
11
2309fd
AppLICAtIOns InFORMAtIOn
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM ()
8 Single-Ended
+
+
+
+
+
+
+
4 Differential
+ () +
+ ()
+ ()
+ ()

(+)

(+)

(+)

(+)
COM ()
Combinations of Differential
and Single-Ended
+
+
+
+
+
+

{
{
{
{
{
{
2309 F01a
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Table 1. Channel Configuration
S/D O/S S1 S0 0 1 2 3 4 5 6 7 COM
0 0 0 0 +
0 0 0 1 +
0 0 1 0 +
0 0 1 1 +
0 1 0 0 +
0 1 0 1 +
0 1 1 0 +
0 1 1 1 +
1 0 0 0 +
1 0 0 1 +
1 0 1 0 +
1 0 1 1 +
1 1 0 0 +
1 1 0 1 +
1 1 1 0 +
1 1 1 1 +
COM
(UNUSED)
COM ()
1st Conversion 2nd Conversion
+

+
+
{
{
{
{
CH2
CH3
CH4
CH5
CH2
CH3
CH4
CH5
2328 F01b
COM COM
REFCOMP/2
Unipolar Mode Bipolar Mode
2328 F02
+

Figure 1a. Example of MUX Configurations


Figure 1b. Changing the MUX Assignments On the Fly
Figure 2. Driving COM in Unipolar and Bipolar Modes
mode,theanaloginputsdrawonlyasmallleakagecur-
rent.Ifthesourceimpedanceofthedrivingcircuitis
low,theADCinputscanbedrivendirectly.Otherwise,
moreacquisitiontimeshouldbeallowedforasource
withhigherimpedance.
Input Filtering
The noise and distortion of the input amplifier and
othercircuitrymustbeconsideredsincetheywilladd
totheADCnoiseanddistortion.Therefore,noisyinput
circuitryshouldbefilteredpriortotheanaloginputsto
minimizenoise.Asimple1-poleRCfilterissufficient
formanyapplications.
TheanaloginputsoftheLTC2309canbemodeledas
a55pFcapacitor(C
IN
)inserieswitha100resistor
(R
ON
),asshowninFigure3a.C
IN
getsswitchedtothe
selectedinputonceduringeachconversion.Largefilter
RCtimeconstantswillslowthesettlingoftheinputs.
It is important that the overall RC time constants be
shortenoughtoallowtheanaloginputstocompletely
settleto12-bitresolutionwithintheacquisitiontime
(t
ACQ
)ifDCaccuracyisimportant.
LTC2309
12
2309fd
AppLICAtIOns InFORMAtIOn
WhenusingafilterwithalargeC
FILTER
value(e.g.1F),
theinputsdonotcompletelysettleandthecapacitive
input switching currents are averaged into a net DC
current(I
DC
).Inthiscase,theanaloginputcanbemod-
eledbyanequivalentresistance(R
EQ
=1/(f
SMPL
C
IN
))
inserieswithanidealvoltagesource(V
REFCOMP
/2),as
showninFigure3b.ThemagnitudeoftheDCcurrent
is then approximately I
DC
= (V
IN
V
REFCOMP
/2)/R
EQ
,
whichisroughlyproportionaltoV
IN
.Topreventlarge
DCdropsacrosstheresistorR
FILTER
,afilterwithasmall
resistorandlargecapacitorshouldbechosen.When
running at the maximum throughput rate of 14ksps,
theinputcurrentequals1.5AatV
IN
=4.096V,which
amountstoafull-scaleerrorof0.5LSBwhenusinga
filterresistor(R
FILTER
)of333.Applicationsrequiring
lowersampleratescantoleratealargerfilterresistor
forthesameamountoffull-scaleerror.
selfheatingandfromdamagethatmayoccurduring
soldering.Metalfilmsurfacemountresistorsaremuch
lesssusceptibletobothproblems.
Dynamic Performance
FastFourierTransform(FFT)testtechniquesareusedto
testtheADCsfrequencyresponse,distortionandnoise
attheratedthroughput.Byapplyingalowdistortion
sinewaveandanalyzingthedigitaloutputusinganFFT
algorithm,theADCsspectralcontentcanbeexamined
forfrequenciesoutsidethefundamental.
Signal-to-Noise and Distortion Ratio (SINAD)
Thesignal-to-noiseanddistortionratio(SINAD)isthe
ratiobetweentheRMSamplitudeofthefundamental
inputfrequencytotheRMSamplitudeofallotherfre-
quencycomponentsattheA/Doutput.Theoutputis
band-limitedtofrequenciesfromaboveDCandbelow
halfthesamplingfrequency.Figure5showsatypical
SINAD of 73.3dB with a 14kHz sampling rate and a
1kHz input. An SNR of 73.4dB can be achieved with
theLTC2309.
V
IN
INPUT
CH0-CH7
R
ON
100
C
IN
55pF
C
FILTER
R
SOURCE
2309 F03a
LTC2309
Figure 3a. Analog Input Equivalent Circuit
V
IN
INPUT
CH0-CH7
R
EQ
1/(f
SMPL
C
IN
)
V
REFCOMP
/2
C
FILTER
R
FILTER
I
DC
2309 F03b
LTC2309
+

Figure 3b. Analog Input Equivalent


Circuit for Large Filter Capacitances
Figures4aand4bshowexamplesofinputfilteringfor
single-ended and differential inputs. For the single-
endedcaseinFigure4a,a50sourceresistoranda
2000pFcapacitortogroundontheinputwilllimitthe
inputbandwidthto1.6MHz.Highqualitycapacitorsand
resistors should be used in the RC filter since these
componentscanadddistortion.NPOandsilvermica
typedielectriccapacitorshaveexcellentlinearity.Carbon
surfacemountresistorscangeneratedistortionfrom
2309 F04a
CH0
COM
LTC2309
REFCOMP
2000pF
0.1F 10F
50
ANALOG
INPUT
Figure 4a. Optional RC Input Filtering for Single-Ended Input
1000pF
2309 F04b
CH0
CH1
LTC2309
REFCOMP
1000pF
1000pF
0.1F 10F
50
50
DIFFERENTIAL
ANALOG
INPUTS
Figure 4b. Optional RC Input Filtering for Differential Inputs
LTC2309
13
2309fd
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the
RMSsumofallharmonicsoftheinputsignaltothe
fundamentalitself.Theout-of-bandharmonicsaliasinto
thefrequencybandbetweenDCandhalfthesampling
frequency(
fSMPL
/2).THDisexpressedas:

THD
V V V V
V
N
=
+ + +
20
2
2
3
2
4
2 2
1
log
...
where V
1
is the RMS amplitude of the fundamental
frequencyandV
2
throughV
N
aretheamplitudesofthe
secondthroughNthharmonics.
Internal Reference
The LTC2309 has an on-chip, temperature compen-
sated bandgap reference that is factory trimmed to
2.5V(RefertoFigure6a).Itisinternallyconnectedtoa
referenceamplifierandisavailableatV
REF
.V
REF
should
bebypassedtoGNDwitha2.2Fceramiccapacitorto
minimizenoise.An8kresistorisinserieswiththeoutput
sothatitcanbeeasilyoverdrivenbyanexternalrefer-
enceifmoreaccuracyand/orlowerdriftarerequired,
asshowninFigure6b.Thereferenceamplifiergains
theV
REF
voltageby1.638to4.096VatREFCOMP.To
compensatethereferenceamplifier,bypassREFCOMP
witha10Fceramiccapacitorinparallelwitha0.1F
ceramic capacitor for best noise performance. The
internalreferencebuffercanalsobeoverdrivenfrom
1VtoV
DD
,asshowninFigure6c.Todoso,V
REF
must
begroundedtodisablethereferencebuffer.
AppLICAtIOns InFORMAtIOn
Figure 5. 1kHz Sine Wave 8192 Point FFT Plot
R2
R3
REFERENCE
AMP
0.1F
10F
2.2F
REFCOMP
GND
V
REF
R1
8k
2.5V
4.096V
LTC2309
2309 F06a
BANDGAP
REFERENCE
Figure 6a. LTC2309 Reference Circuit
0.1F 10F
2309 F06b
LT1790A-2.5
V
OUT
V
IN
5V
V
REF
LTC2309
GND
REFCOMP
2.2F
0.1F
Figure 6b. Using the LT

1790A-2.5 as an External Reference


FREQUENCY (kHz)
0
140
M
A
G
N
I
T
U
D
E

(
d
B
)
120
100
80
0
40
1 3 4 7
2309 G03
20
60
2 5 6
SNR = 73.4dB
SINAD = 73.3dB
THD = 88dB
Figure 6c. Overdriving REFCOMP Using the LT1790A-4.096
0.1F
0.1F
10F
2309 F06c
LT1790A-4.096
V
OUT
V
IN
5V
V
REF
LTC2309
GND
REFCOMP
LTC2309
14
2309fd
Internal Conversion Clock
The internal conversion clock is factory trimmed to
achieveatypicalconversiontime(t
CONV
)of1.3sand
a maximum conversion time of 1.8s over the full
operatingtemperaturerange.
I
2
C Interface
TheLTC2309communicatesthroughanI
2
Cinterface.
TheI
2
Cinterfaceisa2-wireopen-draininterfacesup-
porting multiple devices and multiple masters on a
single bus. The connected devices can only pull the
serialdataline(SDA)LOWandcanneverdriveitHIGH.
SDAisrequiredtobeexternallyconnectedtothesup-
plythroughapull-upresistor.Whenthedatalineisnot
beingdrivenLOW,itisHIGH.DataontheI
2
Cbuscan
betransferredatratesupto100kbits/sinthestandard
modeandupto400kbits/sinthefastmode.TheV
DD

powershouldnotberemovedfromtheLTC2309when
theI
2
CbusisactivetoavoidloadingtheI
2
Cbuslines
throughtheinternalESDprotectiondiodes.
EachdeviceontheI
2
Cbusisrecognizedbyaunique
addressstoredinthedeviceandcanonlyoperateeither
asatransmitterorreceiver,dependingonthefunction
of the device. A device can also be considered as a
masteroraslavewhenperformingdatatransfers.A
masteristhedevicewhichinitiatesadatatransferon
thebusandgeneratestheclocksignalstopermitthe
transfer.Devicesaddressedbythemasterareconsid-
eredslaves.
The LTC2309 can only be addressed as a slave (see
Table2).Onceaddressed,itcanreceiveconfiguration
bits(D
IN
word)ortransmitthelastconversionresult.The
serialclockline(SCL)isalwaysaninputtotheLTC2309
andtheserialdataline(SDA)isbidirectional.Thedevice
supportsthestandardmodeandthefastmodefordata
transferspeedsupto400kbits/s(seetheTimingDiagram
sectionfordefinitionoftheI
2
Ctiming).
The START and STOP Conditions
ReferringtoFigure7,aSTART(S)conditionisgener-
ated by transitioning SDA from HIGH to LOW while
SCLisHIGH.Thebusisconsideredtobebusyafterthe
STARTcondition.Whenthedatatransferisfinished,a
STOP(P)conditionisgeneratedbytransitioningSDA
fromLOWtoHIGHwhileSCLisHIGH.Thebusisfree
afteraSTOPconditionisgenerated.STARTandSTOP
conditionsarealwaysgeneratedbythemaster.
When the bus is in use, it stays busy if a repeated
START(Sr)isgeneratedinsteadofaSTOPcondition.
TherepeatedSTARTtimingisfunctionallyidenticalto
theSTARTandisusedforwritingandreadingfromthe
devicebeforetheinitiationofanewconversion.
AppLICAtIOns InFORMAtIOn
S
START Condition STOP Condition
P
2309 F07
SDA
SCL
SDA
SCL
Figure 7. Timing Diagrams of START and STOP Conditions
Data Transferring
After the START condition, the I
2
C bus is busy and
datatransfercanbeginbetweenthemasterandthe
addressedslave.Dataistransferredoverthebusin
groups of nine bits, one byte followed by one ac-
knowledge (ACK) bit. The master releases the SDA
lineduringtheninthSCLclockcycle.Theslavedevice
canissueanACKbypullingSDALOWorissueaNot
Acknowledge (NACK) by leaving the SDA line high
impedance(theexternalpull-upresistorwillholdthe
linehigh).ChangeofdataonlyoccurswhiletheSCL
lineisLOW.
Data Format
After a START condition, the master sends a 7-bit
addressfollowedbyaread/write(R/W)bit.TheR/W
bit is 1 for a read request and 0 for a write request.
If the 7-bit address matches one of the LTC2309s
9pin-selectableaddresses,theADCisselected.When
LTC2309
15
2309fd
AppLICAtIOns InFORMAtIOn
theADCisaddressedduringaconversion,itwillnot
acknowledgeR/WrequestsandwillissueaNACKby
leavingtheSDAlineHIGH.Iftheconversioniscom-
plete,theLTC2309issuesanACKbypullingtheSDA
lineLOW.TheLTC2309hastworegisters.The12-bit
wideoutputregistercontainsthelastconversionresult.
The6-bitwideinputregisterconfigurestheinputMUX
andtheoperatingmodeoftheADC.
Output Data Format
Theoutputregistercontainsthelastconversionresult.
Aftereachconversioniscompleted,thedeviceauto-
maticallyenterseithernaporsleepmodedepending
onthesettingoftheSLPbit(seeNapModeandSleep
Modesections).WhentheLTC2309isaddressedfor
a read operation, it acknowledges by pulling SDA
LOW and acts as a transmitter. The master/receiver
can read up to two bytes from the LTC2309. After a
completereadoperationof2bytes,aSTOPcondition
isneededtoinitiateanewconversion.Thedevicewill
NACKsubsequentreadoperationswhileaconversion
isbeingperformed.
Thedataoutputstreamis16bitslongandisshifted
out on the falling edges of SCL (see Figure 8a). The
firstbitistheMSBandthe12thbitistheLSBofthe
conversion result. The remaining four bits are zero.
Figures14and15arethetransfercharacteristicsfor
thebipolarandunipolarmodes.Dataisoutputonthe
SDAlinein2scomplementformatforbipolarreadings
orinstraightbinaryforunipolarreadings.
1 2
A6 SDA
START BY
MASTER
ACK BY
ADC
ACK BY
MASTER
NACK BY
MASTER
STOP
BY MASTER
CONVERSION
INITIATED
SCL
SCL
(CONTINUED)
A5 A4 A3 A2 A1 A0 R/W
3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
2309 F08a
B11 B10
READ 1 BYTE
B9 B8 B7
MOST SIGNIFICANT DATA BYTE
B6 B5 B4


SDA
(CONTINUED)


B3 B2 B1 B0
LEAST SIGNIFICANT DATA BYTE
READ 1 BYTE
ADDRESS FRAME
Figure 8a. Timing Diagram for Reading from the LTC2309
LTC2309
16
2309fd
Input Data Format
WhentheLTC2309isaddressedforawriteoperation,
itacknowledgesbypullingSDALOWduringtheLOW
periodbeforethe9thcycleandactsasareceiver.The
master/transmittercanthensend1bytetoprogramthe
device.Theinputbyteconsistsofthe6-bitD
IN
word
followedbytwobitsthatareignoredbytheADCand
are considered dont cares (X) (see Figure8b). The
inputbitsarelatchedontherisingedgeofSCLduring
thewriteoperation.
After power-up, the ADC initiates an internal reset
cyclewhichsetstheD
IN
wordtoall0s(S/D=O/S=
S0=S1=UNI=SLP=0).Awriteoperationmaybe
performedifthedefaultstateoftheADCsconfiguration
isnotdesired.Otherwise,theADCmustbeproperly
addressedandfollowedbyaSTOPconditiontoinitiate
aconversion.
Initiating a New Conversion
TheLTC2309awakensfromeithernaporsleepwhen
properlyaddressedforaread/writeoperation.ASTOP
command may then be issued after performing the
read/writeoperationtotriggeranewconversion.
IssuingaSTOPcommandafterthe8thSCLclockpulse
oftheaddressframeandbeforethecompletionofa
Table 2. Address Assignment
AD1 AD0 ADDRESS
LOW LOW 0001000
LOW Float 0001001
LOW HIGH 0001010
Float HIGH 0001011
Float Float 0011000
Float LOW 0011001
HIGH LOW 0011010
HIGH Float 0011011
HIGH HIGH 0101000
1 2
A6 SDA
START BY
MASTER
ACK BY
ADC
ACK BY
ADC
CONVERSION
INITIATED
STOP BY
MASTER
SCL
A5 A4 A3 A2 A1 A0 R/W
3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
2309 F08b
S/D O/S
WRITE 1 BYTE
S1 S0 UNI
D
IN
WORD
SLP X X
ADDRESS FRAME
Figure 8b. Timing Diagram for Writing to the LTC2309
AppLICAtIOns InFORMAtIOn
read/writeoperationwillalsoinitiatenewconversion,
buttheoutputresultmaynotbevalidduetolackof
adequateacquisitiontime(seeAcquisitionsection).
LTC2309 Address
TheLTC2309hastwoaddresspins(AD0andAD1)that
maybetiedHIGH,LOW,orleftfloatingtoenableone
of9possibleaddresses(seeTable2).
In addition to the configurable addresses listed in
Table2, the LTC2309 also contains a global address
(1101011)whichmaybeusedforsynchronizingmul-
tipleLTC2309sorotherI
2
CLTC230XSARADCs(see
SynchronizingMultipleLTC2309swithGlobalAddress
Callsection).
LTC2309
17
2309fd
AppLICAtIOns InFORMAtIOn
atesaNACKsignalindicatingtheconversioncycleis
inprogress.
Continuous Read/Write
Oncetheconversioncycleiscomplete,theLTC2309
canbewrittentoandthenreadfromusingtherepeated
START(Sr)command.Figure10showsacyclewhich
beginswithadatawrite,arepeatedSTART,followed
byareadandconcludedwithaSTOPcommand.After
all16bitsarereadout,aconversionmaybeinitiated
byissuingaSTOPcommand.Thefollowingconver-
sionwillbeperformedusingthenewlyprogrammed
data.
S
CONVERSION NAP DATA OUTPUT CONVERSION CONVERSION NAP DATA
OUTPUT
R ACK READ 7-BIT ADDRESS P S R ACK
2309 F09
READ 7-BIT ADDRESS P
Figure 9. Consecutive Reading with the Same Configuration
Continuous Read
Inapplicationswherethesameinputchannelissampled
eachcycle,conversionscanbecontinuouslyperformed
andreadwithoutawritecycle(seeFigure9).TheD
IN

wordremainsunchangedfromthelastvaluewritten
intothedevice.Ifthedevicehasnotbeenwrittento
sincepower-up,theD
IN
worddefaultstoall0s(S/D=
O/S=S0=S1=UNI=SLP=0).Attheendofaread
operation,aSTOPconditionmaybegiventostartanew
conversion.Attheconclusionoftheconversioncycle,
thenextresultmaybereadusingthemethoddescribed
above.Iftheconversioncycleisnotconcludedanda
validaddressselectsthedevice,theLTC2309gener-
S
CONVERSION NAP DATA INPUT ADDRESS CONVERSION DATA
OUTPUT
W ACK WRITE 7-BIT ADDRESS Sr R ACK
2309 F10
READ 7-BIT ADDRESS P
Figure 10. Write, Read, START Conversion
LTC2309
18
2309fd
AppLICAtIOns InFORMAtIOn
Synchronizing Multiple LTC2309s with a Global
Address Call
InapplicationswhereseveralLTC2309sorotherI
2
CSAR
ADCsfromLinearTechnologyCorporationareusedon
thesameI
2
Cbus,allconverterscanbesynchronized
throughtheuseofaglobaladdresscall.Priortoissu-
ingtheglobaladdresscall,allconvertersmusthave
completedaconversioncycle.Themasterthenissues
aSTART,followedbytheglobaladdress1101011,and
awriterequest.Allconverterswillbeselectedandac-
knowledgetherequest.Themasterthensendsawrite
byte(optional)followedbytheSTOPcommand.Thiswill
updatethechannelselection(optional)andsimultane-
ouslyinitiateaconversionforallADCsonthebus(see
Figure11).Inordertosynchronizemultipleconverters
withoutchangingthechannel,aSTOPcommandmay
be issued after acknowledgement of the global write
command.Globalreadcommandsarenotallowedand
theconverterswillNACKaglobalreadrequest.
Nap Mode
TheADCentersnapmodeafteraconversioniscom-
plete(t
CONV
)iftheSLPbitissettoalogic0.Thesup-
plycurrentdecreasesto210Ainnapmodebetween
conversions, thereby reducing the average power
dissipationasthesampleratedecreases.Forexample,
the LTC2309 draws an average of 300A at a 1ksps
samplingrate.TheLTC2309keepsonlythereference
(V
REF
)andreferencebuffer(REFCOMP)circuitryactive
wheninnapmode.
Sleep Mode
TheADCenterssleepmodeafteraconversioniscom-
plete(t
CONV
)iftheSLPbitissettoalogic1.TheADC
drawsonly7Ainsleepmode,providedthatnoneof
thedigitalinputsareswitching.WhentheLTC2309is
properlyaddressed,theADCisreleasedfromsleepmode
andrequires200ms(t
REFWAKE
)towakeupandcharge
therespective2.2Fand10Fbypasscapacitorsonthe
V
REF
andREFCOMPpins.Anewconversionshouldnot
beinitiatedbeforethistime,asshowninFigure12.
S
SDA
SCL
CONVERSION NAP
LTC2309
DATA OUTPUT CONVERSION OF ALL LTC2309s
W ACK WRITE (OPTIONAL) GLOBAL ADDRESS P
LTC2309 LTC2309
2309 F11
Figure 11. Synchronous Multiple LTC2309s with a Global Address Call
S
CONVERSION SLEEP t
REFWAKE
CONVERSION
R/W ACK 7-BIT ADDRESS P
2309 F12
Figure 12. Exiting Sleep Mode and Starting a New Conversion
LTC2309
19
2309fd
AppLICAtIOns InFORMAtIOn
Acquisition
TheLTC2309beginsacquiringtheinputsignalatdif-
ferentinstancesdependingonwhetherareadorwrite
operation is being performed. If a read operation is
beingperformed,acquisitionoftheinputsignalbegins
ontherisingedgeofthe9thclockpulsefollowingthe
addressframe,asshowninFigure13a.
Ifawriteoperationisbeingperformed,acquisitionof
theinputsignalbeginsonthefallingedgeofthesixth
clockcycleaftertheD
IN
wordhasbeenshiftedin,as
shown in Figure 13b. The LTC2309 will acquire the
signalfromtheinputchannelthatwasmostrecently
programmedbytheD
IN
word.Aminimumof240nsis
requiredtoacquiretheinputsignalbeforeinitiatinga
newconversion.
1 2
A6 SDA
SCL
A5 A4 A3 A2 A1 A0 R/W
3 4 5 6 7 8 9 1 2
B11
ACQUISITION BEGINS
t
ACQ
2309 F13a
B10
1 2
A2 A1 A0 R/W SDA
SCL
S/D O/S S1 S0 UNI X X
3 4 5 5 6 7 8 9 6 7 8 9
ACQUISITION BEGINS
t
ACQ
2309 F13b
SLP
Figure 13a. Timing Diagram Showing Acquisition During a Read Operation
Figure 13b. Timing Diagram Showing Acquisition During a Write Operation
INPUT VOLTAGE (V)
0V
O
U
T
P
U
T

C
O
D
E

(
T
W
O

S

C
O
M
P
L
E
M
E
N
T
)
1
LSB
2309 F14
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FS/2 1LSB FS/2
FS = 4.096V
1LSB = FS/2
12
1LSB = 1mV
INPUT VOLTAGE (V)
O
U
T
P
U
T

C
O
D
E
2309 F15
111...111
111...110
100...001
100...000
000...000
000...001
011...110
011...111
FS 1LSB 0V
UNIPOLAR
ZERO
FS = 4.096V
1LSB = FS/2
12
1LSB = 1mV
Figure 14. Bipolar Transfer Characteristics (2s Complement) Figure 15. Unipolar Transfer Characteristics (Straight Binary)
LTC2309
20
2309fd
AppLICAtIOns InFORMAtIOn
Figure 16a. Top Silkscreen
2309 F16a
Board Layout and Bypassing
Toobtainthebestperformance,aprintedcircuitboardwith
asolidgroundplaneisrequired.Layoutfortheprinted
board should ensure digital and analog signal lines are
separatedasmuchaspossible.Careshouldbetakennot
torunanydigitalsignalsalongsideananalogsignal.All
analoginputsshouldbeshieldedbyGND.V
REF
,REFCOMP
andV
DD
shouldbebypassedtothegroundplaneasclose
tothepinaspossible.Maintainingalowimpedancepath
for the common return of these bypass capacitors is
essential to the low noise operation of the ADC. These
tracesshouldbeaswideaspossible.SeeFigures16a-e
forasuggestedlayout.
LTC2309
21
2309fd
2309 F16b
Figure 16b. Layer 1 Component Side
AppLICAtIOns InFORMAtIOn
Figure 16c. Layer 2 Ground Plane
2309 F16c
LTC2309
22
2309fd
AppLICAtIOns InFORMAtIOn
Figure 16d. Layer 3 Power Plane
2309 F16d
Figure 16e. Layer Back Solder Side
2309 F16e
LTC2309
23
2309fd
pACKAGe DesCRIptIOn
UF Package
24-Lead Plastic QFN (4mm 4mm)
(ReferenceLTCDWG#05-08-1697)
4.00 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 0.10
24 23
1
2
BOTTOM VIEWEXPOSED PAD
2.45 0.10
(4-SIDES)
0.75 0.05 R = 0.115
TYP
0.25 0.05
0.50 BSC
0.200 REF
0.00 0.05
(UF24) QFN 0105
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.70 0.05
0.25 0.05
0.50 BSC
2.45 0.05
(4 SIDES)
3.10 0.05
4.50 0.05
PACKAGE OUTLINE
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 s 45 CHAMFER
LTC2309
24
2309fd
F Package
20-Lead Plastic TSSOP (4.4mm)
(ReferenceLTCDWG#05-08-1650)
F20 TSSOP 0204
0.09 0.20
(.0035 .0079)
0 8
0.25
REF
0.50 0.75
(.020 .030)
4.30 4.50**
(.169 .177)
1 3 4 5 6 7 8 9 10
11 12 14 13
6.40 6.60*
(.252 .260)
20 19 18 17 16 15
1.10
(.0433)
MAX
0.05 0.15
(.002 .006)
0.65
(.0256)
BSC
6.40
(.252)
BSC
0.19 0.30
(.0075 .0118)
TYP
2
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
RECOMMENDED SOLDER PAD LAYOUT
0.45 0.05 0.65 BSC
4.50 0.10
6.60 0.10
1.05 0.10
pACKAGe DesCRIptIOn
LTC2309
25
2309fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresenta-
tionthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
ReVIsIOn HIstORY
REV DATE DESCRIPTION PAGE NUMBER
D 7/10 RevisedBlockDiagram 1
ChangedAV
DD
andDV
DD
pinstoV
DD
only 2,4-9,20
RevisedNote2 5
ConsolidatedAV
DD
andDV
DD
intoV
DD
andrevisedV
REF
andREFCOMPpindescriptionsinPinFunctionssection 7,8
RevisedFigures6band6candInternalReferenceparagraph,andaddedtexttoI
2
CInterfaceinApplications
Informationsection
13,14
ChangedNAKtoNACKinFigure8a 15
RevisedTypicalApplication 26
(Revision history begins at Rev D)
LTC2309
26
2309fd
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900

FAX: (408) 434-0507

www.linear.com LINEAR TECHNOLOGY CORPORATION 2008


LT 0710 REV D PRINTED IN USA
ReLAteD pARts
tYpICAL AppLICAtIOn
PART NUMBER DESCRIPTION COMMENTS
LTC1417 14-Bit,400kspsSerialADC 20mW,UnipolarorBipolar,InternalReference,SSOP-16Package
LTC1468/LTC1469 Single/Dual90MHz,22V/s,16-BitAccurate
OpAmps
LowInputOffset:75V/125V
LTC1609 16-Bit,200kspsSerialADC 65mW,ConfigurableBipolarandUnipolarInputRanges,5VSupply
LTC1790 MicropowerLowDropoutReference 60ASupplyCurrent,10ppm/C,SOT-23Package
LTC1850/LTC1851 10-Bit/12-Bit,8-Channel,1.25MspsADCs ParallelOutput,ProgrammableMUXandSequencer,5VSupply
LTC1852/LTC1853 10-Bit/12-Bit,8-Channel,400kspsADCs ParallelOutput,ProgrammableMUXandSequencer,3Vor5VSupply
LTC1860/LTC1861 12-Bit,1-/2-Channel250kspsADCsinMSOP 850Aat250ksps,2Aat1ksps,SO-8andMSOPPackages
LTC1860L/LTC1861L 3V,12-bit,1-/2-Channel150kspsADCs 450Aat150ksps,10Aat1ksps,SO-8andMSOPPackages
LTC1863/LTC1867 12-/16-Bit,8-Channel200kspsADCs 6.5mW,UnipolarorBipolar,InternalReference,SSOP-16Package
LTC1863L/LTC1867L 3V,12-/16-bit,8-Channel175kspsADCs 2mW,UnipolarorBipolar,InternalReference,SSOP-16Package
LTC1864/LTC1865 16-Bit,1-/2-Channel250kspsADCsinMSOP 850Aat250ksps,2Aat1ksps,SO-8andMSOPPackages
LTC1864L/LTC1865L 3V,16-Bit,1-/2-Channel150kspsADCsinMSOP 450Aat150ksps,10Aat1ksps,SO-8andMSOPPackages
LTC2302/LTC2306 12-Bit,1-/2-Channel500kspsSPIADCsin
3mm3mmDFN
14mWat500ksps,Single5VSupply,SoftwareCompatiblewithLTC2308
LTC2308 12-Bit,8-Channel500kspsSPIADC 5V,InternalReference,4mm4mmQFNPackage,SoftwareCompatiblewith
LTC2302/LTC2306
LTC2453 Easy-to-Use,Ultratiny16-BitI
2
CDeltaSigmaADC 2LSBINL,50nASleepCurrent,60HzOutputRate,3mm2mmDFNPackage
LTC2487/LTC2489/
LTC2493
2-/4-ChannelEasyDriveI
2
CDeltaSigmaADCs 16-/24Bits,PGAandTemperatureSensor,15HzOutputRate,4mm3mm
DFNPackages
LTC2495/LTC2497/
LTC2499
8-/16-ChannelEasyDriveI
2
CDeltaSigmaADCs 16-/24-Bits,PGAandTemperatureSensor,15HzOutputRate,5mm7mm
QFNPackages
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
2309 TA02
I
2
C
PORT
ANALOG
INPUT
MUX
REFCOMP
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC)
INTERNAL
2.5V REF
V
DD
5V
10V
10V
10V
INPUT
SIGNAL
GND
LTC2309
0.1F
12-BIT
SAR ADC
+

2.2F
10F 0.1F
10F
1F
0.1F
47pF
7
4 5
6
8
1
9
10
100
450k
LT1790-2.5
5V
IN OUT
GND
50k
150k
450k
150k
450k
4pF
V
REF
SDA
SCL
1.7k 1.7k AD1 AD0 CH0
450k
4pF
3
2
50k

+
LT1991
Driving the LTC2309 with 10V Input Signals Using a Precision Attenuator