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Simulating Envelope Tracking with Agilent ADS a Proof of Concept Example

Andy Howard (andy_howard@agilent.com), 2/8/2012

Introduction
Many modern modulated signals have high peak-to-average power ratios (PAPR.) Power amplifiers that must amplify these high PAPR signals, if using a fixed bias, must be operated at relatively high output power back off, to avoid greatly distorting the signal when its envelope excursion is near its peak. However, the greater the amount of back off, the lower the efficiency of the power amplifier will be. Envelope tracking is a way of overcoming this issue, by allowing the amplifiers drain bias to track the magnitude of the input signal envelope. When the input signal envelope is low, the drain bias can be reduced so the amplifier operates closer to its optimal efficiency point. This example applies envelope tracking to an old example amplifier to show techniques of using ADS for this type of design. This example is not meant to show envelope tracking applied to a state-of-the-art power amplifier. It is meant to educate designers on a method (but certainly not the only one) of simulating envelope tracking with ADS.

Characterizing the Power Amplifier


Prior to applying envelope tracking to a power amplifier, you want to see how its PAE varies with output power, with the drain bias voltage swept as a parameter. The HB1ToneGComp1swp schematic in the 0. Testing the Amplifier with a CW Signal to Obtain Shaping Curve folder simulates the power amplifier as a function of drain bias voltage. This schematic and data display are from an updated Amplifier DesignGuide that may be downloaded from the Agilent EEsof Knowledge Center: http://edocs.soco.agilent.com/display/eesofkc/amplifier+DesignGuide+Enhancements+for+post++ADS+2011_10+Release This simulation setup was generated by selecting (from any schematic) DesignGuide > Amplifier > 1Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion at X-dB Gain Compression (w/PAE) vs. 1 Param. Here, we are sweeping the drain bias voltage to see how gain and gain compression vary. The gate bias voltage has been changed from 2 to 1.75 V, so the amplifier will operate a little more efficiently, and the 1 uH inductors in the gate and drain lines have been removed, since the amplifier subcircuit includes bias inductors.

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The HB1ToneGComp1swp data display, Spectrum, Gain, Harmonics tab shows (among many things) a power-added efficiency versus fundamental output power plot:

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The curves (increasing drain bias, from left to right) show how, for lower output powers, the PAE increases as the drain bias is decreased. For example, the fourth curve from the left (drain bias 3 Volts) indicates that if this bias could be used when the input power is near 22 dBm, the PAE could be about 40 % versus about 23% with a fixed drain bias of 6 Volts. The Gain and Gain Compression plot shows how these vary as a function of the output power and drain bias:

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The X-dB Gain Compression Data tab shows the same data, but also presents the data at a specified level of gain compression. Here, 1.5 dB of gain compression (relative to the maximum gain point) has been specified:

The gain values at the 1.5 dB gain compression points (pink dots in the above plot) are the data that will be used to shape the amplifiers drain bias voltage.

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Implementing Envelope Tracking Using Behavioral Model Components


This is a block diagram for simulating envelope tracking. In this example, the sampling of the input signal power, applying the shaping, and modulating the drain voltage are done using ideal, behavioral components, but non-idealities could be introduced.

To carry out an envelope tracking simulation, we have to Generate a modulated signal Implement a method of sampling the input signal power Determine the shaping curve to use Implement a method of modulating the drain voltage

For purposes of illustration, an LTE signal will be used as the modulated signal. We used the LTE_UL_TxSpectrum schematic from the LTE/LTE_FDD_UL_Tx_wrk ADS example to generate the modulated signal. On this schematic (not included in this example workspace), OversamplingOption was increased from 0 to 2 to give a signal sampled with finer resolution, and MappingType was changed from 0 (QPSK) to 1 (16 QAM), which slightly increases the peak-to-average power ratio. The generated waveform has the trajectory diagram, spectrum, and power distribution shown.

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Certainly there are many different settings for this signal, and you may want to see how well envelope tracking works with different modulated signals. Now that we have generated a modulated signal, we need to be able to re-use it in a simulation and detects its power. This is part of the ET_Scheme_Testing in the 1. Testing the Envelope Tracking Scheme schematic:

The VtDataset source reads in the dataset from the LTE signal simulation above. This source allows you to set the carrier frequency to whatever you want via the Freq parameter. Also, the Gain parameter allows you to increase or decrease the amplitude. We need to set the simulation time step to match that of the LTE_UL_TxSpectrum dataset. We can obtain the time step from this dataset by just inserting a listing column of the time variable from this dataset into a data display:

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This shows more of the ET_Scheme_Testing schematic:

If we can detect the magnitude of the envelope of the input signal, we can compute its power. The IQ_DemodTuned component detects the real and imaginary parts of the input modulation signal. The 8 Copyright Agilent Technologies, Inc., 2012

voltage at node Env_Mag_Squared is equal to I**2 + Q**2, where I is the real part of the input signal envelope and Q is the imaginary part. This computation is carried out by the SDD (Symbolically-Defined Device) which generates a current into its port 2 = - (_v1**2+_v3**2)/50 (the - sign indicates a positive current flows out of port 2), where _v1 is the voltage at port 1 and _v3 is the voltage at port 3. This current flows into the 50 Ohm resistor, resulting in voltage Env_Mag_Squared being equal to I**2 + Q**2. We have computed the magnitude of the input signal envelope. Next we need to compute the input signal power and then generate the drain bias voltage that we want. This plot (repeated from above) shows how the drain bias could be adjusted versus the output power, to maintain a particular level of gain compression:

However, we have detected the input power, not the output power. Since we know the gain and output power at each gain compression point, we can compute the input power by just subtracting the gain from the output power. On the HB1ToneGComp1swp data display, we have added this equation, which gives the interpolated available source power at each gain compression point:

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This data is shown here in a listing column:

The same data plotted:

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This shows all of the ET_Scheme_Testing schematic:

The Detected_Pin_dBm equation is the input signal available source power in dBm. This input power is passed into the Vdrain_vs_Pin_dBm.mdf file, and the corresponding drain bias voltage is read and set equal to the Vdrain voltage. This is the Vdrain_vs_Pin_dBm.mdf file: BEGIN GMDIF % Pin_dBm(1) 10.245 11.065 12.535 14.025 15.110 15.880 16.485 17.025 17.510 17.940 END voltage(1) 1.5 2 2.5 3 3.5 4.0 4.5 5.0 5.5 6.0

In this case, we have arbitrarily decided to force the drain bias voltage to always be 1.5 Volts or higher. Therefore, 1.5 is subtracted from the value read from the file, via the Delta_Vdrain=Vdrain-1.5 11 Copyright Agilent Technologies, Inc., 2012

equation. Also, on the DataAccessComponent, we have set ExtrapMode=Constant Extrapolation. This means that if Detected_Pin_dBm is < 10.245, the voltage returned from the file remains fixed at 1.5 Volts. Similarly, if Detected_Pin_dBm > 17.9, the voltage returned from the file remains fixed at 6 Volts. Alternatively, you may allow extrapolation, and you may add artificial data points below the lowest input power and/or above the highest input power shown, to attain the extrapolation characteristics you want. This shows the simulation results with ExtrapMode=Constant Extrapolation:

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This shows the simulation results with ExtrapMode=Interpolation Mode:

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Simulating the power amplifier with a fixed drain bias


The LTE_Signal_w_Fixed_Bias simulates the power amplifier with an LTE signal and a fixed drain bias.

The simulation runs in about 46 seconds. The results show reasonable average PAE, but significant AMto-AM distortion:

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Applying Envelope Tracking to the Amplifier


The LTE_Signal_w_ET_Bias schematic applies envelope tracking to the same amplifier.

This shows improvement in PAE (the black curve is the PAE with a fixed drain bias):

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Re-running the above fixed bias and envelope tracking simulations with Gain=3 on the LTE source shows these results (with fixed bias):

and these results with envelope tracking:

There is a relative improvement in PAE when using envelope tracking. However, the AM-to-AM distortion shows the effects of gain expansion in the shaping curve (derived from the pink dots on the Transducer Power Gain and Gain Compression plot above) even more.

Potential experiments:
See how different gate bias voltages affect performance. However, changing the gate bias too far from Class A may cause distortion to become too severe. Use a different amplifier that has higher gain. Try using different shaping functions. Re-run these simulations with different modulated signals. 16 Copyright Agilent Technologies, Inc., 2012

I welcome feedback, if you have suggestions for enhancing this example, or if there are other results you want to see. My e-mail is: andy_howard@agilent.com

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