Recap: The MIPS Instruction Formats

All MIPS instructions are 32 bits long. The three instruction formats:
31 26 op 6 bits 31 op 6 bits 31 op 6 bits 26 target address 26 bits 26 rs 5 bits rs 5 bits 21 rt 5 bits 21 rt 5 bits 16 immediate 16 bits 0 16 rd 5 bits 11 shamt 5 bits 6 funct 6 bits 0 0

ECE4680 Computer Organization and Architecture Designing Single Cycle Control

R-type I-type J-type

How to design a controller to produce signals to control the datapath

The different fields are: op: operation of the instruction rs, rt, rd: the source and destination registers specifier shamt: shift amount funct: selects the variant of the operation in the op field address / immediate: address offset or immediate value target address: target address of the jump instruction

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Recap: The MIPS Subset

ADD and subtract add rd, rs, rt sub rd, rs, rt
31 26 op 6 bits 21 rs 5 bits 16 rt 5 bits immediate 16 bits 0 31 op 6 bits 26 rs 5 bits 21 rt 5 bits 16 rd 5 bits 11 shamt 5 bits 6 funct 6 bits 0

Recap: A Single Cycle Datapath

We have everything except control signals (underline) Todays lecture will show you how to generate the control signals
Branch Rd RegDst Rt Rs 5 5 busA 32 0 Mux ALU Rt Jump Clk Instruction Fetch Unit Instruction<31:0> <11:15> <21:25> <16:20> <0:15>

OR Imm: ori rt, rs, imm16 LOAD and STORE lw rt, rs, imm16 sw rt, rs, imm16 BRANCH: beq rs, rt, imm16 JUMP: j target
31

1 Mux 0 RegWr 5 ALUctr

Rs Zero

Rt

Rd

Imm16 MemtoReg 0 Mux

busW 32 Clk

Rw Ra Rb 32 32-bit Registers busB 32 Extender

MemWr

32 32 WrEn Adr Data Memory

Data In 32 Clk

1 32 ALUSrc

26 op 6 bits target address 26 bits

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imm16

16

ExtOp
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The Big Picture: Where are We Now?

The Five Classic Components of a Computer
Processor Input Control Memory Datapath

RTL: The ADD Instruction

31 op 6 bits 26 rs 5 bits 21 rt 5 bits 16 rd 5 bits 11 shamt 5 bits 6 funct 6 bits 0

add

rd, rs, rt Fetch the instruction from memory The actual operation Calculate the next instructions address

mem[PC]
Output

R[rd] <- R[rs] + R[rt] PC <- PC + 4

Todays Topic: Designing the Control for the Single Cycle Datapath A note: 2nd step and 3rd step can be done in parallel.

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Instruction Fetch Unit at the Beginning of Add / Subtract

Fetch the instruction from Instruction memory: Instruction This is the same for all instructions
30 Addr<31:2> PC<31:28> Target 4 Instruction<25:0> 26 PC Clk imm16 Instruction<15:0> 16
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The Single Cycle Datapath during Add and Subtract

31 26 op rs 21 rt 16 rd 11 shamt 6 funct 0

mem[PC]

R[rd] <- R[rs] + / - R[rt]

Branch = 0 30 00 30 1 Mux 0 Addr<1:0> Instruction Memory 32 Rd RegDst = 1 Rt Rs 5 5 busA 32 0 Mux ALU Jump = 0 Clk Rt Instruction Fetch Unit ALUctr = Add or Subtract Instruction<31:0> <11:15> <21:25> <16:20> <0:15>

1 Mux 0

RegWr = 1 5 busW 32 Clk

Rs Zero

Rt

Rd

Imm16 MemtoReg = 0

30 1

0 30 Adder Mux

1 30

Jump = previous Instruction<31:0>

Rw Ra Rb 32 32-bit Registers busB 32 Extender

MemWr = 0 0 Mux 32

Instruction Fetch Unit at the End of Add and Subtract

PC <- PC + 4 This is the same for all instructions except: Branch and Jump
30 Addr<31:2> PC<31:28> Target 4 Instruction<25:0> 26 PC Clk imm16 Instruction<15:0> 16
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Adder SignExt 30

32 WrEn Adr

1 32

imm16 Branch = previous Zero = previous

Data In 32 Clk

16

Data Memory

ALUSrc = 0 ExtOp = x
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The Single Cycle Datapath during Or Immediate

31 op 26 rs 21 rt 16 immediate 0

R[rt] <- R[rs] or ZeroExt[Imm16]

Branch = 0 Instruction<31:0> <11:15> Instruction Fetch Unit <21:25> <16:20> <0:15>

30 00 30 1 Mux 0

Addr<1:0> Instruction Memory 32

Rd RegDst = 0

Rt Rs 5 5

Jump = 0 Clk Rt busA 32 0 Mux

1 Mux 0 ALUctr = Or

RegWr = 1 5 busW 32 Clk

Rs Zero ALU

Rt

Rd

Imm16 MemtoReg = 0

30 1

0 30 Adder Mux

1 30

Jump = 0

Instruction<31:0>

Rw Ra Rb 32 32-bit Registers busB 32 Extender

MemWr = 0 0 Mux 32

The Single Cycle Datapath during Load

31 op 26 rs 21 rt 16 immediate 0

R[rt] <- Data Memory {R[rs] + SignExt[imm16]}

Branch = 0 Rd RegDst = 0 Rt Rs 5 5 busA 32 0 Mux ALU Jump = 0 Clk Rt Instruction Fetch Unit ALUctr = Add Instruction<31:0> <11:15> <21:25> <16:20> <0:15>

Adder SignExt 30

32 WrEn Adr

1 32

imm16 Branch = 0 Zero = x

Data In 32 Clk

16

Data Memory

ALUSrc = 1 ExtOp = 0
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The Single Cycle Datapath during Store

31 op 26 rs 21 rt 16 immediate 0

Data Memory {R[rs] + SignExt[imm16]} <- R[rt]

Branch = 0 Rd RegDst = x Rt Rs 5 5 busA 32 0 Mux ALU Jump = 0 Clk Rt Instruction Fetch Unit ALUctr = Add Instruction<31:0> <11:15> <21:25> <16:20> <0:15>

1 Mux 0

1 Mux 0

RegWr = 1 5 busW 32 Clk

Rs Zero

Rt

Rd

Imm16 MemtoReg = 1

RegWr = 0 5 busW

Rs Zero

Rt

Rd

Imm16 MemtoReg = x

Rw Ra Rb 32 32-bit Registers busB 32 Extender

MemWr = 0 0 Mux 32 Clk

32 WrEn Adr

Rw Ra Rb 32 32-bit Registers busB 32 Extender

MemWr = 1 0 Mux 32

32 WrEn Adr

1 32 imm16 16

1 32

imm16

Data In 32 Clk

16

Data Memory

1 32

Data In 32 Clk

Data Memory

ALUSrc = 1 ExtOp = 1
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ALUSrc = 1 ExtOp = 1
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The Single Cycle Datapath during Branch

31 op 26 rs 21 rt 16 immediate 0

Instruction Fetch Unit at the End of Branch

31 op 26 rs 21 rt 16 immediate 0

if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0

Branch = 1 Rd RegDst = x Rt Rs 5 5 5 Jump = 0 Clk Rt Instruction Fetch Unit ALUctr = Subtract Instruction<31:0> <11:15> <21:25> <16:20> <0:15>

if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4

30 Addr<31:2> PC<31:28> Target Instruction<25:0> PC 30 1 Clk imm16 Instruction<15:0> 16 Adder 4 30 26 0 30 Adder Mux 30 00 1 Mux Addr<1:0> Instruction Memory 32

1 Mux 0

RegWr = 0

Rs Zero

Rt

Rd

Imm16 MemtoReg = x

busW 32 Clk

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr = 0 0 Mux 32

ALU

32 WrEn Adr

1 30

Jump = 0

Instruction<31:0>

Mux Data In 32 Clk

SignExt

imm16

16

Data Memory

30 Assume Zero = 1 to see the interesting case. Branch = 1 Zero = 1

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ALUSrc = 0 ExtOp = x
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The Single Cycle Datapath during Jump

31 op 26 target address 0

Instruction Fetch Unit at the End of Jump

31 op 26 target address 0

Nothing to do! Make sure control signals are set correctly!

Branch = 0 Rd RegDst = x Rt Rs 5 5 Zero ALU MemWr = 0 0 Mux 32 WrEn Adr Data In 32 Clk ALUSrc = x ExtOp = x
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PC <- PC<31:29> concat target<25:0> concat 00

30 <0:15> Addr<31:2> PC<31:28> Target Instruction<25:0> PC 30 1 Clk imm16 Instruction<15:0> 16 Adder 4 30 26 0 30 Adder Mux 30 00 1 Mux Addr<1:0> Instruction Memory 32 <11:15>

Instruction<31:0> Instruction Fetch Unit ALUctr = x <21:25> <16:20>

Jump = 1 Clk Rt

1 Mux 0

RegWr = 0 5 busW 32 Clk

Rs

Rt

Rd

Imm16 MemtoReg = x

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

32

1 30

Jump = 1

Instruction<31:0>

Mux

SignExt

imm16

16

Data Memory

30

Branch = 0
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Zero = x
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A Summary of the Control Signals

See Appendix A RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUctr<2:0> 31 R-type I-type J-type
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The Concept of Local Decoding

op RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop<N:0> 00 0000 R-type 1 0 0 1 0 0 0 x R-type 00 1101 10 0011 10 1011 00 0100 00 0010 ori 0 1 0 1 0 0 0 0 Or lw 0 1 1 1 0 0 0 1 Add sw x 1 x 0 1 0 0 1 Add beq x 0 x 0 0 1 0 x Subtract jump x x x 0 0 0 1 x xxx

We Dont Care :-) func 10 0000 10 0010 op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 add 1 0 0 1 0 0 0 x Add sub 1 0 0 1 0 0 0 x Subtract 21 rs rs rt rt target address ori 0 1 0 1 0 0 0 0 Or 16 rd lw 0 1 1 1 0 0 0 1 Add 11 shamt immediate sw x 1 x 0 1 0 0 1 Add 6 funct beq x 0 x 0 0 1 0 x Subtract jump x x x 0 0 0 1 x xxx

func 26 op op op 0 add, sub ori, lw, sw, beq jump

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op 6

Main Control

6 ALUop N

ALU Control (Local)

ALUctr 3 ALU
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The Encoding of ALUop

op 6 Main Control func 6 ALUop N ALU Control (Local) ALUctr 3

The Decoding of the func Field

func op 6 Main Control 6 ALUop N ori Or 0 10 16 rt rd ALU Control (Local) ALUctr 3

How many bits?

In this exercise, ALUop has to be 2 bits wide to represent: (1) R-type instructions I-type instructions that require the ALU to perform: (2) Or, (3) Add, and (4) Subtract

ALUop (Symbolic)
Why not consider J-type?

R-type R-type 1 00 21 rs

lw Add 0 00 11

sw Add 0 00 6 shamt

beq Subtract 0 01

jump xxx xxx 0

ALUop<2:0> 31 R-type op 26

To implement the full MIPS ISA, ALUop hat to be 3 bits to represent: (1) R-type instructions I-type instructions that require the ALU to perform: (2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi)
R-type R-type 1 00 ori Or 0 10 lw Add 0 00 sw Add 0 00 jump Subtract xxx xxx 0 01
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funct

Recall ALU Homework (also P. 286 text): funct<5:0> 10 0000 10 0010 10 0100 10 0101 10 1010
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Instruction Operation add subtract

ALUctr

ALUctr<2:0> 000 001 010 110 111

ALU Operation Add Subtract And Or Set-on-less-than

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ALU

beq

ALUop (Symbolic) ALUop<2:0>

ECE4680 Control.19

and or set-on-less-than

The Truth Table for ALUctr

R-type ALUop (Symbolic) R-type ALUop<2:0> 1 00 ori Or 0 10 lw Add 0 00 sw Add 0 00 beq Subtract 0 01

funct<3:0> 0000 0010 0100 0101 1010

Instruction Op. add subtract and or set-on-less-than

The Logic Equation for ALUctr<0>

ALUop bit<2> bit<1> bit<0> 0 1 1 x x x 1 x x func bit<3> bit<2> bit<1> bit<0> x 0 1 x 0 0 x 1 1 x 0 0 ALUctr<0> 1 1 1

ALUop bit<2> bit<1> bit<0> 0 0 0 1 1 1 1 1 0 x 1 x x x x x 0 1 x x x x x x

func bit<3> bit<2> bit<1> bit<0> x x x 0 0 0 0 1 x x x 0 0 1 1 0 x x x 0 1 0 0 1 x x x 0 0 0 1 0

ALU Operation Add Subtract Or Add Subtract And Or Set on <

ALUctr bit<2> bit<1> bit<0> 0 0 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 0 1

This makes func<3> a dont care

ALUctr<0> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0>

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The Logic Equation for ALUctr<1>

ALUop bit<2> bit<1> bit<0> 0 1 1 1 1 x x x x x x x func bit<3> bit<2> bit<1> bit<0> ALUctr<1> x 0 0 1 x 1 1 0 x 0 0 1 x 0 1 0 1 1 1 1

The Logic Equation for ALUctr<2>

ALUop bit<2> bit<1> bit<0> 0 1 1 1 x x x x x func bit<3> bit<2> bit<1> bit<0> ALUctr<2> x 0 1 x 1 0 x 0 1 x 1 0 1 1 1

ALUctr<2> = !ALUop<2> & ALUop<1> ALUctr<1> = !ALUop<2> & ALUop<1> + ALUop<2> & !func<3> & func<2> & !func<1> ALUop<2> & func<3> & !func<2> & func<1> & !func<1> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

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The ALU Control Block

func 6 ALUop 3 ALU Control (Local) ALUctr 3

The Truth Table for the Main Control

RegDst op 6 ALUSrc Main Control func 6 ALU Control (Local)

:
ALUop 3 00 0000 R-type 1 0 0 1 0 0 0 x R-type 1 0 0 ori 0 1 0 1 0 0 0 0 Or 0 1 0 lw 0 1 1 1 0 0 0 1 Add 0 0 0

ALUctr 3

op

00 1101 10 0011 10 1011 00 0100 00 0010 sw x 1 x 0 1 0 0 1 Add 0 0 0 beq x 0 x 0 0 1 0 x Subtract 0 0 1 jump x x x 0 0 0 1 x xxx x x x
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ALUctr<0> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0> ALUctr<1> = !ALUop<2> & ALUop<1> + ALUop<2> & !func<3> & func<2> & !func<1> + ALUop<2> & func<3> & !func<2> & func<1> & !func<1> ALUctr<2> = !ALUop<2> & ALUop<1> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop (Symbolic) ALUop <2> ALUop <1> ALUop <0>

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The Truth Table for RegWrite

op RegWrite 00 0000 R-type 1 00 1101 10 0011 10 1011 00 0100 00 0010 ori lw sw beq jump 1 1 0 0 0

PLA Implementation of the Main Control

op<5>

..

op<5>

..

op<5>

..

op<5>

..

op<5>

..
<0>

op<5>

..
op<0>

<0>

<0>

<0>

<0>

RegWrite = R-type + ori + lw = !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0> + !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0> + op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0>
op<5>

(R-type) (ori) (lw)

R-type

ori

lw

sw

beq

jump

RegWrite ALUSrc RegDst MemtoReg MemWrite Branch Jump ExtOp

..

op<5>

..

op<5>

..

op<5>

..

op<5>

..
<0>

op<5>

..
op<0>

<0>

<0>

<0>

<0>

R-type

ori

lw

sw

beq

jump RegWrite

ALUop<2> ALUop<1> ALUop<0>

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Putting it All Together: A Single Cycle Processor

ALUop op 6 Instr<31:26> RegDst Main Control ALUSrc 3 func Instr<5:0> 6 ALU Control ALUctr 3

How is this Different from a Real MIPS Processor?

The effect of load in a real MIPS Processor is delayed: - lw $1, 100 ($2) // Load Register R1 - add $3, $1, $0 // Move old R1 into R3 - add $4, $1, $0 // Move new R1 into R4 The effect of load in our single cycle processor is NOT delayed - lw $1, 100 ($2) // Load Register R1 add $3, $1, $0 // Move new R1 into R3

:
Rt Rs 5 5 Rt

Branch Jump Clk Instruction Fetch Unit

Instruction<31:0> <11:15> <21:25> <16:20> <0:15>

Rd RegDst

1 Mux 0 RegWr 5 ALUctr busA 32 0 Mux ALU

Rt Zero

Rs

Rd

Imm16 MemtoReg 0 Mux

busW 32 Clk

Rw Ra Rb 32 32-bit Registers busB 32 Extender

MemWr

32 32 WrEn Adr

The effect of branch and jump in a real MIPS Processor is delayed: - Instruction Address: 0x00 j 1000 - Instruction Address: 0x04 add $1, $2, $3 Instruction Address: 0x1000 sub $1, $2, $3 Branch and jump in our single cycle processor is NOT delayed - Instruction Address: 0x00 j 1000 - Instruction Address: 0x1000 sub $1, $2, $3

1 32 ALUSrc

imm16 Instr<15:0>

Data In 32 Clk

16

Data Memory

ExtOp
ECE4680 Control.29 2003-3-17 ECE4680 Control.30 2003-3-17

Worst Case Timing

Clk PC Old Value Clk-to-Q New Value Old Value Old Value Old Value Old Value Old Value Old Value Old Value Delay through Extender & Mux Old Value Old Value Data Memory Access Time busW
ECE4680 Control.31

Drawback of this Single Cycle Processor

Long cycle time: Cycle time must be long enough for the load instruction: PCs Clock -to-Q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time +
Register Write Occurs

Rs, Rt, Rd, Op, Func ALUctr ExtOp ALUSrc MemtoReg RegWr busA busB Address

Instruction Memory Access Time New Value Delay through Control Logic New Value New Value New Value New Value New Value

Register File Setup Time + Clock Skew Cycle time is much longer than needed for all other instructions

Register File Access Time New Value New Value ALU Delay New Value New
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Old Value

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Where to get more information?

Chapter 5.1 to 5.3 of your text book: Daid Patterson and John Hennessy, Computer Organization & Design: The Hardware / Software Interface, Morgan Kaufman Publishers, San Mateo, California, 1998. For a reference on the MIPS architecture: Gerry Kane, MIPS RISC Architecture, Prentice Hall.

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