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# Preface

three-phase pulse width modulated voltage waveforms (leg, line and common mode voltages) generated by a power converter are analysed. In the second part of this chapter, some methods to extract capacitive couplings between windings, stator and rotor are described. Finally, a high frequency model of an AC motor is discussed to calculate shaft voltage and conducted emission noise. Authors: Dr. Jafar Adabi Firouzjaee, Prof. Firuz Zare

Contents
1 Multilevel Converter Topologies 1.1 Symmetrical Multilevel Converters 2 1.1.1 Introduction 2 1.1.2 Diode-clamped Converter Topology 7 1.1.2.1 Single-phase Diode-clamped Converter 13 1.1.2.2 Three-phase Three-level Diode-clamped Converter 19 1.1.2.3 Capacitor Voltage Control in Diode-clamped Converters 23 1.1.3 Flying Capacitor Converter Topology 29 1.1.3.1 Single-phase Flying Capacitor Converter 34 1.1.3.2 Three-phase Three-level Flying Capacitor Converter 39 1.1.3.3 Capacitor Voltage Control in Flying Capacitor Converter 41 1.1.4 Cascade Converter Topology 45 1.1.4.1 Three-Phase Five-level Cascade Converter 50 1.1.5 High-level Multilevel Topologies 51 1.1.5.1 Diode Clamped Converter 52 1.1.5.2 Flying Capacitor Converter 58 1.1.5.3 Cascade Converter Structure 61 1.1.6 Conclusions 64 1.2 Asymmetrical Multilevel Converters 65 1.2.1 Introduction 65 1.2.2 Unequal DC Link Configuration for Multilevel Converters 67 1.2.3 Unequal DC Link Design Considerations 73 1.2.3.1 Adjacent Switching States 73 1.2.3.2 Capacitor Voltage Balancing 74 1.2.3.3 Voltage Rating of Switching Components 74 1.2.4 Asymmetrical Diode-clamped Converters 74 1.2.4.1 Adjacent Switching States 75 1.2.4.2 Capacitor Voltage Balancing 82 1.2.4.3 Voltage Rating of Switching Components 87 1.2.5 Asymmetrical Flying Capacitor Converter 89 1.2.5.1 Adjacent Switching States 90 1.2.5.2 Capacitor Voltage Balancing 93 1.2.5.3 Voltage Rating of Switching Components 94

3.4.3 A three-phase Inverter Supplied with a Single-phase Diode Rectifier 216 3.4.3.1 Positive Half a Cycle 218 3.4.3.2 Negative Half a Cycle 218 3.4.3.3 Common Mode Voltage Reduction Strategy 222 3.4.4 An AC-DC-AC Motor Drive 223 3.5 Modelling of Electric Motors for Shaft Voltage and EMI Analysis 226 3.5.1 Parasitic Elements 227 3.5.2 Extraction of Parasitic Elements 233 3.5.2.1 Test 1: Input Impedance across Windings and Stator (motor frame) to Extract Cws1 by Removing the Rotor 235 3.5.2.2 Test 2: Impedance of Windings to Extract Cw, Rloss and L 239 3.5.2.3 Test 3: Input Impedance across Rotor and Stator to Extract Crs and Cwr1 240 3.5.2.4 Test 4: Input Impedance across Windings and Rotor to Extract Crs and Cwr1 242 3.5.2.5 Test 5: Input Impedance across the Phases to Extract Cww 243 3.5.3 Simplification of the Model for Different Analysis 244 3.6 Calculation of Capacitive Coupling in AC Machines in order to Reduce Shaft Voltage and Leakage Current 249 3.6.1 The Capacitive Coupling between Stator and Winding (Cws) 252 3.6.2 The Capacitive Coupling between Rotor and Stator (Crs) 253 3.6.3 The Capacitive Coupling between Rotor and Winding (Cwr) 255

Chapter 1:
Multilevel Converter Topologies

## 1.1 Symmetrical Multilevel Converters

1.1.1 Introduction
The growing attraction of high and medium power applications in utility, industrial, and renewable energy systems has increased a demand for high and medium power converters. However, due to the maximum blocking voltage rating of switches, it is troublesome to connect only one power semiconductor switch directly to high voltage. As a result, a multilevel power converter structure has been introduced as an alternative for high and medium voltage applications.

The basic concept of power conversion in multilevel converters is based on a series connection of switching components with several lower DC voltage sources to synthesize a staircase voltage waveform. Different energy sources or storage elements such as capacitors and batteries, or renewable energy sources such as PV panels can be considered as the DC voltage sources in various multilevel converter structures.

By neglecting the ripple on the DC link capacitor, a schematic circuit of a threephase two-level classical converter and a multilevel converter are shown in Fig.1-1, where the input DC source (Vdc) can be one of the above-mentioned sources and the capacitor voltages [Fig.1-1 (b)] meet the following condition:

## VC1 , VC2 ,,VCn VC1

1 1

Vdc Vdc

VC2 , VCn

(1-1)

According to different switching states, it is possible to achieve higher voltage levels at the output voltage by adding up the DC sources in comparison with the two-level converter. This issue has been demonstrated in Fig.1-2, where each step of the output voltage level in the multilevel converter is a fraction of the total DC link voltage of the two-level converter. Therefore, the voltage rate of the power components depends on the DC voltage source to which they are connected.

As seen in Fig.1-2, a two-level converter utilizes only one DC level (Vdc) in order to create the average of reference voltage in each switching cycle, while the multilevel converter is able to synthesis stair case output voltage using several DC link voltage levels. This is closer to a sinusoidal voltage waveform.

Synthesizing a stepped output voltage allows reduction in harmonic content of voltage waveform. In regards to harmonic spectrum of the two-level and the

multilevel converters illustrated in Fig.1-3, it is apparent that the peak of harmonic contents of the output voltage in the multilevel converter is significantly declined compared to the two-level converter. This results in increasing the quality of output waveform and reducing the size and cost of the output filter. The staircase output voltage can improve the quality of the output voltage and reduce the voltage stress (dv/dt) on switching components; this can remedy the problem associated with Electromagnetic Interference (EMI) problems. Switching losses in power converters is proportional to both the switching frequency and the voltage drop across the switching components. Therefore, the multilevel converter contributes to reducing the switching loss as it operates at a lower switching frequency and the voltage level across the semiconductor is decreased. Therefore, less switching loss or better quality are the advantages of multilevel converters compared to two-level converters.

In addition to the above merits of the multilevel converter, utilizing proper modulation technique allows possible elimination of common mode voltage generated by the converter in a motor driver system. This reduces the voltage stress on the motor bearing and increases its lifetime. This issue is discussed in the following chapters.

Three-phase two-level converter p + Phase a a Vdc b vcn(t) c _ n vbn(t) ib(t) van(t) ia(t)
aN (

-v

+ vbN(t) ic(t)

t) +
N

- vc

(t) +

(a)
Three-phase multilevel converter p + +
VC1

Phase a

+
VC2

van(t) a

ia(t)

vbn(t) ib(t) +
VC P

-v
b + vbN(t) c + vcn(t) n

Vdc

aN (

t) +
N

- vc

+ (t)

ic(t)

VCn

(b) Fig.1-1: Schematic diagram of a DC-AC converter (a) two-level classical converter and (b) multilevel converter

10

Vdc

T/2

-Vdc

(a)
Vdc 3Vdc/4 2Vdc/4 Vdc/4 0 -Vdc/4 -2Vdc/4 -3Vdc/4 -Vdc

T /2

(b) Fig.1-2: Output voltage waveform (a) two-level and (b) multilevel converter

Multilevel converters are appropriate for medium and high voltage applications. However, one of their main drawbacks is the need for a greater number of switching components; this imposes extra expense and complexity on the overall system design. Various types of multilevel converters have been proposed based on different structures of a DC link voltage to generate staircase output voltage levels. The best known multilevel topologies are diode-clamped, flying capacitor, and cascade converters. Different current and voltage control have been proposed for multilevel converters to create optimum efficiency. Although each type of multilevel

11

converter shares the advantages of multilevel voltage source converters, they may be suitable for a specific application according to their structures.

60 40

60

## Harmonic magnitude (V)

0.005 0.01 0.015 Time(S) 0.02

Voltage(V)

(a)
60
60

## Harmonic magnitude (V)

0 0.005 0.01 0.015 Time(S) 0.02

40

Voltage(V)

## 20 0 -20 -40 -60

(b) Fig.1-3: (a) A two-level converter output voltage waveform and harmonic contents and (b) multilevel converter output voltage and harmonic contents

This chapter is dedicated to describing and discussing the operation and structure of the three main multilevel converter topologies. In the first section, the basic operation of each converter is first analyzed to provide an overview of the nature of different structures with respect to the switching states and practical operations with equal DC link voltages ( VC1
VC2 ... VCn 1 ); these are termed traditional

multilevel converters or symmetrical multilevel converters. High-level multilevel converters are then analyzed in order to highlight the strengths and weaknesses of each configuration. In the second section, all the multilevel converters will be

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analyzed with unequal DC link voltages; these converters are termed asymmetrical multilevel converters.

## 1.1.2 Diode-clamped Converter Topology

One of the multilevel converter topologies that have achieved much attention in renewable energy systems is the diode-clamped multilevel converter, also known as Neutral-Point-Clamped multilevel converter. This structure was first proposed by Nabae et al. in 1980. Multilevel diode-clamped converters are widely utilized as an interface between a high DC voltage and an AC voltage in renewable energy sources in either grid connection or residential applications. A diode-clamped converter is also a common type of converter used in variable speed drives for high-power medium-voltage (2.4 kV to 13.8 kV) motors. Static Var Compensation has been presented in the literature as an alternative application for this type of converter. Basically, diode-clamped multilevel converters synthesize the small step of staircase output voltage from several series of DC capacitor voltages. Fig.1-4 (a) shows the leg structure of a three-level diode-clamped converter where the total DC link voltage is Vdc and VC1
VC2 Vdc / 2 .

The DC bus voltage is split into two voltage sources by using two DC capacitors, C 1 and C2. Each capacitor is supposed to have an equal DC voltage and each voltage stress will be limited to one capacitor level through clamping diodes (D ca1 and Dca2). This structure consists of pairs of switches, (Sa1, Sa3) and (Sa2, Sa4), which work in a complementary fashion. A single-phase and three-phase structure can be formed by the paralleling of two and three converter leg structures, respectively. A converter with more output voltage levels can be constructed by adding extra DC link capacitors and a pair of switching devices for each extra level. The load current can be positive or negative because of the phase shift between its voltage and current waveforms. Therefore, based on the load power factor, in both positive and negative output voltages, the load current can be either positive or negative. In order to work in different load power factors, switches include a MOSFET or IGBT with anti parallel diodes. This switch structure allows bidirectional current flow for positive and negative load current when the switch is turned on by its gate signal. The "on"

13

and "off' switching states of each switch are defined as 1 and 0, respectively. If the middle point of DC link voltage is regulated at half of the total input DC source

p Sa1 Da1

VC1

a

## Sa1=0 Sa2=1 Vdc/2

VC2

C2 Sa4 Da4

Sa1=0 Sa2=0 0 0 t1 t2 t3 t

(a) (b) Fig.1-4: One leg of three-level diode-clamped converter (a) circuit diagram and (b) output voltage waveform

(Vdc/2), based on three different switching states, three voltage levels can be synthesized at the output voltage of the leg structure of the three-level diodeclamped converter with respect to the point n [See Fig.1-4 (b)]. These switching states are explained in detail below. Switching state Sa1=0, Sa2=0 in (0<t t1) In this switching state, as shown in Fig.1-5, both top switches (Sa1 and Sa2) are off so that their complements Sa3 and Sa4 are on. When the load current is positive [Fig.1-5 (a)], reverse diodes Da3 and Da4 conduct and the load current loop can be provided through the load, Da3 and Da4. However, in the negative load current [Fig.1-5 (b)], Sa3 and Sa4 conduct and the current loop consists of Sa3 and Sa4 through the load. Therefore, as shown in Fig.1-4 (a), the output voltage in 0<t t1 is:

14

van(t)= 0

(1-2)

According to Fig.1-5, this switching state can not affect DC link capacitors, as capacitors C1 and C2 are not included in the current loop through the load.

+ Sa1
VC1

Da1
VC1

Da1

Da2

## + Dca2 Sa3 Da3

VC2

C2 Sa4 Da4

VC2

C2 Sa4 Da4

(a) (b) Fig.1-5: Current loop when Sa1=0, Sa2=0 (a) positive load current and (b) negative load current Switching state Sa1=0, Sa2=1 in (t1<t t2) In this switching state, the top switch Sa1 is turned off, while the other switch Sa2 is on. Therefore, the complementary switches in this leg, Sa3 and Sa4, are on and off, respectively. As shown in Fig.1-6 (a), when the load current is positive, the switch Sa2 and the clamped diode Dca1 conduct due to the polarity of the voltage across the diode and the current direction through the switch. Therefore, the current loop which consists of C2, Dca1, and Sa2 can discharge C2. On the other hand, for the negative load current [Fig.1-6 (b)], Dca2 and Sa3 conduct according to the voltage polarity and the current direction. The current loop in the negative load current consists of C2, Dca2, and Sa3 through the load and it can charge C2.

15

Assuming that the voltage ripple is negligible on the DC link capacitors ( VC1 (t ) VC1 and VC2 (t ) VC2 ), the output voltage in this switching state (t1<t t2) is: van(t)= VC1 =Vdc/2 (1-3)

+ Sa1
VC1

+
Da1

Sa1
VC1

Da1

## + Dca2 Sa3 Da3 a

VC2

C2 Sa4 Da4

VC2

C2 Sa4 Da4

n n (a) (b) Fig.1-6: Current loop when Sa1=0, Sa2=1 (a) positive load current and (b) negative load current

Switching state Sa1=1, Sa2=1 in (t2<t t3) In this switching state (as shown in Fig.1-7) both top switches, Sa1 and Sa2, are on, so that the complementary switches, Sa3 and Sa4, are off. When the load current is positive, the switches Sa1 and Sa2 conduct and the current loop consists of C1, C2, Sa1 and Sa2 [Fig.1-7 (a)]. However, for the negative load current, Da1 and Da2 conduct and the current flows through C1, C2, Da1, and Da2. Therefore, according to Fig.1-7 (b), the output voltage in t2<t t3 is:

## van(t)= VC1 + VC 2 =Vdc

(1-4)

16

Since the capacitors have been considered as the only source of the converter so far, the load current flows through DC link capacitors in this switching state and the direction of the load current may have charged or discharged the capacitors. Positive current loop can charge the DC link capacitors, while negative load current may discharge the DC link capacitors, C1 and C2. It should be mentioned that usually, in practice, battery or another kind of DC power supply is connected to the DC link capacitors. The total DC voltage does not change significantly in this switching state according to the load current direction and the capacitance value.

+ Sa1
VC1

+
Da1

Sa1
VC1

Da1

## + Dca2 Sa3 Da3 a

VC2

C2 Sa4 Da4

VC2

C2 Sa4 Da4

(a) (b) Fig.1-7: Current loop when Sa1=1, Sa2=1 (a) positive load current and (b) negative load current

Switching state Sa1=1, Sa2=0 This switching state is not considered in a diode-clamped configuration as the output voltage in this case depends on the load current. Fig.1-8 shows the current loops for the positive and the negative load currents. In the positive load current, Sa4 is on and Da3 conducts due to the direction of the current. As shown in Fig.1-8 (a), in this situation, the current loop includes Da3 and Da4 through the load and van(t)=0. In the negative load current, Da2 conducts while Sa1 is on. According to Fig.1-8 (b), the current loop contains Da1, Da2, and the DC link capacitors C1 and C2 through the load

17

in which van(t)= VC1 + VC 2 . As discussed, this switching state is not used in diodeclamped converters as the leg voltage depends on the load current.

Three possible voltage levels in one leg of the diode-clamped converter are distinguished by the three switching states. In practice, the capacitor voltage should be balances to an equal value by using a proper PWM strategy. The capacitor voltage levels under the balance conditions should be achieved as follows:
VC1 = VC 2 =Vdc/2

(1-5)

The output voltage levels at the balanced conditions are demonstrated in Table 1-1.

+ Sa1
VC1

+
Da1

Sa1
VC1

Da1

## + Dca2 Sa3 Da3 a

VC2

C2 Sa4 Da4

VC2

C2 Sa4 Da4

(a) (b) Fig.1-8: Current loop when Sa1=1, Sa2=0 (a) positive load current and (b) negative load current

Table 1-1 Possible switching states for one leg of the three-level diode-clamped converter Sa1 Sa2 van(t) 1 1 Vdc 0 1 Vdc/2 0 0 0

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## 1.1.2.1 Single-phase Diode-clamped Converter

A circuit diagram of a single-phase three-level diode-clamped converter is depicted in Fig.1-9. As shown, the single-phase configuration consists of two leg structures of the diode-clamped converter (Leg a and Leg b). As demonstrated, each leg has two pairs of switching components and two clamped diodes. However, both legs share the same DC link to generate output voltage levels.

Due to the fact that each leg of the converter can synthesize three different voltage levels based on different switching states, the output voltage of the single-phase converter can be derived from vab(t)=van(t)-vbn(t) (1-6) As an example, in the interval 0<t t1 shown in Fig.1-9 (b), assuming that (Sa1=1 and Sa2=1) in leg a and (Sb1=0, Sb2=1) in leg b, then van(t)=Vdc and vbn(t)=Vdc/2, respectively. So, the output voltage in steady state operation is vab(t)=Vdc-Vdc/2 = Vdc/2 for this switching interval. By combination of the leg switching states given in Table 1-1, 32 possible switching states can be derived for a single-phase three-level diode-clamped converter. These nine switching states can synthesize five different voltage levels at the output voltage of the single-phase converter and are demonstrated in Fig.1-9 (b) under the balance condition when VC1 = VC 2 =Vdc/2.

All the switching states associated with the five different voltage levels are summarized in Table 1-2. Switching states are distinguished based on the switching states of each leg of the converter. For instance, in the switching states 1101, the first two digits are the switching states associated with leg a, where (Sa1=1, Sa2=1) and the last two digits are the switching states of leg b where (Sb1=0, Sb2=1). The leg voltage and phase voltage waveforms of the single-phase three-level diodeclamped converter are shown in Fig.1-10. According to Table 1-2, there are some switching states which produce a same voltage level at the output voltage. These switching states are called redundant switching states. As presented in Table 1-2, in the single-phase three-level diode-clamped converter, (0000, 0101 and 1111) are the redundant switching states for the voltage level 0, (0100 and 1101) are the redundant switching states for the voltage level Vdc/2 and, finally, (0001and 0111) are the redundant switching states for the voltage level -Vdc/2. Although the

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redundant switching states can synthesize same voltage level at output voltage, they may provide different current paths through the capacitors. This issue can be used to balance the DC link capacitor voltages ( VC1 and VC 2 ) in the diode-clamped converters. This is discussed in detail later in this chapter.
p Sa1 C1 Dca1 Sa2 Da2 Dcb1 Sb2 Db2 Da1 Sb1 Db1

## C2 Sa4 Da4 Sb4 Db4

(a)
vab(t) Vdc Vdc/2 0 -Vdc/2 -Vdc

t1

t2

t3

t4

t5

t6

t7

t8

(b) Fig.1-9: Single-phase three-level diode-clamped converter (a) circuit diagram and (b) output voltage waveform

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Table 1-2

Possible switching states for the single-phase three-level diode-clamped converter Switching states van(t) vbn(t) vab(t) 0000 0 0 0 0001 0 Vdc/2 -Vdc/2 0011 0 Vdc -Vdc 0100 Vdc/2 0 Vdc/2 0101 Vdc/2 Vdc/2 0 0111 Vdc/2 Vdc -Vdc/2 1100 Vdc 0 Vdc 1101 Vdc Vdc/2 Vdc/2 1111 Vdc Vdc 0

vab(t)

vbn(t)

van(t)

Time(S)

Fig.1-10: Output voltage waveforms of the single-phase three-level diode-clamped converter; (from top to bottom) leg a voltage (van(t)), leg b voltage (vbn(t)), and phase voltage (vab(t))

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Same as the analysis for the leg structure and based on the load current direction and the voltage polarity on the switching devices, different switching components are included in the current loop for each switching state. To clarify this issue in the single-phase three-level diode-clamped converter, the current loops for two different switching states are illustrated in Fig.1-11. For the positive load current directions in Fig.1-11 (a) and Fig.1-11 (c), the switching states 0100 and 1101 can discharge C2 and C1. However, the negative load current leads to charging C1 and C2 in the switching states 0100 [Fig.1-11 (b)] and 1101 [Fig.1-11 (d)].

Modulation between adjacent voltage levels at the output voltage shown in Table 12 needs to be obtained by only one switch change. These switching states are defined as adjacent switching states. Simultaneous switching of different switches is not an immense problem when there are just a few of them happening over one cycle; however, when a switching between nonadjacent switching states occurs frequently, it becomes a critical issue because it increases the switching losses. The Fig.1-12 graph demonstrates the achievement of different voltage levels in terms of the adjacent switching states in a single-phase three-level diode-clamped converter. For modulation between levels 0 and Vdc/2, all the switching state pairs [(1111 and 1101), (0101 and 1101), (0101 and 0100), and (0000 and 0100)] can be used to follow the adjacency. Also, for a modulation between levels Vdc/2 and Vdc, adjacency occurs between the switching states (0100 and 1100) and (1101 and 1100). The same situation is true to obtain negative voltage levels.

As there is an adjacent switching state between all voltage levels, transition between different voltage levels can occur without any extra switching losses in a three-level diode-clamped converter. The redundant switching states are apparent from Fig.112, in the positive or the negative voltage levels. As shown, there are three different switching states in level 0 and two different switching states in both levels Vdc/2 and -Vdc/2. These switching states may have different effects on the DC link capacitor voltages at each particular output voltage level. This issue is clearly shown in Fig.111 for the switching states 0100 and 1101 in level Vdc/2. Therefore, when the switching state 0100 discharges C2 due to the positive load current drawn from

22

this capacitor [as shown in Fig.1-11 (a)], C1 is charged to compensate for this voltage drop as the DC link is normally connected to a constant DC source.
+ Sa1 C1 Dca1 Sa2 Da2 Dcb1 Sb2 Db2 Da1 Sb1 Db1

## C2 Sa4 Da4 Sb4 Db4

(a)

+ Sa1 C1 Dca1 Sa2 Da2 Dcb1 Sb2 Db2 Da1 Sb1 Db1

## Vdc a Dca2 Sa3 Da3 Dcb2 Sb3 Db3 b

C2 Sa4 (b)

Da4

Sb4

Db4

23

+ Sa1 C1 Dca1 Sa2 Da2 Dcb1 Sb2 Db2 Da1 Sb1 Db1

## Vdc a Dca2 Sa3 Da3 Dcb2 Sb3 Db3 b

C2 Sa4 (c)
+ Sa1 C1 Dca1 Sa2 Da2 Dcb1 Sb2 Db2 Da1 Sb1 Db1

Da4

Sb4

Db4

## C2 Sa4 Da4 Sb4 Db4

(d) Fig.1-11: Current loops in the single-phase three-level converter: Switching state 0100 (a) positive (b) negative load current; Switching state 1101 (c) positive and (d) negative load current

24

Inversely, while C2 is charged by the negative load current in 0100, C1 is discharged to keep the total DC link constant, as presented in Fig.1-11 (b). As shown in Fig.1-11 (c) and (d), opposite circumstances for the capacitor charging and discharging conditions occur for switching state 1101 to generate the same voltage level due to the reverse direction of the load current. This feature can be used as a freedom in the capacitor voltage balancing in diode-clamped converters.

1100

Vdc

0100

1101

Vdc/2

0000

0101

1111

0001

0111

-Vdc/2

0011

-Vdc

## 1.1.2.2 Three-phase Three-level Diode-clamped Converter

A three-phase three-level diode-clamped converter can be assembled by connecting three leg structures of the three-level diode-clamped converter, as shown in Fig.113. As each leg of the converter consists of three different switching states, there are 33 different switching states in the three-phase three-level diode-clamped converter. These twenty seven different switching states can produce five different voltage levels at each line output voltage which can be defined as vab(t)=van(t)-vbn(t) vbc(t)=vbn(t)-vcn(t) vca(t)=vcn(t)-van(t) (1-7)

25

All possible switching states of the three-phase three-level converter with all associated leg and line voltage levels are demonstrated in Table 1-3. It is supposed that the capacitor voltages ( VC1 and VC 2 ) can be controlled at Vdc/2. Similar to the single-phase converter, the switching states are defined based on the switching states in each leg of the converter. For instance, in the switching state 110100, the first two digits are the switching states of the leg a where (Sa1=1 and Sa2=1), two middle digits are allocated to switching states of the leg b where (Sb1=0 and Sb2=1), and the last two digits represent the switching states of the leg c where (Sc1=0 and Sc2=0).
+ p Sa1 C1 Dca1 Sa2 Da2 Dcb1 Sb2 Db2 Dcc1 Sc2 Dc2 Da1 Sb1 Db1 Sc1 Dc1

Vdc a Dca2 Sa3 Da3 Dcb2 Sb3 Db3 b Dcc2 Sc3 Dc3 c

## Fig.1-13: Three-phase three-level diode-clamped converter

According to Table 1-3, the three-phase converter has more redundant switching states at each line voltage which can be used in the control system. Fig.1-14 shows current loops through the switches and the DC link capacitors for two redundant switching states to generate voltage levels (vab(t)=Vdc/2,vbc(t)=0,vca(t)=-Vdc/2). Considering the direction of ia(t) as the positive load current for the phase a (negative load current for the other two phases), different current loops with respect to the switching states 110101 and 010000 have different effects on the DC link capacitor voltages.

26

+ ia(t) Sa1 C1 Dca1 Sa2 Da2 ia(t) a Sa3 Da3 Dcb2 Dcb1 Sb2 Db2 ib(t) b Sb3 Db3 Dcc2 Sc3 Dc3 Dcc1 Sc2 Dc2 ic(t) c Da1 Sb1 Db1 Sc1 Dc1

Vdc

ib(t)+ ic(t)

Dca2

## C2 Sa4 Da4 Sb4 Db4 Sc4 Dc4

(a)
+ Sa1 C1 Dca1 Sa2 Da2 ia(t) a Sa3 Da3 Dcb2 Sb3 Dcb1 Sb2 Db2 ib(t) b Db3 Dcc2 Sc3 Dc3 Dcc1 Sc2 Dc2 ic(t) Da1 Sb1 Db1 Sc1 Dc1

Vdc

ia(t) Dca2

C2 Sa4
ib(t)+ ic(t)

Da4

Sb4

Db4

Sc4

Dc4

(b) Fig.1-14: Current loops in a three-phase three-level converter (a) switching state 110101 and (b) switching state 010000

27

Leg voltage and phase voltage waveforms of the three-phase three-level diodeclamped converter are shown in Fig.1-15. There are three voltage levels appearing in each leg voltage of each phase. Also, five different voltage levels can be synthesized by different combinations of the three leg voltage levels to generate three-phase voltages with 120 degree phase difference.

Table 1-3

Switching states for a three-phase three-level diode-clamped converter van(t) 0 Vdc/2 Vdc 0 Vdc/2 Vdc 0 Vdc/2 Vdc 0 Vdc/2 Vdc 0 Vdc/2 Vdc 0 Vdc/2 Vdc 0 Vdc/2 Vdc 0 Vdc/2 Vdc 0 Vdc/2 Vdc vbn(t) 0 0 0 Vdc/2 Vdc/2 Vdc/2 Vdc Vdc Vdc 0 0 0 Vdc/2 Vdc/2 Vdc/2 Vdc Vdc Vdc 0 0 0 Vdc/2 Vdc/2 Vdc/2 Vdc Vdc Vdc vcn(t) 0 0 0 0 0 0 0 0 0 Vdc/2 Vdc/2 Vdc/2 Vdc/2 Vdc/2 Vdc/2 Vdc/2 Vdc/2 Vdc/2 Vdc Vdc Vdc Vdc Vdc Vdc Vdc Vdc Vdc vab(t) 0 Vdc/2 Vdc -Vdc/2 0 Vdc/2 -Vdc -Vdc/2 0 0 Vdc/2 Vdc -Vdc/2 0 Vdc/2 -Vdc -Vdc/2 0 0 Vdc/2 Vdc -Vdc/2 0 Vdc/2 -Vdc -Vdc/2 0 vbc(t) 0 0 0 Vdc/2 Vdc/2 Vdc/2 Vdc Vdc Vdc -Vdc/2 -Vdc/2 -Vdc/2 0 0 0 Vdc/2 Vdc/2 Vdc/2 -Vdc -Vdc -Vdc -Vdc/2 -Vdc/2 -Vdc/2 0 0 0 vca(t) 0 -Vdc/2 -Vdc 0 -Vdc/2 -Vdc 0 -Vdc/2 -Vdc Vdc/2 0 -Vdc/2 Vdc/2 0 -Vdc/2 Vdc/2 0 -Vdc/2 Vdc Vdc/2 0 Vdc Vdc/2 0 Vdc Vdc/2 0

Switching states 000000 010000 110000 000100 010100 110100 001100 011100 111100 000001 010001 110001 000101 010101 110101 001101 011101 111101 000011 010011 110011 000111 010111 110111 001111 011111 111111

28

## Leg c voltage (vcn(t))

Vdc

Vdc/2

0.01
Line voltage (vab(t))

0.02 0

0.01
Line voltage (vbc(t))

0.02 0

0.01
Line voltage (vac(t))

0.02

## Vdc Vdc/2 0 -Vdc/2 -Vdc 0 0.01 0.02 0 0.01

Time(S)

0.020

0.01

0.02

Fig.1-15: Leg and line voltage waveforms of the three-phase three-level diodeclamped converter

## 1.1.2.3 Capacitor Voltage Control in Diode-clamped Converters

In diode-clamped converters, series connection of the capacitors at the DC link voltage is necessary to synthesize staircase output voltage by dividing the total input voltage into two or more different DC voltage levels. This structure is suitable for many applications such as power systems and renewable energy systems. Assuming that the DC link capacitors were large enough in the previous cases, the DC link voltages were regulated at the exact amount of VC1
VC2 Vdc / 2 by neglecting the

ripple. However, using a large capacitor at the DC side is not practical as it is too bulky and expensive. Therefore, different current loops due to different switching states may cause the capacitor voltages to be unbalanced. To clarify this issue, a capacitor current equation for (n-1) capacitors in series, is given in (1-8). (j=1, 2,, n-1) (1-8) dt where iC j (t ) is the current through the jth DC link capacitor (Cj) in an n-level

iC j (t )

Cj

dvC j (t )

converter, and vC j (t ) is the voltage across Cj. If assumed that the current through

29

the DC link is constant over one switching cycle, then the capacitor voltage changes linearly. Fig.1-16 demonstrates the DC link capacitor voltage regarding both positive and negative capacitor currents. (1-8) can be rewritten for the switching period as follows:

IC j
where and

Cj

(1-9) t t t is the time interval of the capacitor current change (as shown in Fig.1-16)

vC j (t Tsw) vC j (t )

Cj

VC j

VC j is the capacitor voltage change during this interval. Thus, the variation of

## the capacitor voltage in each switching period can be defined as follows:

VC j t IC j Cj

(1-10)

According to (1-10), the direction of the current through the capacitors can increase or decrease the voltage across the capacitors in each switching period, as shown in Fig.1-16. Therefore, controlling the current can control the capacitor voltages in the diode-clamped converter.

VC j

IC j

ICj

Tsw

Tsw

## Fig.1-16: Capacitor voltage variation based on current direction

In diode-clamped converters, DC link capacitors are connected to load at different switching periods. Thus, these switching states may provide different current paths to charge or discharge the capacitors. The output voltage of two different cases has been shown in Fig.1-17. In Fig.1-17 (a), the DC link voltage of a three-level diodeclamped converter is constructed by a series connection of DC capacitors, while in Fig.1-17 (b), the DC link consists of a series connection of constant DC sources. By comparing these two cases, it is clear that the voltage of the middle point in the DC

30

link capacitors with respect to the bottom of the DC link voltage ( VC 2 ) can not be regulated at Vdc/2, as shown in Fig.1-17 (a). As shown in this figure, based on the current direction through the capacitors, this voltage can be more or less than Vdc/2. This unbalancing can cause some problems in the diode-clamped configuration. Since one of the capacitor voltages is more than Vdc/2 during the unbalancing period, the voltage stress across some switches is increased. This can damage the switches. In addition, unbalanced capacitor voltage can cause harmonic distortion to the current and affect voltage waveforms which results in a reduction in the quality of the output waveforms. Therefore, the DC link capacitor voltage balancing is necessary to create the desired voltage levels at the output voltage.

Vdc

## Leg voltage with regulated DC sources

Vdc/2

0.005

0.01

0.015

0.02 0

0.005

0.01

0.015

0.02

Time(S)

Time(S)

(a) (b) Fig.1-17: Leg voltage waveforms of a three-level diode-clamped converter (a) DC link with two series capacitors and (b) DC link with two series DC sources

To generate output voltage in multilevel converters, the duty cycle of switches can be defined based on different PWM strategies. Due to this fact, a proper switching transition is chosen by a controller to generate the desired output voltage. However, the DC link capacitor voltage unbalance problem happens due to different current loops through selected switches and capacitors. Therefore, based on the sign of load current, a DC link capacitor can be presented in a charging or discharging situation in different switching transitions. Table 1-4 shows these situations in a single-phase three-level diode-clamped converter for the positive load current.

31

Table 1-4

DC link capacitors charging states with respect to different switching states in a single-phase three-level diode-clamped converter Switching states vab(t) 0000 0001 0011 0100 0101 0111 1100 1101 1111 0 -Vdc/2 -Vdc Vdc/2 0 -Vdc/2 Vdc Vdc/2 0 C1 No change Discharge No change Charge No change No change Discharge Discharge No change iLoad(t)>0 C2 No change Charge No change Discharge No change No change Discharge Charge No change

As given in Table 1-4, the capacitor voltages can be controlled in some voltage levels (Vdc/2 and -Vdc/2) as there are options for charging or discharging the DC link capacitors; however, at the voltage levels Vdc, -Vdc and 0, the capacitor voltages can not be changed. As mentioned before, redundant switching states (0001 and 0111) in voltage level Vdc/2 and (0100 and 1101) in voltage level Vdc/2 can help to balance the capacitors voltage due to their different effect on DC link capacitors. This issue is shown in Fig.1-18 for a three-level converter in which the total DC voltage is supplied by a constant DC source, and output voltage is Vdc/2. By assuming a positive load current through C2 and a negative current through C1 [as shown in Fig.1-18 (a)], the load current is drawn from C2 which leads to discharging the bottom capacitor. As the total DC link voltage is constant ( VC1 + VC 2 =Vdc), a current can be injected to the top capacitor from the DC source. As a consequence in this situation, the C2 is discharged by the load current and C1 is charged with the DC source current. The switching state 1101 in Fig.1-18 (b) can discharge C1 and charge C2, similar to the switching state0100. It is mentioned that in the cases when the total DC source is supplied by a diode rectifier, charging and discharging situations should be taken into account based on the fact that the rectified output

32

voltage and the DC link capacitor voltage may fluctuate. In general, the switching states 0011 and 1100 can charge or discharge both capacitors if they are not connected to a DC source.

Sa1 C1
iC1 (t )

Da1

Sb1

Db1

Dca1

Sa2

Da2 a

Dcb1

Sb2

Db2 b

Vin

+ iC2 (t )

Dca2

Sa3

Dcb2 Da3

Sb3

Db3

## C2 Sa4 Da4 Sb4 Db4

R-L

(a)
Sa1 C1 Dca1 Vin + iC1 (t )

Da1

Sb1

Db1

Sa2

Da2 a

Dcb1

Sb2

Db2 b

iC2 (t )

Dca2

Sa3

Da3

Dcb2

Sb3

Db3

## C2 Sa4 Da4 Sb4 Db4

R-L

(b) Fig.1-18: Current loop in a single-phase three-level converter with positive load current (a) switching state 0100 and (b) switching state 1101

33

With choosing the switching states to balance the capacitors in modulation between two voltage levels, the adjacent switching states should also be taken into account to minimize the switching losses. As seen in Fig.1-19, for modulation between (0 and Vdc/2), it is possible to either charge or discharge C1 and C2 based on their voltage error in voltage level Vdc/2 if the controller chooses 0101 as a switching state to generate voltage level 0. For modulation between (Vdc/2 and Vdc), once the controller selects 1100 to synthesis level Vdc, the next adjacent switching states to produce voltage level Vdc/2 can be chosen among the switching states available in this level. In a positive load current for instance, if the voltage of the top capacitor ( VC1 ) is less than the bottom one ( VC 2 ), the switching state 0100 should be chosen to charge C1 and discharge C2. In contrast, the switching state 1101 should be chosen when the top and bottom capacitors should be discharged and charged, respectively. The same scenario is valid for the negative load current. Therefore, the capacitor voltage balancing using adjacent switching state is possible in different modulation levels in a single-phase three-level diode-clamped converter.

## Adjacent switching states Charge Discharge No change C1 C2 0100

1100

C1 C2 Vdc

C1 C2 1101 Vdc/2

C1 C2 0000 0101

C1 C2

C1 C2 1111

Fig.1-19: DC link capacitor charging states with respect to different voltage levels and adjacent switching states in a single-phase three-level converter with positive load current The capacitor voltage balancing algorithm for more than three levels has some restrictions and these are discussed specifically at the end of this section.

34

## 1.1.3 Flying Capacitor Converter Topology

The flying- capacitor converter was proposed by Meynard and Foch in 1992. The structure of this converter is similar to the diode-clamped converter except that the voltage clamping is achieved by means of capacitors that float with respect to the input DC link voltage. Output voltage can be synthesized by connecting the capacitors based on different switching states. A leg structure of a three-level flying capacitor converter is shown in Fig.1-20. If the ripple on the DC capacitors is neglected, this structure includes: one DC link capacitor (C) with potential of Vdc across it, a leg capacitor (Ca1) with VCa1 =Vdc/2 to synthesis step voltage at the output voltage, and two pairs of switches with anti-parallel diodes to conduct positive and negative load current. A leg voltage can be synthesized by connecting the leg capacitor (Ca1) in series with the DC link capacitor (C). More voltage levels can be achieved by connecting more pair of switches and leg capacitors, and this is discussed in the following section. Switches have the same structure as the diode-clamped converter. However, the complementary switches are constituted by (Sa1, Sa4) and (Sa2, Sa3), as shown in Fig.1-20 (a). Using this configuration, four different switching states can be utilized in each leg to obtain different voltage levels which have one more switching state than a diode-clamped converter. As seen in Fig.1-20 (b), when the voltage of Ca1 is assumed at Vdc/2 ( VCa1
Vdc / 2 ), three different voltage levels can be synthesized at

the leg voltage based on four different switching states. Operation of this configuration in different switching states is analyzed as follows: Switching state Sa1=0, Sa2=0 in (0<t t1) In this switching state both top switches Sa1 and Sa2 are off, so that their complements Sa4 and Sa3 are on. When the load current is positive, the reverse diodes Da3 and Da4 conduct and the current loop consist of Da3, Da4 and a load. However, in a negative load current, Sa3 and Sa4 conduct and the current loop consists of Sa3, Sa4 and the load. Therefore, as shown in Fig.1-21 (a), the output voltage in interval 0<t t1 is: van(t)= 0 (1-11)

In this switching state, the leg capacitor voltage ( VCa1 ) is not influenced by the load current as it is not included in the current loop.

35

p + Sa1 Da1

Da2

Vdc

Sa1=1 Sa2=0 or

a Sa3 Da3

## Sa1=0 Sa2=1 Vdc/2 Sa1=0 Sa2=0

Sa4 n

Da4

t1

t2

t3

(a) (b) Fig.1-20: One leg of a three-level flying capacitor converter (a) circuit diagram and (b) output leg voltage waveform
+ Sa1 Da1
+ Sa1 Da1

## Sa2 Vdc C Ca1

Da2
Vdc C Ca1

Sa2

Da2

a Sa3 Da3
Sa3 Da3

Sa4 -

Da4
-

Sa4

Da4 n

(a) (b) Fig.1-21: Current loops when Sa1=0 and Sa2=0 (a) positive load current and (b) negative load current

36

Switching state Sa1=0, Sa2=1 (t1<t t2) As shown in Fig.1-22 (a), for the positive load current, the switch Sa2 from the top and the anti-parallel diode Da4 from the bottom conduct due to the polarity of the voltage across the diode and the current direction through the switch. The current loop includes Ca1, Sa2, Da4, and the load. By assuming a positive load current, as shown in Fig.1-22 (a), this switching state can discharge the leg capacitor Ca1. On the other hand, for the negative load current, Da2 and Sa4 conduct according to the polarity of the voltage. This current loop can charge Ca1 based on the depicted direction. The current loop in a negative load current is shown in Fig.1-22 (b) and consists of Ca1, Da2, and Sa4. The output voltage for this switching state is: van(t)= VCa1
Vdc / 2

(1-12)

+ Sa1 Da1

+ Sa1 Da1

## Da2 Vdc a C Ca1

Sa2

Da2

a Sa3 Da3

Sa3

Da3

Sa4 -

Da4 n

Sa4

Da4 n

(a) (b) Fig.1-22: Current loops when Sa1=0, Sa2=1 (a) positive load current and (b) negative load current

Switching state Sa1=1, Sa2=0 (t1<t t2) In spite of a diode-clamped structure, this switching state is one of the switching states to achieve Vdc/2. Current loops for a positive and negative load current are shown in Fig.1-23. Following the current loops shown in Fig.1-23, Sa1 and Da3

37

conduct for the positive load current, and Da1 and Sa3 conduct for the negative load current. Here again, by considering VCa1 at half of the DC link capacitor voltage, the output voltage in the subinterval t1<t t2 is shown in Fig.1-20 (b) which is derived from (1-13). van(t)=Vdc- VCa1 =Vdc/2 (1-13)

In this switching state, as the current loop is constituted through the leg capacitor (Ca1) state, the capacitor can be charged by the positive load current as shown in Fig.1-23 (a), and discharged by the negative load current as shown in Fig.1-23 (b).

+ Sa1 Da1

+ Sa1 Da1

## Da2 Vdc a C Ca1

Sa2

Da2

a Sa3 Da3

Sa3

Da3

Sa4 -

Da4 n

Sa4

Da4 n

(a) (b) Fig.1-23: Current loops when Sa1=1, Sa2=0 (a) positive load current and (b) negative load current Switching state Sa1=1, Sa2=1 in (t2<t t3) In this switching state, both top switches Sa1 and Sa2 are on and their complements Sa3 and Sa4 are off. As shown is Fig.1-24 (a), for a positive load current , the switches Sa1 and Sa2 conduct so that the current loop consists of C, Sa1 and Sa2, and the load; meanwhile, for a negative load current, Da1 and Da2 conduct, and the

38

current flows through C, Da1, Da2, and the load [Fig.1-24 (b)]. Therefore, the output voltage in subinterval t2<t t3 is: van(t)= VC=Vdc (1-14) The load current flows through the DC link capacitors in this switching state so that this switching state cannot affect the leg capacitor voltage as there is no current loop through it. According to the different switching states given in Table 1-5, three possible voltage levels can be synthesized by four different switching states. It is assumed that the DC link voltage is connected to a constant voltage source Vdc, and leg capacitor (Ca1) voltage is controlled at Vdc/2 ( VCa1 =Vdc/2) by choosing proper switching states.

+ Sa1 Da1

+ Sa1 Da1

## Da2 Vdc a C Ca1

Sa2

Da2

a Sa3 Da3

Sa3

Da3

Sa4 -

Da4 n

Sa4

Da4

n (a) (b) Fig.1-24: Current loops when Sa1=1, Sa2=1 (a) positive load current and (b) negative load current

As presented in switching interval t1<t t2, both of the switching states 01 and 10 generate same voltage level at Vdc/2. Therefore, there is a redundant switching state in each leg voltage of the flying capacitor topology. The adjacent switching states are shown in Fig.1-25. The redundant switching states can guarantee the

39

capacitor voltage balancing with adjacency in each leg of the converter as they have different effects on the charge and discharge of the leg capacitor.

11

Vdc

01

10

Vdc/2

00

Fig.1-25: Adjacent switching states in one leg of a three-level flying capacitor converter

Table 1-5

Switching states in one leg of the three-level flying capacitor converter Sa1 0 0 1 1 Sa2 0 1 0 1 van(t) 0 Vdc/2 Vdc/2 Vdc

## 1.1.3.1 Single-phase Flying Capacitor Converter

A single-phase three-level flying capacitor converter can be built with two legs (Leg a and Leg b) which are connected to the same DC link voltage, as shown in Fig.1-26. Each leg consists of two pairs of switching components and one leg capacitor. Regarding the output voltage equation of the single-phase converter given in (1-6), five different voltage levels can be generated at the output voltage of the three-level flying capacitor converter by controlling the voltage of Ca1 and Cb1. In order to have a balance condition, the voltage of the leg capacitors should be regulated at Vdc/2. The output voltage of the three-level single-phase flying capacitor converter under the balanced condition is demonstrated in Fig.1-26 (b). Sixteen possible switching states with respect to the combination of the leg switching states can synthesize five different voltage levels in the single-phase three-level flying capacitor converter. All switching states associated with the five different voltage

40

levels are summarized in Table 1-6. The switching states are defined based on the switching states of each leg of the converter similar to the diode-clamped topology.
p + Sa1 Da1 Sb1 Db1

## Sa2 Vdc C Ca1

Da2 Cb1 a

Sb2

Db2

b Sb3 Db3

Sa3

Da3

Sa4 -n

Da4

Sb4

Db4

(a)
vab(t) Vdc Vdc/2 0 -Vdc/2 -Vdc

t1

t2

t3

t4

t5

t6

t7

t8

(b) Fig.1-26: A single-phase three-level flying capacitor converter (a) circuit diagram and (b) output waveform

As there are sixteen different switching states to obtain five voltage levels, it is apparent that there are more redundant switching states available in the single-phase

41

flying capacitor when compared to the diode-clamped converter. The graph of the switching states to achieve different voltage levels is shown in Fig.1-27.

Table 1-6

Switching states for the single-phase three-level flying capacitor converter Switching states 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 van(t) 0 0 0 0 Vdc/2 Vdc/2 Vdc/2 Vdc/2 Vdc/2 Vdc/2 Vdc/2 Vdc/2 Vdc Vdc Vdc Vdc vbn(t) 0 Vdc/2 Vdc/2 Vdc 0 Vdc/2 Vdc/2 Vdc 0 Vdc/2 Vdc/2 Vdc 0 Vdc/2 Vdc/2 Vdc vab(t) 0 -Vdc/2 -Vdc/2 -Vdc Vdc/2 0 0 -Vdc/2 Vdc/2 0 0 -Vdc/2 Vdc Vdc/2 Vdc/2 0

As shown in Fig.1-27, six redundant switching states are available at voltage level 0 and four redundant switching states are available for levels Vdc/2 and -Vdc/2. Adjacent switching states are available between all consecutive voltage levels; this means that modulation between two consecutive voltage levels can be obtained by only one switch transition. In addition, adjacency between switching states of voltage levels 0 and Vdc/2 gives more freedom of choice in controlling the leg capacitor voltages in the three-level flying capacitor converter. For instance, if the switching state 1010 is considered as a present state [Fig.1-28 (a)], there are two adjacent switching options such as 1000 and 1110 for modulation between levels 0 and Vdc/2. These two switching states at level Vdc/2 may provide different current loops through the leg capacitors in leg a and leg b. Fig.1-28 (b) and (c) present the current loops in these switching states for the positive load current. The same situation is available for all other switching states at voltage level 0, so that the leg capacitor voltage balancing can be implemented based on this freedom to choose different adjacent switching states in the flying capacitor topology.

42

1100

Vdc

0100

1000

1110

1101

Vdc/2

0000

1010

0110

0101

1001

1111

## (a) Positive half cycle

0000 1010 0110 0101 1001 1111 0

0001

0010

1011

0111

-Vdc/2

0011

-Vdc

(b)Negative half cycle Fig.1-27: Adjacent switching states in the single-phase three-level flying capacitor converter

Da2 Cb1 a

Sb2

Db2

b Sb3 Db3

Sa3

Da3

Sa4 -

Da4

Sb4

Db4

(a)

43

## Sa2 Vdc C Ca1

Da2 Cb1 a

Sb2

Db2

b Sb3 Db3

Sa3

Da3

Sa4 -

Da4

Sb4

Db4

(b)
+ Sa1 Da1 Sb1 Db1

## Sa2 Vdc C Ca1

Da2 Cb1 a

Sb2

Db2

b Sb3 Db3

Sa3

Da3

Sa4 -

Da4

Sb4

Db4

(c) Fig.1-28: Current loops in a single-phase three-level flying capacitor converter, with positive load current (a) switching state 1010 (b) switching state 1110 and (c) switching state 1000

44

If the voltage across the leg capacitor in the flying capacitor converter is controlled at half of the DC link voltage, the five-level output voltage and three-level leg voltage of a single phase flying capacitor converter is similar to that shown in Fig.110.

## 1.1.3.2 Three-phase Three-level Flying Capacitor Converter

Configuration of a three-phase three-level flying capacitor converter with a three-leg structure is shown in Fig.1-29. Based on a combination of the leg switching states, there are 4 3 different switching states in a three-phase three-level flying capacitor topology. These sixty four switching states can synthesis five different voltage levels in each line output voltage. Table 1-7 illustrates all possible switching states of the three-phase threelevel converter with all associated leg and line voltage levels when the leg capacitor voltages are controlled at Vdc/2. So, we have:
VCa1 = VCb1 = VCc1 =VC/2=Vdc/2
p + Sa1 Da1 Sb1 Db1 Sc1 Dc1

(1-15)

Da2 Cb1 a

Sb2

Db2 Cc1 b

Sc2

Dc2

c Sc3 Dc3

Sa3

Da3

Sb3

Db3

Sa4 -n

Da4

Sb4

Db4

Sc4

Dc4

## Fig.1-29: Three-phase three-level flying capacitor converter

Similar to the three-phase diode-clamped converter, the switching states are defined based on the switching states of each leg of the converter and are categorized based on the switching states which produce the same line voltage levels shown in

45

Sb2

## Db2 ib(t) b Cc1

Sc2

Dc2 ic(t) c

Sa3

Da3

Sb3

Db3

Sc3

Dc3

Sa4 -

Da4

Sb4

Db4

Sc4

Dc4

R-L

R-L

R-L

(a)
+ Sa1 Da1 Sb1 Db1 Sc1 Dc1

Sb2

## Db2 ib(t) b Cc1

Sc2

Dc2 ic(t) c

Sa3

Da3

Sb3

Db3

Sc3

Dc3

Sa4 -

Da4

Sb4

Db4

Sc4

Dc4

R-L

R-L

R-L

(b) Fig.1-30: Current loops in a three-phase three-level flying capacitor converter (a) switching state 000110 and (b) switching state 001001 Table 1-7. It is obvious that the three-phase flying capacitor structure generates a number of redundant switching states for each leg, and line voltages which can be

46

used in a control system to charge and discharge the capacitors. Fig.1-30 shows current loops through the switches and the capacitors for two redundant switching states of voltage levels (vab(t)=-Vdc/2, vbc(t)=0,vca(t)=Vdc/2). By considering positive currents for ib(t) and ic(t), current flows through different legs have different effects on the leg capacitor voltages in switching states 000110 and 001001. Line and leg output voltages of the three-phase flying capacitor are the same as those shown in Fig.1-15.

## 1.1.3.3 Capacitor Voltage Control in Flying Capacitor Converter

As discussed in the previous section, a staircase output voltage can be synthesized by connecting the DC link voltage and/or the leg capacitors in series. Therefore, to have a desired output voltage level, the capacitor voltages should remain at specific voltage level. In practice, the capacitor voltage balancing can be disturbed due to different load currents flow through capacitors so that the output voltage cannot have the desired value, as shown in Fig.1-17 (a). This unbalancing can pose some disadvantages such as extra harmonic contents, affecting voltage and current waveforms and causing high voltage stress on switching components. To prevent unbalanced leg capacitor voltage in a flying capacitor converter, proper switching states should be selected among the adjacent switching states to charge and discharge the capacitors properly. As demonstrated in Fig.1-25, each leg of the converter has switching redundancy in the middle voltage level (Vdc/2) which can be used for the capacitor voltage control. Leg capacitor charging states with both positive and negative load current loops with respect to different voltage levels and adjacent switching transitions are demonstrated in Fig.1-31. It is supposed that the input DC link is connected to a DC voltage source (Vdc) and the leg capacitors should be controlled at Vdc/2. It is apparent that, the capacitor voltage balancing is possible in each switching cycle for positive and negative load currents due to the redundant switching states at level Vdc/2. For example for a positive load current in leg a, If VCa1 is less than its reference at the beginning of a switching cycle, the capacitor is charged based on (110) by choosing 10 (Sa1=on and Sa2=off) at the next switching state. However, if
VCa1 is more than its reference (Vdc/2), the controller chooses the 01 (Sa1=off and

Sa2=on) for modulation between (Vdc/2 and Vdc) or (0 and Vdc/2) which can reduce

47

this voltage. The same scenario is valid for the other legs and also for a negative load current. This issue is shown in Fig.1-32 where the direction of the current flows through the loop is positive.

## techniques and duty cycles according to the reference voltage or current.

Table 1-7

Switching states in a three-phase three-level flying capacitor converter Switching states 000000 010101 010110 011001 011010 100101 100110 101001 101010 111111 000001 000010 010111 011011 100111 101011 010000 100000 111001 111010 110101 110110 101111 011111 000101 000110 001001 001010 000100 001000 101101 101110 011101 011110 111101 111110 van(t) 0 vbn(t) 0 vcn(t) 0 vab(t) vbc(t) vca(t)

Vdc/2

Vdc/2

Vdc/2

Vdc 0

Vdc 0

Vdc/2

Vdc/2

Vdc

Vdc/2

0 Vdc/2 0 -Vdc/2

Vdc

Vdc/2

Vdc/2

Vdc/2

Vdc

## Vdc -Vdc/2 0 Vdc/2

Vdc/2

Vdc/2

Vdc/2

0 -Vdc/2 Vdc/2 0

Vdc/2

Vdc

Vdc/2

Vdc

Vdc

Vdc/2

Vdc/2

-Vdc/2

48

010100 011000 101000 100100 110111 111011 010001 010010 100001 100010 000111 001011 001101 001110 011100 101100 010011 100011 110001 110010 110100 111000 000011 001100 001111 110000 110011 111100

Vdc/2

Vdc/2

Vdc

Vdc/2

Vdc/2

Vdc/2

## Vdc Vdc/2 0 Vdc Vdc/2 0 Vdc 0 Vdc 0 Vdc 0

-Vdc/2 -Vdc -Vdc/2 Vdc/2 Vdc Vdc/2 0 -Vdc -Vdc Vdc Vdc 0

-Vdc/2 Vdc/2 Vdc -Vdc -Vdc/2 Vdc/2 -Vdc Vdc 0 0 -Vdc Vdc

Vdc Vdc/2 -Vdc/2 Vdc/2 -Vdc/2 -Vdc Vdc 0 Vdc -Vdc 0 -Vdc

Charge No change Discharge 11 Ca1 Vdc Ca1 10 Vdc/2 Ca1 01 10 Ca1 Vdc/2 11 Ca1

Vdc

Ca1 01

## Ca1 00 Positive load current 0 00

Ca1 0

Fig.1-31: Leg capacitor (Ca1) charging states with respect to different voltage levels and adjacent switching states in one leg of the three-level converter for positive and negative load currents

49

+ Sa1 Da1

Da2

a Sa3 Da3

Sa4 + Sa1

Da4

Da1

## Sa2 Vdc C Ca1

Da2

a Sa3 Da3

Sa4 Da4 Fig.1-32: Current loops in leg a of the three-level flying capacitor when load current is positive (a) Sa1=1, Sa2=0 (b) Sa1=0, Sa2=1

50

The third topology for a multilevel converter is cascade converter, which can be synthesized by a series of two-level H-bridge converters (Marchesoni, 1990). Cascade configuration has been attractive for medium and high voltage renewable energy systems such as photovoltaic, due to its modular and simple structure. The configuration of a single-phase five-level cascade converter consists of two-level Hbridge cells in series which is shown in Fig.1-33.

a Cell 1
Sa1 Da1 Sa3 Da3

Vin

+ -

a1
Sa2 Da2

b1
Sa4 Da4

Cell 2
Sa5 Da5 Sa7 Da7 + -

Vin

a2
Sa6 Da6

b2
Sa8 Da8

## Fig.1-33: Two H-bridge inverters in series

Each two-level H-bridge converter includes one isolated DC source and two pairs of switches (Sa1, Sa2 and Sa3, Sa4) which work in complementary mode. By combination of four switching states, three different voltage levels at the output voltage of each H-bridge converter cell can be synthesized. Table 1-8 summaries possible switching states associated with different voltage levels of the Cell 1 in cascade converter structure where the input DC voltage with neglected ripple is Vin. Sa2 and Sa4 work complementarily with respect to Sa1 and Sa3, respectively. For example, for the case (Sa1=1 and Sa3=0), Sa1 is on, Sa2 is off, Sa3 is off and finally Sa4 is on. In Fig.1-34, the current loops are shown for the positive load current to achieve three voltage levels from the H-bridge cells. The same switching states exist for the other H-bridge cell.

51

Sa1 Da1 Sa3 Da3

## Sa1=off and Sa3=on

Sa1 Da1 Sa3 Da3

Vin

+ Sa2 Da2

Vin
a1 b1
Sa4 Da4

+ Sa2 Da2

a1

b1
Sa4 Da4

(a) va b (t ) =Vin 1 1
Sa1=on and Sa3=on
Sa1 Da1 Sa3 Da3

(b) va b (t ) =-Vin 1 1
Sa1=off and Sa3=off
Sa1 Da1 Sa3 Da3

Vin

+ -

a1
Sa2 Da2

b1
Sa4 Da4

Vin

+ Sa2 Da2

a1

b1
Sa4 Da4

(c) va b (t ) =0 1 1

Table 1-8

## Possible switching states in an H-bridge converter Sa1 0 0 1 1 Sa3 0 1 0 1

va1b1 (t )

0 -Vin Vin 0

According to the configuration of the cascade converter, the switching states in different H-bridge cells allow the adding and subtracting of the DC link voltages to synthesize a staircase output voltage. As shown in Fig.1-33, the output voltage can be derived as,
va1b2 (t ) = va1b1 (t ) + va 2 b2 (t )

(1-16)

If assumed that the input DC voltage of all cells is equal to the amount Vdc/2 (Vin=Vdc/2), each cell itself can produce three voltage levels: Vdc/2, 0, and -Vdc/2.

52

Therefore, five different voltage levels can be generated at the output voltage of the two-cell cascaded converter with different combinations, as shown in Table 1-9. As the bottom switches in each cell of the converter are complements of the top ones, the switching states in the single-phase cascade converter are defined based on the top switches of each H-bridge cell. As an example, switching state 1001 means that in the first H-bridge cell (Cell 1) the switching states are (Sa1=on, Sa2=off, Sa3=off, Sa4=on ) and in the second cell (Cell 2) the switching states are (S a5=off, Sa6=on, Sa7=on, Sa8=off). Each single-phase cascade converter with n cells in series, have (2n+1) voltage levels at the output. In contrast with diode-clamped and flying capacitor structures, cascade converters are named based on the number of voltage levels in each phase of the inverter, rather than on the number of leg voltage levels. In this structure, higher levels can easily be implemented by adding classical H-bridge cells into the chain of H-bridge cells. However, as this structure uses an isolated DC voltage source for each H-bridge cell, it needs additional DC voltage sources and switching devices and these increase the cost of the system.

Table 1-9

Switching states in a single-phase with two H-bridge converters Switching states 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
va1b1 (t ) va2b2 (t ) va1b2 (t )

## 0 -Vdc/2 Vdc/2 0 0 -Vdc/2 Vdc/2 0 0 -Vdc/2 Vdc/2 0 0 -Vdc/2 Vdc/2 0

0 -Vdc/2 Vdc/2 0 -Vdc/2 -Vdc 0 -Vdc/2 Vdc/2 0 Vdc Vdc/2 0 -Vdc/2 Vdc/2 0

As demonstrated in Table 1-9, 42 different switching states are available in the single-phase two-cell H-bridge cascade converter. However, only five different voltage levels can be synthesized at the output voltage. The output voltage of each

53

cell of the five-level cascade converter with output voltage in low frequency modulation is illustrated in Fig.1-35. An all adjacent switching states diagram for a five-level single-phase cascade converter with all redundant switching states in each level of the output voltage is depicted in Fig.1-36. Implicitly, there are four redundant switching states at levels Vdc/2 and - Vdc/2 and also there are six switching redundancies in level 0. Furthermore, there are adjacent switching states between all adjacent voltage levels of the output voltage so that the modulation between consecutive voltage levels can be applied without extra switching losses by choosing the adjacent switching states in each level of the modulation.

## H-bridge cell 1 H-bridge cell 2 Phase voltage

Vdc/2 0 -Vdc/2

Vdc/2 0 -Vdc/2

Vdc Vdc/2 0 -Vdc/2 -Vdc 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time(S)

Fig.1-35: Voltage waveforms of a single-phase cascade converter with two H-bridge cells

54

Two circuit diagrams based on the redundant switching states (1000 and 1110) of level Vdc/2 are illustrated in Fig.1-37 for a positive load current. As shown, different switching states may provide different current paths through the switching components and a load; however, these current loops are not investigated in order to balance the capacitor voltages, as isolated DC supplies are used for each H-bridge converter. Therefore, the capacitor voltage balancing is not needed in this configuration. However, in some applications such as Static Var Compensator, capacitors are used as storage elements instead of the isolated DC sources. Thus, the current loops should be investigated for capacitor voltage balancing in such applications. Isolated DC sources can be provided by battery or renewable energy sources such as photovoltaic and fuel cells through DC-DC converters. Also, transformers with multiple isolated secondary outputs can be utilized as input DC sources for H-bridge cells.

1010

Vdc

0010

1000

1110

1011

Vdc/2

0000

0011

0110

1100

1001

1111

## (a) Positive half cycle

0000 0011 0110 1100 1001 1111 0

0100

0001

0111

1101

-Vdc/2

-Vdc 0101

(b) Negative half cycle Fig.1-36: Adjacent switching states in a single-phase cascade converter

55

Sa1 Da1

Sa3 Da3

Sa1

Da1

Sa3 Da3

Vin

Vin

Sa5

Da5

Sa7 Da7

Sa5 Da5

Sa7 Da7

Vin

Vin

## + Sa6 Da6 Sa8 Da8

(a) (b) Fig.1-37: Current loops in a single-phase cascade converter when load current is positive (a) switching state 1000 and (b) switching state 1110

## 1.1.4.1 Three-Phase Five-level Cascade Converter

A three-phase cascade converter can be implemented by connecting three modules of single-phase cascade converters in a star or a delta connection. A configuration of a five-level three-phase cascade converter, which consists of two H-bridge cells in each phase, is shown in Fig.1-38.
a
Sa1 Da1 Sa3 Da3 Sb1 Db1 Sb3 Db3

b
Sc1 Dc1 Sc3 Dc3

Sa5 Da5

Sa7 Da7

Sb5 Db5

Sb7 Db7

Sc5 Dc5

Sc7 Dc7

Vin

Vin

Vin

## Fig.1-38: Three-phase five-level cascade converter

56

One of the important features of the cascade converter is the modularity of its structure which can ease the modulation in this type of multilevel structure. However, the number of isolated DC sources can increase the cost of the converter. As each leg of the three-phase cascade converter is a single-phase converter, each phase can be controlled individually to generate five voltage levels. As a result, a maximum of nine voltage levels can be obtained in line voltage (vab(t), vbc(t), vca(t)) by combination of leg voltage levels. However, all nine available voltage levels may not be synthesized at the line voltage due to the phase shift between the phase voltages. Apart from adding more H-bridge cells to increase the number of output voltage levels, there are other alternatives such as using different H-bridge converters or unequal isolated DC sources. These alternatives are discussed in the asymmetrical multilevel configuration section of this chapter.

## 1.1.5 High-level Multilevel Topologies

As discussed in the foregoing sections, three-level converters can generate stepped voltage outputs which can assist DC-AC converters in improving the output voltage quality and reducing switching component voltage rates. Advantages of the multilevel converters will be greatly enhanced by increasing the number of output voltage levels. Fig.1-39 represents a converter with (2n-1) voltage levels at the output waveform of an n-level multilevel converter which is generated by adding n step waveforms with different switching angles (1, 2... n). However, this will result in an increase in the number of active and passive components and eventually increase the cost of the system. Furthermore, increasing the number of power components can cause a limitation in some operational points regarding capacitor voltage balancing due to the different current loop through the capacitors. Therefore, converters with four- or more voltage levels need a complex controller to balance capacitor voltages and to generate PWM signals. Due to the different structures of the multilevel topologies, they need a different number of components to achieve high-level output voltage. As a result, there is a need for investigation of different nlevel topologies in order to find the limitations. The structure of diode-clamped, flying capacitor and cascade multilevel converters with more voltage levels are discussed later in this section.

57

Vin -Vin

1 2 N

## 1.1.5.1 Diode-Clamped Converter

A three-phase four-level diode-clamped converter is shown in Fig.1-40. All three phase structures share a common DC link voltage, which has been subdivided into three DC voltages using three series DC link capacitors. If the total DC voltage is Vdc and the voltage across each capacitor is shared equally at Vdc/3, the voltage stress across each switching device is limited to Vdc/3 through the clamping diodes. Switching states associated with different voltage levels are shown in Table 1-10. Each leg structure has three complementary switch pairs so that the turning on and off of the switches in one pair can not occur simultaneously. The complementary switch pairs for leg a are (Sa1, Sa4), (Sa2, Sa5), (Sa3, Sa6). From Table 1-10 it is also apparent that in the four-level diode-clamped converter, the switching states of each leg are always adjacent to obtain consecutive voltage levels.

T/2 T t

58

p
+ Sa1 Da1 C1 Dca1 Sa2 Da2 Dcb1 Sb2 Db2 Dcc1 Sc2 Dc2 Sb1 Db1 Sc1 Dc1

Dcb3

Dcc3

Sc3 Dc3 c

Sa4 Da4

Sb4 Db4

Sc4 Dc4

Dca4 C3 -

Sa5 Da5

Dcb4

Sc5 Dc5

Sa6 Da6

Sb6 Db6

Sc6 Dc6

## Fig.1-40: Three-phase four-level diode-clamped converter

Table 1-10

Possible switching states in one leg of the four-level diode-clamped converter Sa1 Sa2 Sa3 van(t) 1 1 1 Vdc 0 1 1 2Vdc/3 0 0 1 Vdc/3 0 0 0 0

The line voltage can be obtained by subtracting the leg voltages, so that seven voltage levels can be synthesized at the line voltage. In general, an n-level diodeclamped converter comprises an (n-1) DC link capacitor, 2 (n-1) switches and 2(n-1) anti-parallel diodes as well as (2n-4) clamped diodes which can generate n voltage levels at each leg and (2n-1) voltage levels at the line voltage. In the four-level converter with equal DC link capacitor voltage, the minimum voltage rating of each switch is Vdc/3; however, voltage rating of diodes can be different due to the changing of the clamped voltage in different switching states. As shown in Fig.1-39, in leg a, when all the top switches (Sa1 to Sa3) are turned on, the clamped diode Dca2 must block 2Vdc/3. Similarly, Dca1 must block Vdc/3. Therefore, if the converter

59

is designed to have the same voltage rating for all switches and clamped diodes, Dca2 should be implemented with two clamped diodes in series. In general, in order to have an identical switching components with the same break down voltage rating, (n-1)(n-2) clamped diodes are required in each leg of an n-level converter. It is obvious that the number of switches as well as clamped diodes is a function of the number of levels in a diode-clamped converter. This increases the cost and complexity of the layout.

Another problem associated with high level diode-clamped converters is capacitor voltage balancing. Also, it is possible to pre-charge the capacitors to the same voltage value and as the ripple is insignificant it can be approximated as:
VC1 = VC 2 = VC3 =Vdc/3

(1-17)

However, there is no guarantee of keeping their voltages identical during the operation due to the different current loops which may provide different DC current through the middle capacitors in the DC link voltage and these can charge or discharge the capacitors. These current loops for the positive half a cycle and positive load current are shown in Fig.1-42. In order to solve the capacitor voltage balancing in each level of modulation based on switching state selection, Table 1-11 shows all switching states in a single-phase four-level diode-clamped converter with the charging and discharging states of the capacitors.

In addition, adjacency between switching states for modulation between levels should be considered to minimize the switching losses. Therefore, Fig.1-43 shows the adjacent switching states between different voltage levels and capacitor charging with respect to the switching states. A challenging task is to find the best switching states in each modulation level in order to apply the capacitor voltage balancing and to keep the adjacency to minimize switching losses. To study the capacitor voltage balancing in a four-level single-phase diode-clamped converter, modulation in all voltage levels has been examined based on the capacitors charging and discharging situation, as shown in Fig.1-43.

60

C2 a Vdc

C(n-2)

## Dcan C(n-1) Sa(2n-2) Da(2n-2) n

Fig.1-41: A leg structure of an n-level diode-clamped converter Modulation between levels 0 to Vdc/3 In this level, there is no option to charge or discharge the capacitors in level 0 as no capacitor is located in the current loops. As a result, the capacitor voltage balancing must be considered in level Vdc/3 where at least one of the capacitors is in the load current loop. As shown in Fig.1-43, there is no problem with controlling the middle capacitor voltage ( VC 2 ) as the adjacent switching states are available to select the best switching state which can charge or discharge the capacitor based on its voltage error. However, a problem arises when the present switching state is 000000 (or 111111) and C1 (or C3) needs to be discharged according to the voltage control algorithm decision. As shown in Fig.1-43, there is no adjacent switching state to select the best option for the control algorithm; thus, in order to control the capacitor voltages, an extra number of switchings should take place and these impel extra losses to the system. To minimize the number of extra switchings in this condition, balancing algorithm should be designed to use the centre switching states 001001 and 011011 as switching states in level 0. In this case, switching

61

transient to balance the capacitor voltages which occur between nonadjacent switching states 011011 (or 001001) to 001000 (or 111011) can cause a fewer number of extra switchings. Modulation between levels Vdc/3 to 2Vdc/3 Since modulation between these voltage levels can change the capacitor voltages, a control algorithm can be applied in both voltage levels. According to Fig.1-47, there is an option to charge or discharge each DC link capacitor in level Vdc/3; however, there is no option to charge the middle capacitor (C 2) in level 2Vdc/3. This problem may not disturb the middle capacitor voltage significantly when the voltage error is not high (due to the capacitor size or load condition) and it can be modified in level Vdc/3 with a proper switching state. However, when error is high, this modulation is uncontrolled as there is no adjacent switching state to control the middle capacitor. Therefore, this control level is called a semi-control.

Table 1-11 DC link capacitor charging states with respect to different switching states in a single-phase four-level converter iLoad(t)>0 Switching states vab(t) C1 C2 C3 000000 0 No change No change No change 000001 -Vdc/3 Discharge Discharge Charge 000011 -2Vdc/3 Discharge Charge Charge 000111 -Vdc No change No change No change 001000 Vdc/3 Charge Charge Discharge 001001 0 No change No change No change 001011 -Vdc/3 Discharge Charge Discharge 001111 -2Vdc/3 Charge Charge Discharge 011000 2Vdc/3 Charge Discharge Discharge 011001 Vdc/3 Charge Discharge Charge 011011 0 No change No change No change 011111 -Vdc/3 Charge Discharge Discharge 111000 Vdc No change No change No change 111001 2Vdc/3 Discharge Discharge Charge 111011 Vdc/3 Discharge Charge Charge 111111 0 No change No change No change

Modulation between levels 2Vdc/3 to Vdc Since there is no option to balance the capacitors voltage in level Vdc and there is no chance to charge C2, the major problem arises for the middle capacitor. Therefore, at

62

this voltage level, the capacitor voltage cannot be controlled properly in a four-level diode-clamped converter as the middle capacitor voltage ( VC 2 ) is always charged or discharged due to the load current sign.

+ C1

a C2

C3 -

C1

C1

a C2

b C2

C3

C3

C1 C1

C1

a C2

b C2

b C2

C3 -

C3

C3

C1 C1

C1

C1

a C2

b C2

b C2

b C2

C3

C3

C3

C3

63

## Adjacent switching states Charge Discharge No change C1 C2 C3 011000

C1 C2 C3 111000 Vdc

C1 C2 C3 111001 2Vdc/3

C1 C2 C3 001000 C1 C2 C3 011000

C1 C2 C3 111011

Vdc/3

000000 C1 C2 C3

001001 C1 C2 C3

011011 C1 C2 C3

111111 C1 C2 C3

Fig.1-43: Adjacent switching sates and DC link capacitor conditions for the positive load current in a four-level diode-clamped converter

The main advantages and disadvantages of multilevel diode-clamped converters are described as follows: Advantages: All of the leg structures share a common DC link, which minimizes the capacitance requirements of the converter. For this reason, a back-to-back topology is a practical solution for adjustable speed drives or wind turbine systems. Few capacitors are required. Disadvantages: Capacitor voltage balancing tends to overcharge or discharge the capacitors without precise monitoring and control. The number of clamping diodes required is specifically related to the number of levels; a high number of levels can increase the complexity of this converter.

## 1.1.5.2 Flying Capacitor Converter

A circuit topology of a three-phase four-level flying capacitor multilevel converter is shown in Fig.1-44. This topology has a ladder structure of DC leg capacitors, where the voltage difference between two adjacent leg capacitors gives the step change at the output voltage. Therefore, for the four-level converter with the input DC voltage

64

of Vdc and the output stepped voltage of Vdc/3, the voltage on the capacitors should be kept at VCa1 =Vdc/3 and VCa 2 =2Vdc/3, as shown in Fig.1-44.
p
Sa1 Da1 Sb1 Db1 Sc1 Dc1

Sa2 Da2

Sb2 Db2

Sc2 Dc2

Sc3 Dc3 c

Sb4 Db4

Sc4 Dc4

Sa5 Da5

Sb5 Db5

Sc5 Dc5

Sa6 Da6

Sb6 Db6

Sc6 Dc6

## Fig.1-44: Three-phase four-level flying capacitor converter

Each leg structure has three complementary switch pairs. For example, pairs of switches in leg a are (Sa1, Sa6), (Sa2, Sa5), (Sa3, Sa4). All the combinations of the leg voltage levels for the four-level circuit in Fig.1-44 are summarized in Table 1-12. Similar to the three-level structure, it is apparent that there are leg switching redundancies which allow capacitor voltage control to provide different current loops while the output voltage is the same. By subtracting the leg voltages, seven voltage levels can be synthesized at the line voltage. Due to the switching states in the leg voltage, more redundancies can be obtained for inner voltage levels, so that two or more switching states are available to synthesize each voltage level. As mentioned in the three-level flying capacitor converter, different switching states through the leg capacitors based on the load current direction, may charge or discharge the leg capacitor voltage. Disturbance in the capacitor voltage can reduce the output voltage quality and harm switching components. Thus, the leg and line

65

redundant switching states will allow changing the current direction in different switching states to balance the capacitor voltages.

Table 1-12 Possible switching states in one leg of the four-level flying capacitor converter Sa1 Sa2 Sa3 van(t) 0 0 0 0 0 0 1 Vdc/3 0 1 0 Vdc/3 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 2Vdc/3 Vdc/3 2Vdc/3 2Vdc/3 Vdc

In general, an n-level flying-capacitor multilevel converter (as shown in Fig.1-45) consists of 2(n-1) switches and (n-2) leg capacitors (excluding the DC link capacitor, C) in each leg structure. However, to have an identical voltage rating to that of the main switches for the leg capacitors, a greater number of capacitors are required per leg structure. The main advantages and disadvantages of multilevel flying capacitor converters are as follows: Advantages: Redundancies in the leg switching states are available for balancing the voltage levels of the capacitors. Real and reactive power flow can be controlled. Disadvantages: Controlling the capacitor voltage levels is complicated. Also, recharging all of the capacitors to the same voltage level at start-up is complex. The large numbers of capacitors are both more expensive and bulky. Packaging is also more difficult in converters with a high number of levels. The capacitors are not always reliable components.

66

p Sa1 Da1

Vdc

a Ca(n-2) Ca1

Sa(2n-2) Da(2n-2) n

## Fig.1-45: Leg structure of n-level flying capacitor converter

The three-phase cascade converter consists of three individual phase structures to supply the three-phase load. As each H-bridge cell includes a two-level H-bridge converter with a separated DC source, series connection of H-bridge cells can synthesize different output voltage levels in each phase structure. Therefore, by increasing the number of series H-bridge cells, the number of output voltage levels can be increased. A three-phase structure of a cascaded converter with three Hbridge converter in series is illustrated in Fig.1-46. As discussed for the two-cell converter, each H-bridge cell can generate three different voltage levels, Vin, 0, and Vin. The outputs of each cell are connected in series such that the synthesized voltage waveform is the sum of the converter outputs. Therefore, seven levels can be achieved in the output phase voltage in the cascade converter with three H-bridge cells in each phase. In the three-level cascade converter, by combination of phase

67

voltage levels a maximum thirteen voltage levels can be obtained using the line equation; however, all these voltage levels cannot be generated at the line voltages (vab(t), vbc(t), vca(t)) due to 120 phase shift between phase voltages.

a Sa1 Da1 Vin + Sa2 Da2 Sa4 Da4 Sa3 Da3 Vin + Sb2 Db2 Sb4 Db4 Sb1 Db1

c Sc3 Dc3

Sc4 Dc4

Sb5 Db5

Sc5 Dc5

Sc7 Dc7

Sb6 Db6

Sb8 Db8

Sc6 Dc6

Sc8 Dc8

Sb9 Db9

Sc9 Dc9

Sc11 Dc11

Sb10 Db10

Sb12 Db12

Sc10 Dc10

Sc12 Dc12

## Fig.1-46: Three-phase seven-level cascade converter

Cascade converters are good candidates for medium and high power applications due to their modularity in structure. Therefore, it can easily be extended for an nlevel converter by adding more cells in each phase. However, the number of components, such as switches and separated DC source, is increased. As shown in Fig.1-47, in order to synthesis (2n+1) levels in each phase voltage, n equal separated DC sources and (4n) switches are necessary for each phase structure. Increasing the number of output voltage levels is not practical as it can impose extra cost to the system. To increase the number of voltage levels without increasing the number of components, several asymmetrical cascade configurations have been proposed in the recent literature. As an example, using multiple voltage levels in DC sources instead of identical DC sources in each H-bridge cell will result in an increase in the number of outputs with the same number of components. These types of converters are so-

68

called hybrid converters. This approach enables a wider diversity of output voltage magnitudes; however, it also results in unequal voltage ratings for each of the cells and loss of the modularity of structure. These types of converters are discussed in detail in the next section.
a b c

Sa1 Da1

Sb1 D b1

Sa1 Dc1

Vin + -

Vin + -

Vin + -

Cell 1

Vin

+ -

Vin

+ -

Vin

+ -

Cell 2

Vin

+ -

Vin
Sa(4n) Da(4n)

+ -

Vin
Sb(4n) Db(4n)

+ -

Sc(4n) Dc(4n)

Cell n

## Fig.1-47: Three-phase structure of n-level cascade converter

According to the DC link voltage of the cascade converter, it is apparent that there is no need for capacitor voltage balancing as each H-bridge is supplied by a separate DC source. However, in some applications, DC capacitors may be used for other cells for reactive power control. Therefore, more effort is required to find the best switching states in each phase of the cascaded converter to balance the capacitor for its desired value for each H-bridge cell. The main advantages and disadvantages of multilevel cascaded H-bridge converters are as follows: Advantages: The series of H-bridge cells creates a modularized layout and packaging for this type of converter; this leads to simple and cheap manufacturing. Disadvantages:

69

Separate DC sources are required for each H-bridge cell. This can limit its application when the number of output voltage levels is increased in high level converters.

1.1.6 Conclusions
Multilevel converters are promising converters for high and medium power applications due to their structures. The common advantages of all multilevel converter topologies are reduction in voltage stress across switching components, and improvement of harmonic contents of the output waveforms. These advantages result in a lower rate of voltage blocking for switches and higher voltage quality, respectively. However, different topologies may confront problems associated with capacitor voltage balancing, particularly in voltage level structure in diode-clamped converters. The large number of components, which results in complexity of the structure and extra cost, is another weakness of these types of converters.

In this chapter, the symmetrical configuration of different topologies has been overviewed in detail in order to illustrate their ability and performance in different switching states. Analyses have been extended to high level multilevel converters in order to highlight the boundaries in different topologies at the design stage. Various capacitor voltage balancing strategies have been proposed based on both PWM strategies and adjacency. Alternatively, utilizing effective front end converters in accordance to different applications may help to reduce the limitations caused by capacitor voltage unbalance in some topologies. On the other hand, utilizing asymmetrical multilevel converters can reduce the number of components with better quality, but this affects the complexity of the control system. This issue is analyzed in the following section.

70

## 1.2 Asymmetrical Multilevel Converters

1.2.1 Introduction
The previous section presented an extensive comparison between the symmetrical multilevel topologies in terms of their circuit structure, application and technical issues. Typically, different types of multilevel converters utilise a symmetrical structure with the same rating of DC link voltages and power devices due to the modularity and simplicity of the control strategy. The advantages of multilevel converters are increased when the number of output voltage levels is increased. However, the number of voltage steps is proportional to the number of power components. Therefore, enhancement of the multilevel converter topologies requires additional DC voltage sources or capacitors and switching devices, and this can impose extra cost and complexity on the system. Recently, asymmetrical multilevel converters with unequal DC source or DC capacitor voltages have been addressed for well-known multilevel structures to increase the multilevel converters performance, without adding any complexity to the power circuit.

The number of levels can be defined as the number of possible voltage levels at the output terminals of the converter; with respect to the reference point (which can be ground or neutral point). As described in the previous section, due to the number of switching components in multilevel converters, there are some redundant switching states to generate leg, phase, and line voltages in different structures. Thus, in some voltage levels, there is more than one switching state to synthesize a same voltage level at the output of the converter. These switching states can increase the choice of freedom in control strategy. This specific attribute of the multilevel converters can be utilized to maximize the number of output voltage levels in multilevel converters with the same layout of the multilevel power circuit. Therefore, it is possible to generate different voltage levels using redundant switching states when unequal, rather than equal, DC link configurations are utilized in the structure of multilevel converters.

Output voltage levels are defined based on DC link voltages in multilevel converters. Therefore, an asymmetrical multilevel converter created by an unequal

71

DC link arrangement may influence the regular switching states and features of the symmetrical multilevel converters (explained in the previous section). To have an effective design of asymmetrical multilevel converters, uniformity and modulation condition should be taken into account. A uniform configuration allows the use of a simple control strategy and an increase in the THD of the output waveform. To meet this criterion, finding a good factor between the DC link voltages is necessary in multilevel structures. Along with possible maximization of obtainable output voltage levels based on the voltage ratio of DC sources, the existence of adjacent switching states to move from one possible voltage level to another with only one switch change should be considered. Simultaneous switching of different switches is not an immense problem when there are just a few switchings occurring over a lot of transients; however, when switching between the nonadjacent switching states occurs frequently, it becomes a critical switching loss issue. Therefore, the DC voltage ratio of DC link, including DC sources or DC capacitors, should be presented to obtain maximum voltage levels on output voltage with adjacent switching states between all possible voltage levels, as well as to preserve the uniformity of the output voltage levels. This can minimize the switching losses and simplify the control complexity.

In this section, design rules and the possibility of DC link configurations for asymmetrical multilevel converters are discussed. The asymmetrical structures of the DC link voltage for single-phase multilevel converters are analyzed in two design conditions: the sequences of the voltage levels and the modulation strategies. Three main kinds of multilevel structures are investigated in this section, as shown in Fig.1-48. Thus, in the first two topologies [as depicted in Fig.1-48 (a) and Fig.148 (b)], DC link capacitors are regulated at different voltage levels dissimilar to the symmetrical condition. The third topology [depicted in Fig.1-48 (c)] uses unequal DC sources for each H-bridge cell. The cells can be fed either by separated DC sources, or by insulated rectifiers. Various design considerations for different topologies such as adjacent switching states for modulation technique, DC link capacitor voltage balancing, and switch voltage rating are investigated in this chapter.

72

a
+ -

+ -

+ -

(a) (b) (c) Fig.1-48: (a) One leg of the diode-clamped converter (b) one leg of the flying capacitor and (c) H-bridge cascaded converter

## 1.2.2 Unequal DC Link Configuration for Multilevel Converters

To study the concept of asymmetrical multilevel converters, this section starts with a discussion of low-level multilevel converters; this can then be extended to high-level converters. Fig.1-49 is the schematic diagram of a single-phase multilevel converter with two DC links which can form different topologies based on DC link configuration, as explained in the previous section. If the ripple on DC link is negligible, all the DC link voltages should be regulated to an identical value to have equal voltage levels at the output voltage ( VC1
VC2 ).

73

+
VC1

aN (

vbn(t) ib(t) +
VC2

-v

b vcn(t) c

+ vbN(t) ic(t)

t) +
N

- vc

(t) +

## Fig.1-49: Schematic diagram of a multilevel converter with two-DC link capacitors

According to Fig.1-49, assuming that the total DC link voltage is Vdc and the ripple on the DC link capacitors is negligible, each DC link should be controlled at Vdc/2 for the symmetrical case. In this condition, three different voltages (0, Vdc/2, and Vdc) can be generated in the leg voltage using different switching states. Since the output voltage in a single-phase converter is defined as (1-6), five different voltage levels can be generated at the output voltage based on different combinations of the leg voltages.

From the switching states derived for multilevel converters in the previous section, it is apparent that some combinations produce the same voltage levels at the output waveform. The switching states associated with these combinations are called redundant switching states. Therefore, in different configurations of multilevel converters, the redundant switching states occur for some voltage levels in which different switching states synthesis a same output voltage level. As discussed for different topologies, these switching states may be used in a control strategy to balance capacitor voltages based on different current loops.

The idea of the asymmetrical multilevel converters can be based on either using an unequal DC link arrangement or asymmetrical structure of converters to get benefits such as a greater number of output voltage levels, better voltage quality or a reduced number of components. Unequal DC link arrangements for multilevel converters, in which different asymmetrical multilevel topologies can be made with respect to the

74

DC link structure, are investigated in this section. This leads to the generation of new voltage levels through a reduction in the number of redundant switching states. To examine this concern, let us suppose that one of the DC link voltages is twice the strength of the other DC link capacitor in the structure shown in Fig.1-49. By assuming that the ripple on the DC link is negligible, the DC link capacitors can be regulated at either:
VC2 VC1 2VC1 2VC2

(1-18)
2VC1 ), if the total DC voltage is Vdc, VC 2 =2Vdc/3 and

## Thus, in the first case ( VC2

VC1 =Vdc/3. According to different switching states in each leg of the converter,

three different voltage levels with the amount of 0, Vdc/3, and Vdc are synthesized at the output leg voltage. As shown in Fig.1-50, different combinations of these three voltage levels produce seven different voltage levels at the output voltage of the asymmetrical arrangement [Fig.1-50 (b)]; this is two more than the case with identical DC link voltages [Fig.1-50 (a)].

In comparison with Fig.1-50 (a), the number of combinations and voltage vectors remain the same in Fig.1-50 (b); however, two redundant voltage vectors of Vdc/2 and -Vdc/2 can produce new voltage levels in the asymmetrical converter output. Output voltages of symmetrical and asymmetrical multilevel converters at switching frequency of 2 kHz are demonstrated in Fig.1-51. Therefore, a descent in harmonic content peak with a same switching frequency and an approximately same physical layout is expected by increasing the number of output voltage levels in the asymmetrical converter. Using this idea in four and more level converters, a different ratio of DC link voltages may be utilized to generate a different number of output voltage levels. However, there are some technical issues which should be taken into account for the proposed DC link ratios with respect to different configurations of multilevel converters.

75

van(t) Vdc

vab(t) Vdc

Vdc

## Vdc/2 Vdc/2 Vdc/2 0 -Vdc/2 0 0 -Vdc

(a)
van(t) vbn(t) vab(t) Vdc van(t)- vbn(t) Vdc Vdc 2Vdc/3 Vdc/3 2Vdc/3 2Vdc/3 0 -Vdc/3 0 0 -2Vdc/3 -Vdc

(b) Fig.1-50: Possible output voltage levels between two legs (a) in a symmetrical multilevel converter VC 2 VC1 and (b) in an asymmetrical multilevel converter
VC2
Vdc

2VC1
Vdc 2Vdc/3

Vdc/2

Voltage (V)

Vdc/3 0 -Vdc/3

## -Vdc/2 -Vdc 0 0.005 0.01 0.015

-2Vdc/3 -Vdc
0.02

0.005

0.01

0.015

0.02

Time(S)

Time(S)

(a) (b) Fig.1-51: Output voltage waveform of (a) symmetrical three-level converter VC 2 VC1 and (b) asymmetrical three-level converter VC 2 2VC1

76

A uniform voltage level is necessary to achieve good quality at output voltage and simple control laws in the multilevel converters. In other words, it is necessary to have identical voltage steps at the output waveforms. Therefore, uniformity of the output voltage should be taken into account when the possible maximization of output voltage levels is analyzed. To show the importance of the effect of the DC link voltage selection on the uniformity of the output voltage steps, two different DC link voltage ratios VC 2
2VC1 and VC 2 3VC1 are investigated in Fig.1-52 while

## It is obvious that asymmetrical DC link

arrangements produce two more voltage levels in the output of the converter compared with the symmetrical multilevel converter [Fig.1-50 (a)]. However, voltage steps in Fig.1-52 (b) are not the same in all switching transients as the voltage difference between voltage levels 0 and Vdc/4 is Vdc/4, while it is Vdc/2 between voltage levels Vdc/4 and 3Vdc/4. The output voltages of the discussed DC link arrangements are demonstrated in Fig.1-53. This configuration disturbs the uniformity of the output voltage which may increase or decrease the output current ripple and voltage stress in different load conditions. Although it might be possible to obtain uniform output voltage by using a different DC link for each converter leg individually, this is impractical in most of the applications, particularly in three-phase systems where the DC link is shared between all converter legs. Consequently, proper selection of the DC link ratio in multilevel converters is vital to achieve a simple control method and output voltage steps with minimum harmonic distortion.

77

van(t)

vbn(t)

Vdc

## van(t)- vbn(t) Vdc

2Vdc/3

2Vdc/3

0 -Vdc/3

-2Vdc/3 -Vdc

(a)
van(t) vbn(t) van(t)- vbn(t) Vdc Vdc vab(t) Vdc Vdc/4 3Vdc/4 Vdc/2 Vdc/4 3Vdc/4 3Vdc/4 0 -Vdc/4 0 0 -3Vdc/4 -Vdc Vdc/4

(b) Fig.1-52: Possible output voltage levels between two legs in the asymmetrical threelevel converter with DC link configurations (a) VC 2 2VC1 and (b) VC 2 3VC1
Vdc 2Vdc/3 Vdc 2Vdc/3 Vdc/3 0 -Vdc/3 -2Vdc/3 -Vdc 0 0.005

Voltage (V)

Vdc/3 0 -Vdc/3

-2Vdc/3 -Vdc

Time(S)

0.01

0.015

0.02

0.005

0.01

0.015

0.02

Time(S)

(a) (b) Fig.1-53: Output voltage waveform of the asymmetrical single-phase three-level converter when (a) VC 2 2VC1 and (b) VC 2 3VC1

78

## 1.2.3 Unequal DC Link Design Considerations

Along with uniformly increasing the output voltage levels in asymmetrical multilevel converters, some technical issues should be taken into account at the design stage. Adjacent switching states should necessarily be available between voltage levels to minimize the number of switching transitions which can reduce switching losses. Also, reducing the redundant switching states to increase the number of obtainable voltage levels may affect the capacitor voltage balancing freedom in some asymmetrical configurations which should be analysed based on current loops in different switching states. Finally, applying unequal DC link voltages causes different voltage stress on switching components; this can disturb equal distribution of switching losses and modularity in the structure. Therefore, all these technical issues should be taken into account in all multilevel configurations to have an effective asymmetrical configuration.

One of the essential issues in maximizing output voltage levels based on the voltage ratio of DC sources is the existence of adjacent switching states. Extra switching loss becomes a critical problem when the switching between the nonadjacent switching states occurs repeatedly in modulation between adjacent voltage levels. This can cause a critical switching loss issue in power electronic converters. As mentioned above, each voltage level is associated with one or more switching states in multilevel converters. In the symmetrical multilevel converters, successive voltage levels are synthesized using redundant switching states in each voltage level, as shown in the previous chapter. However, in the asymmetrical configuration due to the unequal DC voltage levels, some redundant switching states generate new voltage levels at the output of the converter; this may disturb adjacency of switching states to achieve adjacent voltage levels. To investigate the adjacency between switching states in order to have a minimum switching losses, adjacent graphs associated with different switching states of the converter should be examined. This issue is discussed for a single-phase three-level diode-clamped converter, flying capacitor converter and cascaded H-bridge converter in the next section.

79

## 1.2.3.2 Capacitor Voltage Balancing

Capacitor voltage balancing is the main issue in some multilevel configurations due to the existence of DC currents in the middle points of the DC link in which a capacitor is either charged or discharged for some intervals. Unbalanced voltage across the capacitors may lead to low quality output waveforms as well as switch malfunction. As discussed in the previous section, different current loops may be generated by different switching states through the DC link capacitors, the switching components, and a load which can charge or discharge the capacitors. Therefore, the capacitor voltage control in multilevel converters such as flying capacitor or diodeclamped converters are largely dependent on the redundant switching states in each voltage level according to the current flowing through the capacitors. Freedom of choice in the capacitor voltage control based on different current loops should be taken into account in asymmetrical configuration due to a reduction in the redundant switching states. These current loops may charge or discharge the DC link capacitor voltages depending on the direction of the load current.

## 1.2.3.3 Voltage Rating of Switching Components

The output voltage of the asymmetrical multilevel converters benefits from more voltage levels with the same number of components compared with symmetrical converters; however, extra voltage rates should be applied for some switching devices in each leg of the converter. Each voltage level in multilevel converters is synthesized by conducting some switches in a particular switching state. At the same time, the DC link voltage appears across the other switching components. Therefore, the voltage break down of the switching components is proportional to the DC link voltage in multilevel converters. As a result, an unequal DC link arrangement provides the switching components with different break down voltage matched with unequal DC link. This can affect the switching losses and modularity of the design.

## 1.2.4 Asymmetrical Diode-clamped Converters

In this section, different design points for a basic configuration of a single-phase diode-clamped converter (a three-level converter) are investigated to highlight the strengths and weaknesses of this topology for an asymmetrical configuration. A single-phase three-level diode-clamped structure is demonstrated in Fig.1-54.

80

p + Sa1
VC1

Da1

Sb1

Db1

+ Dca2
VC2

C2

Sa4 -n

Da4

Sb4

Db4

## Fig.1-54: A single-phase three-level diode-clamped converter

In order to have a comparative study of symmetrical and asymmetrical topologies for adjacent switching states, output voltages of a three-level single-phase diodeclamped converter with the equal ( VC 2 voltages are described in Table 1-13. Two adjacent and nonadjacent switching graphs for the equal and unequal DC link arrangements are depicted in Fig.1-55. As shown in Fig.1-55 (a), in the symmetrical converter, the adjacent switching states are available between all voltage levels, as previously discussed. In the asymmetrical configuration, the switching states 0100 and 0001 in the unequal arrangement produce new voltage levels 2Vdc/3 and 2Vdc/3, respectively. However, despite uniformly increasing the number of output voltage levels, there is no switching adjacency for modulation between (Vdc/3 and 2Vdc/3) in the positive and (-Vdc/3 and -2Vdc/3) in the negative half a cycle of the
VC1 ) and unequal ( VC 2 2VC1 ) DC link

81

output voltage, as shown in Fig.1-55 (b). These nonadjacent switching states induce a simultaneous switching between these two levels, in which two switching devices should switch at the same time, as presented in Fig.1-55 (b). This can impose unwanted switching losses to the system. Therefore, it seems that applying the unequal DC link arrangement to the three-level diode-clamped converter is not a promising method of meeting the requirement of a power electronic converter. In order to design an asymmetrical configuration for multilevel converters, the DC voltage ratio of the DC link voltages should be examined with respect to adjacent switching graphs to avoid modulation between the nonadjacent switching states. It should be mentioned that the adjacent switching graphs can be changed according to different configurations of the DC link arrangements in a higher level diodeclamped converter.

Table 1-13

Switching states in a single-phase three-level diode-clamped converter with equal and unequal DC link arrangements Symmetrical diode-clamped Asymmetrical diode-clamped converter ( VC 2 VC1 ) converter ( VC 2 2VC1 ) van(t) 0 0 0 Vdc/2 Vdc/2 Vdc/2 Vdc Vdc Vdc vbn(t) 0 Vdc/2 Vdc 0 Vdc/2 Vdc 0 Vdc/2 Vdc vab(t) 0 -Vdc/2 -Vdc Vdc/2 0 -Vdc/2 Vdc Vdc/2 0 Switching states 0000 0001 0011 0100 0101 0111 1100 1101 1111 van(t) 0 0 0 2Vdc/3 2Vdc/3 2Vdc/3 Vdc Vdc Vdc vbn(t) 0 2Vdc/3 Vdc 0 2Vdc/3 Vdc 0 2Vdc/3 Vdc vab(t) 0 -2Vdc/3 -Vdc 2Vdc/3 0 -Vdc/3 Vdc Vdc/3 0

Switching states 0000 0001 0011 0100 0101 0111 1100 1101 1111

82

## One switch change

1100 Vdc 1100 1100 1100 1100

## One switch change

0100 1101 0100 Vdc/2 1101 0100 1101 0100 1101

0000

0101

1111

0001

0111

-Vdc/2

0011

-Vdc

(a)
1100 Vdc

1100 1100

## Two switch change

0100 2Vdc/3 0100 0100 0100 0100 0100 0100

## One switch change

1101 Vdc/3 1101 1101 1101 1101 1101 1101 0000

0101

1111

## -Vdc/3 0111 0001 -2Vdc/3

0011

-Vdc

(b) Fig.1-55: Adjacent and nonadjacent switching states between different voltage levels in a single-phase three-level diode-clamped converter (a) symmetrical configuration ( VC 2 VC1 ) and (b) asymmetrical configuration ( VC 2 2VC1 )

To illustrate this issue and to study the performance of an effective unequal DC link configuration on redundant switching states, a single-phase four-level diodeclamped converter with two unequal DC link arrangements is examined in this section. A circuit diagram of a four-level single-phase diode-clamped converter with three series capacitors in the DC link is shown in Fig.1-56 (a). Capacitor voltages

83

## should be balanced so that, ignoring the DC link ripple, VC1

VC2

VC3 =Vdc/3 in

the symmetrical configuration. All possible switching states with relative output voltage levels in conventional arrangement are shown in Table 1-14.

Switching states are defined based on switching states of each leg of the converter. For instance, switching states 001011 means that the first three digits are switching states of the leg a where (Sa1=0, Sa2=0, Sa3=1), and the last three digits are the switching states of the leg b where (Sb1=0, Sb2=1, Sb3=1). It is clear that seven output voltage levels can be generated based on different switching states. However, there are some redundant switching states in each level of modulations. Adjacent switching states of the four-level converter are shown in Fig.1-56 (b). As the adjacency is available between all modulation levels, different output voltage levels in the single-phase conventional topology can be obtained with adjacent switching states and minimum switching transition.

Table 1-14

Output voltage in different switching states for a symmetrical fourlevel converter Switching states vab(t) 000000 0 000001 -Vdc/3 000011 -2Vdc/3 000111 -Vdc 001000 Vdc/3 001001 0 001011 -Vdc/3 001111 -2Vdc/3 011000 2Vdc/3 011001 Vdc/3 011011 0 011111 -Vdc/3 111000 Vdc 111001 2Vdc/3 111011 Vdc/3 111111 0

As shown in Fig.1-56 (b), more than one switching state is available to synthesize some voltage levels at output waveform. This specific characteristic of the multilevel converters can be utilized to maximize the number of output voltage levels with the same layout and complexity as the power circuit structure. Therefore, an unequal arrangement is examined for this converter in order to increase the

84

number of output voltage levels with the same number of components. As a case study, it is assumed that one of the capacitor voltages is maintained at twice the level of the other capacitors in DC link voltage configuration, so that the DC link voltage is not equally shared between the three capacitors. Two different DC link voltage configurations have been presented in this chapter in order to find the proper arrangement. In the first arrangement, the voltage of the centre capacitor ( VC 2 ) is twice the level of the external ones ( VC1 and VC3 ). Therefore, we have:
VC2 2VC1 2VC3

(1-19)

Assuming Vdc as the total input voltage and neglecting the ripple on DC voltages, the capacitor voltages in this unequal DC link arrangement should be constrained to:
VC1 =Vdc/4
VC 2 =Vdc/2 VC3 =Vdc/4

(1-20)

On the other hand, an unequal DC link can be arranged when the bottom capacitor voltage ( VC3 ) is maintained at twice the level of the other capacitor voltages ( VC1 and VC 2 ). So,
VC3 2VC1 2VC2

(1-21)

Therefore, considering Vdc as the total DC link voltage, the capacitor voltages should be regulated at:
VC1 =Vdc/4
VC 2 =Vdc/4 VC3 =Vdc/2

(1-22)

The output voltage levels associated with different switching states of the singlephase four-level diode-clamped converter with both of the unequal proposed DC link arrangements are demonstrated in Table 1-15. According to the output voltage, both configurations achieve two more voltage levels with an equal voltage step of Vdc/4 at each switching transient compared to the symmetrical single-phase fourlevel diode-clamped converters.

85

VC1
+

## C1 Dca1 Sa2 Da2 Dcb1 Sb2 Db2

Dca3

Sa3 Da3 a

Dcb3

Sb3 Db3 b

VC2

C2 Dca2 Sa4 Da4 + Dca4 C3 Sa6 Da6 Sb6 Db6 Sa5 Dcb4 Da5 Sb5 Db5 Dcb2 Sb4 Db4

VC3
n

R-L

(a)
111000 Vdc 2Vdc/3

111001 011001

## 111011 011011 111111

Vdc/3 0

001001

000001

001011 001111

011111

-Vdc/3

000011

-2Vdc/3 -Vdc

000111

(b) Fig.1-56: A single-phase four-level diode-clamped converter (a) circuit diagram and (b) adjacent switching states graph for the symmetrical case

Adjacent switching states in both unequal DC link configurations are shown in Fig.1-57 to examine the switching loss which is associated with the number of

86

switching transients per cycle. Possible switching states in adjacent and nonadjacent switching states in the graph of Fig.1-57 (a) show that moving from Vdc/2 to Vdc/4 and from -Vdc/2 to -Vdc/4 cannot be obtained by only one switch change when the middle capacitor voltage is twice the level of the other capacitor voltages, as there is no consecutive voltage vector between these voltage levels. This voltage change will result in significant switching losses that occur to achieve these voltage levels. In the other asymmetrical case shown in Fig.1-57 (b), while adjacent switching states are available between all voltage levels, individual nonadjacent switching transitions are required between the following switching states: (011000) and (111001) (000011) and (001111)

Table 1-15 Output voltage in different switching states for the asymmetrical single-phase four-level diode-clamped converter when the middle capacitor or bottom capacitor is doubled in the DC link arrangement Middle capacitor ( VC 2 ) is doubled Bottom capacitor ( VC3 )is doubled Switching states
000000 000001 000011 000111 001000 001001 001011 001111 011000 011001 011011 011111 111000 111001 111011 111111

vab(t) 0 -Vdc/4 -3Vdc/4 -Vdc Vdc/4 0 -Vdc/2 -3Vdc/4 3Vdc/4 Vdc/2 0 -Vdc/4 Vdc 3Vdc/4 Vdc/4 0

Switching states
000000 000001 000011 000111 001000 001001 001011 001111 011000 011001 011011 011111 111000 111001 111011 111111

vab(t) 0 -Vdc/2 -3Vdc/4 -Vdc Vdc/2 0 -Vdc/4 -Vdc/2 3Vdc/4 Vdc/4 0 -Vdc/4 Vdc Vdc/2 Vdc/4 0

These transitions between these switching states require two switch changes, as depicted by dashed lines in Fig.1-57 (b). Therefore, to avoid extra repetitive switching, a proper control strategy is required. In the positive voltage levels, when the controller increases the voltage level from Vdc/2 to 3Vdc/4, a transition occurs

87

from switching state (111001) to (011000). Then, the controller uses switching state (001000 and 01100) for modulation between Vdc/2 and 3Vdc/4. Also, after the occurrence of the transition from 3Vdc/4 (switching state 011000) to Vdc/2 (switching state 111001), the controller uses state 011001 for the modulation between Vdc/2 and Vdc/4. The same situation occurs when the output voltage is negative. Since these nonadjacent switching transitions occur only four times during one cycle, switching losses are negligible compared to the total losses.

According to the above analysis, it is apparent that using the unequal arrangement with VC3
2VC1 2VC2 for the asymmetrical single-phase four-level diode-clamped

converter is an effective configuration, as more output voltage levels can be obtained compared to the conventional equal DC link configuration with the same number of components and almost the same number of switchings per cycle. Extra switching losses to achieve these extra voltage levels are negligible compared to switching frequency, as it occurs four times in each fundamental cycle. Therefore, a decrease in switching redundancy cannot affect the uniformity and switching adjacency of the four-level multilevel converter significantly with an appropriate DC link voltage arrangement.

## 1.2.4.2 Capacitor Voltage Balancing

Asymmetrical diode-clamped configuration has the intrinsic capacitor voltage balancing problem of the diode-clamped converters. Therefore, switching states, as well as the direction of the current through capacitors, should be considered to balance the capacitors voltage. The capacitor voltage situation in each switching state associated with the positive voltage levels in the asymmetrical single-phase four-level diode-clamed converter ( VC3 demonstrated in Table 1-16.
2VC1 2VC2 ) with positive load current is

88

111000

111001

## Vdc/4 0 -Vdc/4 -Vdc/2

001111

-3Vdc/4 -Vdc

000111

(a)
Adjacency 111000 No adjacency 011000 111001 001000 011001 001001 001011 001111 000011 011011 111011 111111 011111 000000 Vdc

## 3Vdc/4 Vdc/2 Vdc/4 0 -Vdc/4 -Vdc/2 -3Vdc/4 -Vdc

000001

000111

(b) Fig.1-57: Adjacent and nonadjacent switching states in an asymmetrical diodeclamped converter when (a) VC2 2VC1 2VC3 (b) VC3 2VC1 2VC2

89

Table 1-16

Capacitor charging and switching state in the positive half a cycle and with positive load

Switching states 001001 011011 111111 011001 111011 111001 001000 011000 111000

Sa1 0 0 1 0 1 1 0 0 1

Sa2 0 1 1 1 1 1 0 1 1

Sa3 1 1 1 1 1 1 1 1 1

Sb1 0 0 1 0 0 0 0 0 0

Sb2 0 1 1 0 1 0 0 0 0

Sb3 1 1 1 1 1 1 0 0 0

## C1 No change No change No change Charge Discharge Discharge Charge Charge No change

As abovementioned, modulation between voltage levels should take place based on adjacent switching states. In order to consider both the adjacency and capacitor voltage balancing in the asymmetrical single-phase four-level diode-clamped converter, Fig.1-58 demonstrates both adjacent switching states and DC link capacitor charging states in a positive half a cycle, assuming that the load current is positive. As shown, there is only one option for modulation between Vdc (111000) and 3Vdc/4 (011000) which discharges the C3 and C2 and charges C1 for the positive load current. Also, C1 and C3 are uncontrolled when the output voltage level changes from 3Vdc/4 (011000) to Vdc/2 (001000) as it is the only adjacent switching state between these two voltage levels. Current loops in these switching states (011000) and (001000) are shown in Fig.159. By assuming the direction of the positive load current through C2 and C3, capacitor current through C1 in Fig.1-59 (a) is negative. As shown, load current is fed by the capacitors C2 and C3 which discharge them. As the total DC link voltage is constant ( VC3
VC1 VC2 =Vdc), a DC current can be injected to C1 from the DC

source. As a consequence in this situation, the bottom C2 and C3 are discharged by the load current and C1 is charged with DC source current. On the other hand, in switching state 001000 shown in Fig.1-59 (b), the load current is taken from C3 and the DC source current is injected to C1 and C2 in which C3 is discharged and C2

90

and C3 are charged. Thus, the modulation between these two voltage levels discharges C3 and charges C1.

No change Discharge

111000

C1 C2 C3 C1C2 C3

Vdc

## 011000 Charge C1 C2C3 111001 C1 C2 C 3 011001 111011 C1C2 C3 001000 C1C2 C3

3Vdc/4

Vdc/2

Vdc/4 0

001001 C1 C2 C3

011011 C1 C2 C3

111111 C1 C2 C3

000000 C1 C2 C3

Fig.1-58: Adjacent and nonadjacent switching states between different voltage levels in a four-level diode-clamped converter with unequal DC link capacitor ( VC3 2VC1 2VC2 )

As a consequence, the freedom of choice for capacitor voltage balancing using redundant switching states is less than in the conventional configuration due to the lack of switching states in each voltage level. Separated DC-DC converters or active front-end converters, such as multi-output DC-DC converters, are necessary to control the capacitor voltages specifically for high power factor loads.

91

VC1
+

Dca3 Vin + -

Sa3 Da3 a

Dcb3

Sb3 Db3 b

VC2

## C2 Dca2 Sa4 Da4 Dcb2 Sb4 Db4

+ Dca4 C3 Sa6 Da6 Sb6 Db6 Sa5 Dcb4 Da5 Sb5 Db5

VC3
-

R-L

(a)
+ Sa1 Da1 Sb1 Db1

VC1
+

Dca3 Vin + -

Sa3 Da3 a

Dcb3

Sb3 Db3 b

VC2

## C2 Dca2 Sa4 Da4 Dcb2 Sb4 Db4

Dca4 C3

Sa5

Dcb4 Da5

Sb5 Db5

VC3
-

Sa6 Da6

Sb6 Db6

R-L

(b) Fig.1-59: Current loop for a single-phase four-level converter in positive load current (a) Switching state 011000 and (b) Switching state 001000

92

## 1.2.4.3 Voltage Rating of Switching Components

As mentioned in the previous section, in contrast to the symmetrical multilevel converters, unequal DC link arrangement can impose unequal voltage rating for the switching components in asymmetrical multilevel converters. To clarify this issue, let us consider the circuit diagram of the four-level diode-clamped converter in different switching states, as shown in Fig.1-60. Considering Vdc as a total DC link voltage, the voltage across the switching components associated with different output voltage levels in the asymmetrical configuration ( VC3
2VC1 2VC2 ) is

described in Table 1-17. By switching between the different voltage levels, some components should clamp and tolerate the DC link voltage level once they do not conduct. Therefore, the minimum voltage rating of each component is proportional to the DC link voltage. The worst case which employs maximum voltage across a switch can be defined as the minimum voltage rate of switching components.

In Table 1-18, maximum voltage across switching components in the four-level converter in different switching states is shown to be comparable to the voltage rating of switching components in symmetrical ( VC3
VC1 VC2 )

and

asymmetrical ( VC3

2VC1

## 2VC2 ) converters. In the asymmetrical configuration,

the maximum voltage rating of switches Sa3 and Sa6 in each leg is Vdc/6 more than the switches in the symmetrical configuration for the same DC link voltage. As shown in Table 1-18, maximum voltage rating of diodes Dca1 and Dca3 are decreased by Vdc/12 and Vdc/6 with respect to the symmetrical converter; however, the maximum voltage tolerated by another two diodes Dca2 and DCa4 are increased by Vdc/12 and Vdc/6; this shows that the maximum voltage across diodes has not been changed in both configurations.

93

VC1
+

VC1
+ Dca3 Sa3 Da3 a

Dca3

Sa3 Da3 a

VC2

VC2

Da5

Da5

VC3
-

VC3
-

VC1
+

VC1
+ Dca3 Sa3 Da3 a

Dca3

Sa3 Da3 a

VC2

VC2

## C2 Dca2 Sa4 Da4 + Dca4 C3 Sa6 Da6 Sa5

Da5

Da5

VC3
-

VC3
-

Fig.1-60: Equivalent circuits for different switching states in the asymmetrical fourlevel diode-clamped converter

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Table 1-17
Leg voltage Vdc 3Vdc/4 Vdc/2 0

Voltage rates across switching components in the asymmetrical four-level diode-clamped converter
Sa1 0 Vdc/4 Vdc/4 Vdc/3 Sa2 0 0 Vdc/4 Vdc/3 Sa3 0 0 0 Vdc/3 Sa4 Vdc/3 0 0 0 Sa5 Vdc/3 Vdc/4 0 0 Sa6 Vdc/3 Vdc/2 Vdc/2 0 Dca1 Vdc/4 0 0 0 Dca2 0 0 Vdc/4 3Vdc/4 Dca3 Vdc/2 Vdc/4 0 0 Dca4 0 0 0 Vdc/2

Table 1-18 Maximum voltage rates across switching components in one leg of the symmetrical and asymmetrical four-level diode-clamped converter
Switches and diodes in one leg of diodeclamped converter Sa1 Sa2 Sa3 Sa4 Sa5 Sa6 Dca1 Dca2 Dca3 Dca4 Maximum voltage rates in symmetrical four-level diodeclamped converter Maximum voltage rates in asymmetrical four-level diodeclamped converter ( VC 2VC 2VC )
3 1 2

( VC3

VC1
Vdc/3 Vdc/3 Vdc/3 Vdc/3 Vdc/3 Vdc/3 Vdc/3 2Vdc/3 2Vdc/3 Vdc/3

VC2 )

Vdc/3 Vdc/3 Vdc/2 Vdc/3 Vdc/3 Vdc/2 Vdc/4 3Vdc/4 Vdc/2 Vdc/2

## 1.2.5 Asymmetrical Flying Capacitor Converter

In a symmetrical flying capacitor converter, different voltage levels can be obtained based on voltage regulated at leg capacitors in each leg of the converter. In this section, a single-phase three-level flying capacitor converter, as shown in Fig.1-61, is investigated with asymmetrical DC link arrangement.

95

Da2 Cb1 a

Sb2

Db2

b Sb3 Db3

Sa3

Da3

Sa4 n

Da4

Sb4

Db4

## Fig.1-61: A single-phase three-level flying capacitor converter

Since each leg of the flying capacitor converter has its own DC capacitor, each leg can be controlled individually. This gives a large degree of redundancy in the flying capacitor configuration to achieve different voltage levels, as discussed in the previous section. Therefore, it is more likely to obtain adjacent switching states in asymmetrical configurations for modulation between adjacent levels. Due to the structure of this converter, it is possible to set different voltage levels for each leg structure individually to create an asymmetrical configuration. However, this chapter considers a same set of DC voltage levels for the leg capacitors in all leg structures. To evaluate this matter for the flying capacitor, instead of VCa1
VCb1

## =Vdc/2 in the symmetrical configuration, it is assumed that:

VCa1 VCb1 =Vdc/3

(1-23)

The possible voltage levels can be synthesized by four different switching states given in Table 1-19. This design synthesizes one more voltage level in each leg of the converter compared to the symmetrical structure which leads to achieve two more voltage levels in the single-phase converter output. All possible switching

96

states with relative output voltage levels in a single-phase three-level flying capacitor with the asymmetrical DC link arrangement are shown in Table 1-20.

Table 1-19 Switching states for one leg of the three-level flying capacitor converter with symmetrical and asymmetrical configurations Symmetrical configuration Asymmetrical configuration Sa1 Sa2 van(t) Sa1 Sa2 van(t) 0 0 0 0 0 0 0 1 Vdc/2 0 1 Vdc/3 1 0 Vdc/2 1 0 2Vdc/3 1 1 Vdc 1 1 Vdc

Adjacent and some nonadjacent switching states of the asymmetrical DC voltage configuration are shown in Fig.1-62 to examine the switching loss which is associated with the number of switchings per cycle. As shown, adjacency is available between all switching states; however, nonadjacent switching states occur when the voltage level moves from Vdc/3 to 2Vdc/3 in the positive half a cycle, and from -Vdc/3 to -2Vdc/3 in the negative half cycle. This nonadjacent switching transient takes place only two times for modulation between these voltage levels. The controller can follow the adjacency for the rest of the modulations. Assuming that a present switching state is 1110 and output voltage has to be changed from Vdc/3 to 2Vdc/3, the switching state is changed from 1110 to 1101 which employs two switch changes. However, to avoid the nonadjacent switching states for the rest of modulation, the controller can use 1101 and 1001 to minimize the switching transient. This scenario is valid for the negative half cycle. Therefore, four extra switchings take place over one cycle to fulfill the modulation between all voltage levels. This extra switching loss is negligible in high switching frequency applications. As a consequence, more redundant switching states in the flying capacitor structure allow the use of an asymmetrical DC voltage configuration in the three-level flying capacitor to increase the voltage levels uniformly and to fulfill the adjacent switching states between different voltage levels. Alternative DC voltage arrangements for the leg capacitors in three and more voltage levels should be examined in order to achieve more uniform voltage levels by preserving the adjacent switching states between all voltage levels.

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Table 1-20

Switching states for a single-phase three-level flying capacitor converter Switching states van(t) vbn(t) vab(t) 0000 0 0 0 0001 0 Vdc/3 -Vdc/3 0010 0 2Vdc/3 -2Vdc/3 0011 0 Vdc -Vdc 0100 Vdc/3 0 Vdc/3 0101 Vdc/3 Vdc/3 0 0110 Vdc/3 2Vdc/3 -Vdc/3 0111 Vdc/3 Vdc -2Vdc/3 1000 2Vdc/3 0 2Vdc/3 1001 2Vdc/3 Vdc/3 Vdc/3 1010 2Vdc/3 2Vdc/3 0 1011 2Vdc/3 Vdc -Vdc/3 1100 Vdc 0 Vdc 1101 Vdc Vdc/3 2Vdc/3 1110 Vdc 2Vdc/3 Vdc/3 1111 Vdc Vdc 0

1100

Vdc

1101

2Vdc/3

0100

1001

1110

Vdc/3

0000

0101

1010

1111

0001

0110

1011

-Vdc/3

0010

0111

-2Vdc/3

-Vdc 0011

Fig.1-62: Adjacent and nonadjacent switching states for single-phase three-level flying capacitor with asymmetrical DC voltage arrangement ( VCa1 VCb1 = Vdc/3)

98

## 1.2.5.2 Capacitor Voltage Balancing

The flying capacitor topology benefits from the adjacent switching states which can give more freedom in capacitor voltage balancing in this type of multilevel converter. Thus, a greater degree of freedom for capacitor voltage balancing is expected in the asymmetrical flying capacitor compared to the diode-clamped configuration, due to the large number of redundant switching states in the singlephase structure. The adjacent and nonadjacent switching states graph for the

positive half a cycle of a single-phase converter, together with leg capacitor charging conditions with positive load current, is shown in Fig.1-63.

## No change Discharge Charge Ca1 Cb1 1000 Ca1 Cb1

Positive load current Ca1 Cb1 1100 Ca1 Cb1 1101 Ca1 Cb1 1001 11 10 Ca1Cb1 0101 1010 Ca1 Cb1 1111 0 Vdc/3 2Vdc/3 Vdc

## 0100 Ca1 Cb1 0000 Ca1 Cb1 Ca1 Cb1

Fig.1-63: Adjacent switching states between different voltage levels in an asymmetrical three-level flying capacitor converter ( VCa1 VCb1 =Vdc/3)

As presented, despite the symmetrical configurations for the flying capacitor converters discussed in the previous section, there is no option to control the leg capacitor voltages based on the adjacent switching states between voltage levels. As shown, to follow the adjacent switching states for modulation between voltage levels, at least one leg capacitor voltage will be uncontrolled. This can cause an unbalanced leg capacitor voltage in the asymmetrical three-level flying capacitor; this is impractical due to the output voltage distortion and switching component

99

damage. To address this issue, particular balancing circuits such as auxiliary devices might be used to control the capacitor voltages. As a result, the capacitor voltage balancing for different asymmetrical flying capacitor configurations should be examined along with adjacent switching states.

## 1.2.5.3 Voltage Rating of Switching Components

Voltage rating of the switching components in the flying capacitor can also be influenced by the DC link arrangement. Equivalent circuit diagrams of different switching states in an asymmetrical three-level flying capacitor when ( VCa1
VCb1

=Vdc/3) and total input DC voltage is Vdc are illustrated in Fig.1-64. According to different switching states shown in Fig.1-64, it is apparent that switches Sa1 and Sa4 should block 2Vdc/3 when the output voltage levels are Vdc/3 and 2Vdc/3, respectively. This voltage rating is twice the voltage rating of Sa2 and Sa3 (Vdc/3).

In order to compare the voltage rating of the switches in symmetrical ( VCa1 =Vdc/2) and asymmetrical ( VCa1

VCb1

## VCb1 =Vdc/3) three-level flying capacitor

converters with the input DC voltage of Vdc, maximum voltage stress on each switch is presented in Table 1-21. Apparently, in asymmetrical converters, maximum voltage ratings of two switches (Sa1 and Sa4) are Vdc/6 more than in the symmetrical configuration. On the other hand, voltage rating of switches S a2 and Sa3 are Vdc/6 less than the ones in the symmetrical configurations.

Thus, the issue of voltage rating limits of high frequency switching devices can limit the high DC link voltage ratio selection for multilevel converters. In addition, the unequal DC voltage rating of switches may influence the modularity of the modulation and increase the losses. This should be taken into account in asymmetrical configurations. Therefore, the DC link ratio for asymmetrical configurations should be chosen at the design stage.

100

## Switching state 01"

+ Sa1 + Sa2 Vdc C VCa1 Ca1 a Sa3 Da3 Da2 Vdc Da1

Da4 +

Sa4

Da4

## Switching state 11"

+ Sa1 + Sa2 Vdc C VCa1 Ca1 a Sa3 Da3 Da2 Vdc Da1

## Sa1 + Sa2 C VCa1 Ca1

Da1

Da2

a Sa3 Da3

Sa4 -

Da4 -

Sa4

Da4

Fig.1-64: Equivalent circuits for different switching states in the asymmetrical unequal DC link of the three-level flying capacitor converter

Table 1-21 Maximum voltage rate of the switching components in the symmetrical and asymmetrical three-level flying capacitor converters
Switches and diodes in one leg of flying capacitor converter Sa1 Sa2 Sa3 Sa4 Maximum voltage rates in symmetrical three-level flying capacitor converter Maximum voltage rates in asymmetrical three-level flying capacitor converter

( VCa1

VCb1 =Vdc/2)
Vdc/2 Vdc/2 Vdc/2 Vdc/2

( VCa1

VCb1 =Vdc/3)
2Vdc/3 Vdc/3 Vdc/3 2Vdc/3

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## 1.2.6 Asymmetrical Cascaded H-bridge Converters

Among multilevel topologies, cascade configuration has an attraction for medium and high voltage renewable energy systems such as photovoltaic due to its modular and simple structure, and it has been reviewed in the symmetrical multilevel converters. Series connection of two-level H-bridge converters is shown in Fig.1-65 for n cells per phase. Each cell is supplied by a separated DC source where the ith converter cell is supplied by a DC source (Vin(i)).

Vin1

+ -

Vin2

+ -

Vin(n)

+ -

## Fig.1-65: One phase of series connection of two-level H-bridge converters

In a symmetrical multilevel converter, all the DC sources are equivalent and are the same fraction of the total DC voltage (Vdc). Thus, neglecting the ripple of DC source voltages, we have:

Vin1 Vdc

Vin2 Vdc

...

Vin(i ) Vdc

...

Vin(n) Vdc

(1-24)

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Using unipolar modulation, three different voltage levels can be synthesized in each H-bridge converter cell, so that (1-25) shows the number of output voltage levels in the symmetrical cascade converters, as explained in the previous section.

2 n 1

(1-25)

Fig.1-66 shows N different voltage levels at the output voltage of the n-cell cascade converter. In order to achieve the uniform output voltage, all voltage steps should be equal. Assuming that the smallest DC voltage source of the cascade converter shown in Fig.1-65 is (Vin1), we have,
Vj Vj
1

Vin1

(j=0,, (N-1)/2)

(1-26)

V(N-1)/2 V(N-3)/2

1 2 N -V(N-3)/2 -V(N-1)/2

## Fig.1-66: Output voltage of the N-level cascade converter

It is apparent that the number of output voltage levels depends on the number of Hbridge converter cells in this structure. Consequently, increasing the number of output voltages is related to the number of power components which increase the cost and complexity of the converter layout structure and control system.

Asymmetrical cascade converters contribute to generating a greater number of output voltage levels without adding H-bridge converter cells. An asymmetrical cascade converter is implemented if one of the above symmetry conditions in (1-24) is not valid. Different unequal DC sources can be implemented in cascade multilevel configurations to synthesis more voltage levels at the output side. Two case studies for the DC source ratios are analyzed to illustrate this issue.

T/2 T

103

1.2.6.1 Asymmetrical Cascade Two-level H-bridge Converter with the Factor of Two
In this approach, the ratio between DC voltage sources supplying consecutive Hbridge converters is two, as shown in (1-27).

Vin 2 Vin1

Vin 3 Vin 2

...

Vin (i ) Vin (i
1)

...

Vin ( n) Vin ( n
1)

(1-27)

(1-28)

## Also, assuming the total DC voltage levels is as follows:

Vdc Vin1 Vin 2 ... Vin (n)

(1-29)

By substitution of (1-28) into (1-29), the total DC voltage of the cells can be derived as follows:

Vdc

Vin1 (2n 1)

(1-30)

On the other hand, as the output voltage is uniform, for N-level output voltage depicted in Fig.1-66:
Vdc Vin1 (N 2 1)

(1-31)

Consequently, the relationship between the number of output voltage levels (N) and the number of two-level H-bridge cells is defined by:

2(n 1) 1

(1-32)

Comparing (1-25) and (1-32), it is apparent that with the same number of converter cells, more voltage levels can be synthesized at the output voltage of the converter in asymmetrical cascade configuration with the factor of two, compared to the symmetrical cascade converter.

104

1.2.6.2 Asymmetrical Cascade Two-level H-bridge Converter with the Factor of Three
The same analysis can be carried out on an n-cell cascade converter when the ratio between DC voltage sources supplying consecutive H-bridge converters is three, as shown in (1-10).

Vin 2 Vin1

Vin 3 Vin 2

...

Vin (i ) Vin (i
1)

...

1)

(1-33)

## 3 Vin1 3 2 Vin1 3 i 1 Vin1 3 n 1 Vin1

(1-34)

By substitution of (1-34) in (1-29), the sum of the DC input voltages of the cells can be derived as follows:

Vdc

Vin1

(3n 1) 2

(1-35)

If the output voltage is uniform, for N-level output voltage shown in Fig.1-66:
Vdc Vin1 (N 2 1)

(1-36)

Consequently, the relationship between the number of output voltage levels (N) and the number of two-level H-bridge cells is defined by equating (1-35) and (1-36) as follows:

3n

(1-37)

It is obvious that more voltage levels can be synthesized at the output voltage with the same number of two-level H-bridge cells in the asymmetrical cascade configuration with the factor of three, compared to the symmetrical cascade

105

converter. A comparison between the number of output voltage levels based on the number of converter cells for symmetrical and asymmetrical configurations has been summarized in Table 1-22. As shown, the asymmetrical cascade converters generate more output voltage levels with the same number of components, compared to the symmetrical cascade converter. A difference between the numbers of output voltage levels is significant in a high number of cells; however, the need for extra separated DC sources is the drawback of having a high number of cells.

It should be noted that the asymmetrical configurations with factors of two and three are not the only asymmetrical arrangements to increase the number of voltage levels without increasing the number of H-bridge converter cells. Various asymmetrical arrangements with different ratios between DC sources can be utilized to maximize the number of output voltage levels; however, uniformity of the output voltage with the same voltage steps and the use of adjacent switching states should be considered at a design stage. Table 1-22 Number of voltage levels in terms of number of cells in symmetrical and asymmetrical configurations Number of levels (N) Symmetrical 5 7 9 11 Asymmetrical (factor two) 7 15 31 63 Asymmetrical (factor three) 9 27 81 243

Number of cells(n)

2 3 4 5

As discussed in the previous section, increasing the number of voltage levels is directly related to the redundant switching states. On the other hand, redundant switching states may provide adjacent switching states between adjacent voltage levels. Therefore, along with increasing the number of voltage levels to increase the quality of the output waveforms, existence of the adjacent switching states for modulation between the voltage levels should be taken into account.

106

To investigate these issues in the asymmetrical cascade converters, a simple two cell (n=2) structure of the cascade converter with the proposed asymmetrical arrangements is examined. Fig.1-67 shows the cascade converter with n=2, where the ratio between the DC sources of each cell is two or three. Fig.1-68 illustrates the possible output voltage levels of each H-bridge converter cell to synthesise the output voltage levels in the two-cell cascade converter with symmetrical and asymmetrical configurations. Due to a reduction in redundant switching states, there are two and four more voltage levels at the output voltage in the asymmetrical configuration, with the ratio of two (Vin2=2Vin1) and three (Vin2=3Vin1), respectively. Assuming that,

Vdc=Vin1+Vin2

(1-38)

in the asymmetrical arrangement with the factor of two (Vin2=2Vin1), then it can be concluded that Vin2=2Vdc/3 and Vin1=Vdc/3. The same is true in the configuration with the factor of three (Vin2=2Vin1), Vin2=3Vdc/4 and Vin1=Vdc/4. Using this assumption, the possible output voltage levels which can be generated at the output voltage of the asymmetrical two-cell cascaded converter are shown in Table 1-23. As the bottom switches in each cell of the converter are the complements of the top ones, the switching states in the single-phase cascade converter are defined based on the top switches of each H-bridge cell. As an example, switching state 1001 means that in the first H-bridge cell (Cell 1) switching states are (Sa1=on, Sa2=off, while Sa3=off, Sa4=on ), and in the second cell (Cell 2) the switching states of switches are (Sa5=off, Sa6=on, while Sa7=on, Sa8=off). According to the voltage levels associated with different switching states, the asymmetrical configuration with the factor of three generates a larger number of voltage levels as expected, based on the theoretical analysis. However, as for the other multilevel topologies, adjacent switching states should be studied based on an adjacent switching graph. Fig.1-69 demonstrates the adjacent switching graph of the asymmetrical configurations with the factors of two and three.

107

a1 Cell 1
Sa1 Da1 Sa3 Da3

Vin1

+ Sa2 Da2

b1
Sa4 Da4

Cell 2
Sa5 Da5 Sa7 Da7 + -

Vin2

a2
Sa6 Da6 Sa8 Da8

b2

## Fig.1-67: A single-phase two-cell cascade converter

According to the adjacent switching graphs, the adjacent switching states are available between all voltage levels in the asymmetrical configuration of factor two. However, in asymmetrical cascade converter with the factor of three, there is no adjacent switching states for the modulation between the voltage levels (Vdc/4, 2Vdc/4) and (-Vdc/4, -2Vdc/4) in the positive and negative half a cycle (dashed lines). If extra switching transient happens a few times over one fundamental cycle, extra switching losses will be negligible; however, it increases switching losses significantly if it repeatedly happens over the one cycle.

108

## Output voltage (van(t)) 4(Vin1) Vin1

3(Vin1) Vin1 2(Vin1) Vin1 1(Vin1) 2Vin1 Vin1 0 -1(Vin1) 2(Vin1) 0 -1(Vin1) -2(Vin1) -3(Vin1) 0 1(Vin1) 2(Vin1)

Cell-2

Cell-1

## Cell-2 Cell-1 Cell number

Cell number

Fig.1-68: Possible output voltages of cascade converter with n=2 to generate (a) five voltage levels (Vin2=Vin1) (b) seven voltage levels (Vin2=2Vin1) and (c) nine voltage levels (Vin2=3Vin1)

Modulation between voltage levels based on the switching states for high and low voltage H-bridge converter cells as well as the total output voltage have been illustrated in Fig.1-70 for the asymmetrical cascade converter with the factors of two and three. It can be observed that extra switching transient happens only once in the positive half a cycle with the factor two [Fig.1-70 (a)]; however, the extra switching occurs continuously with the factor of three for the modulation between Vdc/4 and 2Vdc/4, as shown in Fig.1-70 (b). This scenario happens for the negative half a cycle as well. Therefore, extra switching occurs only four times in each full cycle in the asymmetrical DC voltage arrangement with the factor of two, while the number of extra switching transients is significantly increased specifically with the factor of three. Therefore, although the asymmetrical cascade converter generates more voltage levels with the factor of three, it is not a proper selection compared to the factor of two due to the absence of adjacency between the voltage levels and, eventually, large switching losses.

109

In the asymmetrical configuration with the factor of two, each H-bridge converter cell generates three voltage levels with equal voltage steps. Therefore, in general, to fulfill the uniformity of output voltage, and preserve the adjacency for all switching states in the asymmetrical configuration with the factor of two, DC source voltage in the low voltage cells can be derived from (1- 39).

Vin(i )

Vin( n) 2n i

(i=1,,n)

(1-39)

As a result, for the two-cell converter (n=2) shown in Fig.1-67, the relationship between DC voltage sources can be obtained as:
Vin1 Vin2 2

(1-40)

Switching states in a single-phase asymmetrical two-cell cascade converter with factors of two and three Asymmetrical DC sources with the factor Asymmetrical DC sources with the of two factor of three v a1b (t ) va2b2 (t ) v a1b2 (t ) va1b (t ) va2b2 (t ) v a1b2 (t ) states states
1 1

Table 1-23

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

## 0 -2Vdc/3 2Vdc/3 0 0 -2Vdc/3 2Vdc/3 0 0 -2Vdc/3 2Vdc/3 0 0 -2Vdc/3 2Vdc/3 0

0 -2Vdc/3 2Vdc/3 0 -Vdc/3 -Vdc Vdc/3 -Vdc/3 Vdc/3 -Vdc/3 Vdc Vdc/3 0 -2Vdc/3 2Vdc/3 0

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

## 0 -3Vdc/4 3Vdc/4 0 0 -3Vdc/4 3Vdc/4 0 0 -3Vdc/4 3Vdc/4 0 0 -3Vdc/4 3Vdc/4 0

0 -3Vdc/4 3Vdc/4 0 -Vdc/4 -Vdc 2Vdc/4 -Vdc/4 Vdc/4 -2Vdc/4 Vdc Vdc/4 0 -3Vdc/4 3Vdc/4 0

110

1010

Vdc

0010

2Vdc/3

1000

0110

1011

Vdc/3

0000

1100

0011

1111

0100

1001

0111

-Vdc/3

0001

1101

-2Vdc/3

0101

-Vdc

(a)
Adjacent switching states Non-Adjacent switching states 1110 0110 1000 0000 0100 1001 0001 1101 1100 0011 0111 1011 1111

1010

## Vdc 3Vdc/4 2Vdc/4 Vdc/4 0 -Vdc/4 -2Vdc/4 -3Vdc/4 -Vdc

0010

0101

(b) Fig.1-69: Adjacent and nonadjacent switching states between different voltage levels single-phase cascade converter (a) factor of two and (b) factor of three

111

1010

Vdc

1110
Two switches change Or Extra switching

0010

2Vdc/3

1000

0110

Vdc/3

0000

1100

0100

-Vdc/3
10

2Vdc/3

10 10 10

10

10

10 10

## Switching states: Low voltage cell

00 00 00 00 00 00 00 00 00 00 00 00

Vdc/3 0

## One switch change

01 01 01 01 01 01

-Vdc/3
10 10 10 10 10 10

Vdc 2Vdc/3

## Two switches change Or Extra switching

10 10 10 00 00 00 10 00

00 10

00 00 10 10 00 00 10 10 00 10

Output voltage
00 00

01 10 00 00 00 00 00 00 00 00 01 01 00 00 01 00 00 00

01 01 10 10

Vdc/3

0 -Vdc/3

(a)

112

Vdc 3Vdc/4

2Vdc/4

Vdc/4 0

-Vdc/4

## 10 10 Switching states: High voltage cell One switch change

10

3Vdc/4

00 00 00
10 10 10 10 10 00 00 00 00 00 00 00

10 10 10

0 Vdc/4 0 -Vdc/4

## Switching states: Low voltage cell One switch change

00

00 00

01

01

01

01

01

01

01 01 01 10 10 10 10 10 10

## Three switches change Or Extra switching

01 10 10 10 10 00 00 00 01 10 01 10

## Vdc 3Vdc/4 2Vdc/4 Vdc/4 0 -Vdc/4

00 10

00 00 10 10 00 00 10 10 01 10 01 01 10 10 00 10

Output voltage
00 00 00 00 00 00 00 00 00 00 01 00 01 00 01 00

10 00

10 00

(b) Fig.1-70: Modulation between voltage levels in asymmetrical configurations with the factor of (a) two and (b) three

113

## 1.2.6.4 Voltage Rating of the Switching Components

The second technical issue associated with utilizing the unequal DC sources in the asymmetrical cascade configurations is unequal voltage stress on switching components. In other words, switching components of each H-bridge cell should be designed based on the DC link voltage of that particular cell. To verify this issue, switching state 1001 has been demonstrated in Fig.1-71. In this particular switching state, (Sa1 or Da1) and (Sa4 or Da4) from the top cell and (Sa6 or Da6) and (Sa7 or Da7) from the bottom cell are On. Therefore, (Sa2 or Da2) and (Sa3 or Da3) should block Vin1, while Vin2 is the maximum voltage across the (Sa5 or Da5) or (Sa8 or Da8). Therefore, the switching components should be chosen according to the voltage level of each H-bridge cell in the asymmetrical configuration.

a1

Sa1 Da1

Sa3 Da3

Vin1

+ Sa2 Da2

b1
Sa4 Da4

Cell 1

Sa5 Da5

Sa7 Da7

Cell 2 b2

Vin2 + -

a2
Sa6 Da6 Sa8 Da8

Fig.1-71: Equivalent circuit associated with the switching state 1001 in the asymmetrical cascade converter with two cells

Therefore, due to the different voltage rating of the switching devices in the asymmetrical cascade configuration, it loses its modularity advantage compared to the symmetrical cascade converter. Moreover, as the switching loss is proportional to the voltage stress across each switch, this imposes high switching loss in the high voltage cells. Various PWM strategies for the asymmetrical cascade converters with high and fundamental switching frequency have been presented. However, as the

114

switching losses is proportional to the voltage across switching components, special PWM strategies should be used to decrease the losses in high voltage converter cells.

Voltage (V)

Vdc/3 0 -Vdc/3

0.005

0.01

0.015

0.02

## High voltage cell

Voltage (V)
2Vdc/3 0 -2Vdc/3 0 0.005 0.01 0.015 0.02

Vdc

## Output voltage of the converter

Voltage (V)

2Vdc/3 Vdc/3 0 -Vdc/3 -2Vdc/3 -Vdc 0 0.005 0.01 Time(S) 0.015 0.02

Fig.1-72: Voltage waveforms for a single-phase two cell cascade converter. From top to bottom: Cell 1 voltage ( va1b1 (t ) ), Cell 2 voltage ( va 2 b2 (t ) ), and Output voltage ( v a1b2 (t ) )

To reduce the switching losses and improve the converter efficiency, hybrid modulations for cascade converters with unequal DC sources which allow use of the slow switching devices in the higher voltage cells and fast switching devices in lower voltage cells are proposed. The switching loss of the high voltage cell is

115

decreased by reducing the switching frequency to fundamental frequency, so that maximum achievable switching frequency of the modulator is governed by the switching frequency of the low voltage cells. A hybrid modulation at switching frequency of 5 kHz has been conducted for an asymmetrical cascade converter with factor of two (Vin2=2Vin1). The output voltages of each cell and the cascade converter are shown in Fig.1-72. As discussed, the high switching frequency is achieved for the low voltage cell, and the high voltage cell operates at the fundamental frequency (low frequency) to reduce the switching losses.

## 1.2.7 Asymmetrical Cascade Converter with Multilevel H-bridge Converters

In general, in the cascaded H-bridge converters, if each cell can generate m voltage levels at the H-bridge converter output and n is the number of H-bridge cells, the number of voltage levels at the converter output when the DC sources are equal (Vin1=Vin2==Vin(n)) can be found by (1-41). N=n (m-1) +1 (1-41)

According to (1-41), a higher-level converter can easily be implemented by increasing either the number of H-bridge converter cells (n) or using a higher level H-bridge converter (m) in this configuration. As mentioned, adding extra H-bridge cells impel more separated DC power supplies to the system.

An alternative way to enhance the output voltage quality with a minimum number of components in the cascade structure is to replace the two-level H-bridge converters with the multilevel H-bridge converters in this structure. This structure is called a hybrid converter. The structure of a cascaded H-bridge hybrid converter, where each cell can be either two-level or multilevel H-bridge converter, is demonstrated in Fig.1-73. As discussed in the previous section, single-phase n-level diodeclamped and flying capacitor structures can be considered as multilevel H-bridge converters with (m=2n-1) voltage levels at the output voltage. The number of cells depends on the desired output voltage level and the combination of two-level or multilevel H-bridge cells.

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Finding a proper DC voltage ratio between the separated DC sources of the series cells can increase the number of output voltage levels for a given power circuit (See Fig.1-73) with the equivalent number of components. Different DC voltage ratios for H-bridge cells have been proposed to achieve the maximum number of output voltage levels. For example, a hybrid converter including an H-bridge two-level converter and an m-level H-bridge multilevel converter is investigated and is shown in Fig.1-74. This configuration is a hybrid configuration in which the number of components can be minimized. The analysis in terms of the number of voltage levels in this converter has been performed in this section.
Two-level H-bridge converter

Vin1

+ -

H-bridge cell

+ vout 1(t) -

+
H-bridge diode-clamped converter

Vin2

+ -

H-bridge cell

+ vout 2 (t) -

vout (t)

Vin(n)

+ -

H-bridge cell

+ vout (n)(t) -

## Fig.1-73: Topology of cascaded H-bridge converters

To achieve maximum voltage levels at the output voltage of the two-cell proposed topology, as for (1-39), the output voltage levels of the multilevel H-bridge converter should be divided into equal voltage levels using switching states of the low cell converter. In this manner, the DC voltage arrangement can be considered as follows:

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Vin1

## voltage step of the multilevel inverter 2

(1-42)

Based on this arrangement, the number of output voltage levels can be derived from (1-43):

2 m 1

(1-43)

where m is the number of output voltage levels of the multilevel H-bridge converter. Regarding (1-43), the number of output voltage levels is increased by raising the multilevel H-bridge output voltage levels, in which extra switches and DC capacitors are required.

+
Vin1
+ -

vout 1(t)

vout(t)

Vin2

+ -

+ vout 2(t) -

## High voltage cell

Fig.1-74: Block diagram of a cascade converter including an m-level single-phase multilevel converter in series with a two-level H-bridge converter

According to the asymmetrical configurations for diode-clamped or flying capacitor converters (which are analyzed in the previous section), using asymmetrical configuration in the DC link voltage of these converters leads to an increase in the output voltage levels without increasing the number of components in the multilevel H-bridge structure. The use of both symmetrical and asymmetrical configurations for H-bridge multilevel converters in the proposed two-cell hybrid cascaded topology should be analyzed in the case of uniform voltage, adjacent switching states, and break down voltage of the switching components. As an example, this issue will be comparatively investigated for two-level H-bridge multilevel

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converters connected in series with the four-level single-phase symmetrical and asymmetrical diode-clamped configurations. Example 1: a two-level H-bridge converter connected in series with a symmetrical four-level diode-clamped H-bridge converter Since an effective asymmetrical configuration is available for more than three-level diode-clamped converter in case of adjacent switching states, a symmetrical fourlevel diode-clamped H-bridge converter is utilized in the configuration of the cascade converter to have a comparative study. A four-level diode-clamped Hbridge converter can synthesize (24-1=7) different voltage levels at the output voltage, as previously discussed. Fig.1-75 illustrates a cascade converter assembled from one module of a low voltage two-level H-bridge converter and high voltage four-level diode-clamped H-bridge converter. According to the symmetrical structure of the four-level H-bridge converter, each DC link capacitor is regulated at Vin2/3 ( VC1
VC2 VC3

## Vin2/3). According to Table 1-14, minimum voltage step

in output voltage of the symmetrical four-level H-bridge converter is Vin2/3. Therefore, to meet (1-42), the DC source ratio of H-bridge cells should be considered as follows: Vin2=6Vin1 (1-44)

Therefore, referring to (1-43), fifteen different voltage levels are expected be achieved on output voltage as m=7. Possible voltage levels for the symmetrical fourlevel diode-clamped and two-level H-bridge converters with relevant output voltage levels are shown in Fig.1-76. As shown, voltage levels of the diode-clamped Hbridge converter are divided equally to the smaller voltage levels by the DC voltage of the low voltage cell. Some voltage levels can be achieved with more than one possible combination of voltage levels, which can increase the choice of adjacency between voltage levels.

Assuming that total DC voltage at the input side is Vdc (Vin1+Vin2=Vdc ), Vin1=Vdc/7 and Vin2=6Vdc/7 with respect to (1-44), switching states in each H-bridge cell associated with different voltage levels in a two-cell cascade converter are summarized in Table 1-24. In Fig.1-77, adjacency of switching states according to Table 1-24 are depicted and shows all output voltage levels of the proposed topology. Therein, switching states at the center of each square (blue) are the

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switching states associated with the high voltage symmetrical diode-clamped Hbridge converter and switching states around each square (red) belong to the low voltage two-level H-bridge converter. By this means, three different voltage levels can be generated around each voltage level of the diode-clamped output voltage.
a1

Sa1 Da1

Sa3 Da3

Vin1

b1

VC1
+

Dca3

Sa7 Da7 a2

Dcb3

Sb13 Db13 b2

## High voltage cell

Vin2

+ -

VC2

C2 Dca2 Sa8 Da8 + Dca4 C3 Sa10 Da10 Sb16 Db16 Sa9 Dcb4 Da9 Sb15 Db15 Dcb2 Sb14 Db14

VC3
-

Fig.1-75: Two-cell cascade converter topology with series connection of two-level H-bridge converter and four-level diode-clamped H-bridge converter Also, it is apparent that adjacent switching states are available between all switching states for modulation between consecutive voltage levels. To implement this number of voltage levels, with a regular symmetrical cascade converter, seven two-level Hbridge converter cells are necessary. This imposes four more DC sources and twelve switches in comparison to the proposed hybrid cascade converter. Also, when

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compared with series multilevel connection, this configuration needs capacitor voltage balancing for just one cell of the converter, and this can reduce the complexity of control and structure of the converter.

## Output voltage (v a1b2 (t ) )

(Vin2+ Vin1) Vin1 Vin2/3 (Vin2) (Vin2-Vin1) or (2Vin2/3+ Vin1) (2Vin2/3) Vin2/3 (2Vin2/3- Vin1) or (Vin2/3+ Vin1) (Vin2/3) Vin2/3 (Vin2/3- Vin1) or (Vin1) 0 -(Vin2/3- Vin1) or -(Vin1) -(Vin2/3) -(2Vin2/3- Vin1) or -(Vin2/3+ Vin1) -(2Vin2/3) -(Vin2-Vin1) or -(2Vin2/3+ Vin1) -(Vin2) -(Vin2+ Vin1)

## Cell-2 Cell-1 Cell number

Fig.1-76: Possible output voltages of each H-bridge converter cell to generate fifteen voltage levels in cascade converter based on series two-level H-bridge and symmetrical four-level diode-clamped H-bridge converter (Vin2=6Vin1)

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Table 1-24 Output voltage levels for different switching states of the two-level converter, single-phase four-level symmetrical diode-clamped converter, and the proposed fifteen-level H-bridge cascaded converter topology
Two-level H-bridge converter (Low voltage cell) Switching states Sa1 Sa3

v a1b1 (t )

00 0 0 0 10 1 0 Vdc/7 01 0 1 -Vdc/7 11 1 1 0 Symmetrical diode-clamped H-bridge converter (High voltage cell) Switching states v a b (t ) S S S S S S
a5 a6 a7 a11 a12 a13
2 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 1 0 1 1 0 0 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 Proposed fifteen-level hybrid converter Modulation levels v a1b2 (t ) v a2b2 (t ) 7Vdc/7 6Vdc/7 5Vdc/7 4Vdc/7 3Vdc/7 2Vdc/7 Vdc/7 0 -Vdc/7 -2Vdc/7 -3Vdc/7 -4Vdc/7 -5Vdc/7 -6Vdc/6 6Vdc/7 5Vdc/7 4Vdc/7 3Vdc/7 2Vdc/7 Vdc/7 0 -Vdc/7 -2Vdc/7 -3Vdc/7 -4Vdc/7 -5Vdc/7 -6Vdc/7 -7Vdc/7 6Vdc/7 6Vdc/7 4Vdc/7 4Vdc/7 2Vdc/7 2Vdc/7 0 0 -2Vdc/7 -2Vdc/7 -4Vdc/7 -4Vdc/7 -6Vdc/7 -6Vdc/7

000000 000001 000011 000111 001000 001001 001011 001111 011000 011001 011011 011111 111000 111001 111011 111111

0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1

0 -2Vdc/7 -4Vdc/7 -6Vdc/7 2Vdc/7 0 -2Vdc/7 -4Vdc/7 4Vdc/7 2Vdc/7 0 -2Vdc/7 6Vdc/7 4Vdc/7 2Vdc/7 0

v a1b1 (t )
Vdc/7 -Vdc/7 Vdc/7 -Vdc/7 Vdc/7 -Vdc/7 Vdc/7 -Vdc/7 Vdc/7 -Vdc/7 Vdc/7 -Vdc/7 Vdc/7 -Vdc/7

0 0 0 0 0 0 0 0 0 0 0 0 0 0

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10 11 10 01 11 10 01 11 10 01 11 111111 00 01 11 011111 01 11 001111 01 11 000111 01 00 00 10 01 11 10 01 00 10 01 11 000011 00 011011 00 10 01 11 001011 00 10 01 11 000001 00 111011 00 10 01 11 001001 00 10 01 11 011001 00 10 01 11 000000 00 111001 00 10 01 11 001000 00 10 11 011000 00 10 111000 00 10

7Vdc/7 6Vdc/7 5Vdc/7 4Vdc/7 3Vdc/7 2Vdc/7 Vdc/7 0 -Vdc/7 -2Vdc/7 -3Vdc/7 -4Vdc/7 -5Vdc/7 -6Vdc/7 -7Vdc/7

Fig.1-77: Adjacent switching states graph of a two-cell hybrid cascade converter with series symmetrical single-phase four-level diode-clamped converter and twolevel converter Example 2: A two-level H-bridge connected in series with an asymmetrical four-level diode-clamped H-bridge converter (1-44) shows that there is still a possibility to increase the number of voltage levels without increasing the number of power components by utilizing the asymmetrical multilevel H-bridge converter in the high voltage cell (as discussed in the first part of this section). To investigate this issue, the high voltage cell in Fig.1-75 is

replaced by an asymmetrical four-level diode-clamped H-bridge converter where the bottom capacitor voltage is twice that of the others ( VC3
2VC1 2VC2 ). Regarding

switching states of the asymmetrical configuration of the four-level diode-clamped converter in Table 1-15, nine different voltage levels can be achieved in output voltage, instead of the seven voltage levels of the symmetrical configuration. Using this configuration, DC link capacitor voltage should be regulated as:
VC1 VC2 VC3

## Vin2/4 Vin2/4 Vin2/2 (1-45)

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Therefore, minimum voltage step in output voltage of the asymmetrical four-level H-bridge converter is Vin2/4. To achieve maximum voltage levels by preserving the adjacent switching states between all voltage levels, (1-42) defines the DC sources ratio of the H-bridge cell as follow: Vin1=Vin2/8 (46)

Fig.1-78 demonstrates all possible voltage levels which can be obtained in output voltage of the hybrid cascade converter with series connection of the asymmetrical four-level diode-clamped and two-level H-bridge converters. As shown, four more voltage levels can be synthesized in output voltage with the same number of components as the two-cell hybrid converter using the symmetrical diode-clamped H-bridge converter in the high voltage cell.

If assumed that the total output voltage is Vdc (Vin1+Vin2=Vdc), Vin1=Vdc/9 and Vin2=8Vdc/9 in order to satisfy (1-46). Table 1-25 illustrates all the switching states associated with different voltage levels in each converter cells, as well as illustrating the total output voltage of the proposed two-cell hybrid cascade converter using low and high voltage cell switching states. Adjacent switching states of the hybrid cascade converter using series connection of the asymmetrical diode-clamped and two-level H-bridge converters are depicted in Fig.1-79. Herein, switching states located at the middle of each square (blue) are the switching states of the high voltage cell (asymmetrical diode-clamped H-bridge converter), while switching states at the corner of each square (red) belong to the two-level converter. According to this graph, adjacent switching states are available between all consecutive voltage levels. It is clear that to modulate between voltage levels, the high voltage cell should operate at a fundamental frequency and the low voltage cell governs the actual switching frequency of the converter system to share the losses equally between cells. This issue can be observed in Fig.1-80 for both of the proposed hybrid cascade converters with symmetrical and asymmetrical four-level diodeclamped H-bridge converters.

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Output voltage ( v a1b2 (t ) ) Vin1 Vin2/4 Vin2/4 Vin2/4 Vin2/4 (Vin2+ Vin1) (Vin2) (Vin2-Vin1) or (3Vin2/4+Vin1) (3Vin2/4) (3Vin2/4- Vin1) or (2Vin2/4+Vin1) (2Vin2/4) (2Vin2/4- Vin1) or (Vin2/4+Vin1) (Vin2/4) (Vin2/4- Vin1) or (Vin1) 0 -(Vin2/4- Vin1) or -(Vin1) -(Vin2/4) -(2Vin2/4-Vin1) or -(Vin2/4+Vin1) -(2Vin2/4) -(3Vin2/4- Vin1) or -(2Vin2/4+Vin1) -(3Vin2/4) -(Vin2-Vin1) or -(3Vin2/4+Vin1) -(Vin2) -(Vin2+ Vin1) Cell-2 Cell-1 Cell number

Fig.1-78: Possible output voltages of the cascade converter based on series two-level and asymmetrical four-level diode-clamped H-bridge converters (Vin2=8Vin1) As shown in Fig.1-80, the higher voltage levels are generated by the diode-clamped converter which works in a low frequency and the modulation between voltage levels occurring by the two-level converter cell based on a high switching frequency. As the modulation between voltage levels occurs in the two-level converter, adjacent switching states are available between all voltage levels. However, some non adjacent switching states take place when the high voltage cell needs to change the voltage level. As this condition happens just a few times in each fundamental cycle, extra losses produced by these switching states are negligible when compared to the total switching frequency of the converter.

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10 11 10 11 10 01 11 10 11 10 01 11 111111 01 11 011111 01 11 00 10 001111 01 11 10 01 11 000111 01 00 000011 00 00 10 01 11 00 11 10 011011 01 00 11 111001 01 111011 00 10 10 00 11 001000 00 10 01 11 011001 00 10 000000 01 00 00 011000 01 00 10 111000 00

9Vdc/9 8Vdc/9 7Vdc1/9 6Vdc1/9 5Vdc1/9 4Vdc1/9 3Vdc1/9 2Vdc1/9 Vdc1/9 0 -Vdc1/9 -2Vdc1/9 -3Vdc1/9 -4Vdc1/9 -5Vdc1/9 -6Vdc1/9 -7Vdc1/9 -8Vdc1/9 -9Vdc1/9

## 01 11 001001 00 10 01 11 001011 10 01 000001 00

Fig.1-79: Adjacent switching states graph of two-cell hybrid cascade converter with series symmetrical single-phase four-level diode-clamped converter and two-level converter

Output voltage of the hybrid cascade converter based on series connection of twolevel converter with symmetrical and asymmetrical four-level diode-clamped Hbridge converter is shown in Fig.1-81. It is clear that using an asymmetrical diodeclamped converter in the configuration of the cascade hybrid converter can increase the number of voltage levels with the same number of components and the same structure.

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Table 1-25 Output voltage levels for different switching states of the two-level converter, single-phase four-level symmetrical diode-clamped converter, and the proposed fifteen-level H-bridge cascaded converter topology (Vdc2=8Vdc1)
Two-level H-bridge converter (Low voltage cell) Switching states Sa1 Sa3

v a1b1 (t )

00 0 0 0 10 1 0 Vdc/9 01 0 1 -Vdc/9 11 1 1 0 Asymmetrical diode-clamped H-bridge converter (High voltage cell) Switching states v a b (t ) S S S S S S
a5 a6 a7 a11 a12 a13
2 2

0 0 0 0 0 0 0 0 0 0 0 0 1 -4Vdc/9 0 0 0 0 1 1 -6Vdc/9 0 0 0 1 1 1 -8Vdc/9 0 0 1 0 0 0 4Vdc/9 0 0 1 0 0 1 0 0 0 1 0 1 1 -2Vdc/9 0 0 1 1 1 1 -4Vdc/9 0 1 1 0 0 0 6Vdc/9 0 1 1 0 0 1 2Vdc/9 0 1 1 0 1 1 0 0 1 1 1 1 1 -2Vdc/9 1 1 1 0 0 0 8Vdc/9 1 1 1 0 0 1 4Vdc/9 1 1 1 0 1 1 2Vdc/9 1 1 1 1 1 1 0 Proposed Fifteen-level Hybrid Converter Modulation levels ( v a1b2 (t ) ) v a2b2 (t ) v a1b1 (t ) 9Vdc/9 8Vdc/9 0 Vdc/9 8Vdc/9 8Vdc/9 7Vdc/9 0 -Vdc/9 8Vdc/9 7Vdc/9 6Vdc/9 0 Vdc/9 6Vdc/9 6Vdc/9 5Vdc/9 0 -Vdc/9 6Vdc/9 5Vdc/9 4Vdc/9 0 Vdc/9 4Vdc/9 4Vdc/9 3Vdc/9 0 -Vdc/9 4Vdc/9 3Vdc/9 2Vdc/9 0 Vdc/9 2Vdc/9 2Vdc/9 Vdc/9 0 -Vdc/9 2Vdc/9 Vdc/9 0 0 Vdc/9 0 0 -Vdc1/9 0 -Vdc/9 0 -Vdc/9 -2Vdc/9 0 Vdc/9 -2Vdc/9 -2Vdc/9 -3Vdc/9 0 -Vdc/9 -2Vdc/9 -3Vdc/9 -4Vdc/9 0 Vdc/9 -4Vdc/9 -4Vdc1/9 -5Vdc/9 0 -Vdc/9 -4Vdc/9 -5Vdc/9 -6Vdc1/9 0 Vdc/9 -6Vdc/9 -6Vdc/9 -7Vdc1/9 0 -Vdc/9 -6Vdc/9 -7Vdc/8 -8Vdc/9 0 Vdc/9 -8Vdc/9 -8Vdc/9 -9Vdc/9 0 -Vdc/9 -8Vdc/9

000000 000001 000011 000111 001000 001001 001011 001111 011000 011001 011011 011111 111000 111001 111011 111111

127

Fifteen-level converter Voltage levels Extra switching 3Vdc/8 2Vdc/8 Vdc/8 0 -Vdc/8 00 10 00

Nineteen-level converter Voltage levels 10 3Vdc/9 11 2Vdc/9 Vdc/9 0 -Vdc/9 2Vdc/9 or 2Vdc/8

111011 01

111111 01

11

Output voltage Vdc/9 or Vdc/8 0 111011 High voltage cell switching states Extra switching Vdc/9 or Vdc/8 0

111111

## 0 0 0 1 0 0 Low voltage cell switching states 0 0 1 0 1 0 1 01 0 0 0 0 0 00 0 0 0 0 1 0 1 0 0 0 0 1 0 1

Fig.1-80: Modulation between voltage levels in a hybrid cascade converter using symmetrical and asymmetrical four-level diode-clamped H-bridge converters in the high voltage cell

To have nineteen voltage levels in output voltage of the regular cascade converter using two-level H-bridge converter cells with identical DC sources, nine converter cells are required. These have twenty switches and seven DC sources more than the proposed hybrid cascade converter with the asymmetrical four-level diode-clamped converter. This can decrease the number of components in the system and maximize the number of output voltage levels to increase the quality of waveforms. However,

128

capacitor voltage balancing should be taken into account for the high voltage multilevel converter cell as it can be solved either by a proper modulation technique or frontend converters.

(a)

(b) Fig.1-81: Output voltage of the hybrid cascade converter based on series connection of two-level H-bridge converter and single-phase (a) symmetrical and (b) asymmetrical four-level diode-clamped converter

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1.2.8 Conclusions
Advantages of the multilevel converter are magnified by increasing the number of output voltage levels. However, the number of output voltage levels is proportional to the number of power components in different types of multilevel converters. Therefore, to increase the output voltage resolution, the extra cost and complexity of the system should be tolerated. An asymmetrical multilevel converter is a solution to increase the output voltage quality in regular multilevel converters without increasing the number of the components. Using unequal DC link in different configuration may lead to an increase in the number of voltage levels with the same number of components by elimination of redundant switching states.

Different asymmetrical configurations based on diode-clamped, flying capacitor and cascade converters are presented in this chapter. However, along with output voltage maximization, some technical issues should be taken into account at the design stage unequal DC link arrangement. Uniform output voltage is important to create a modular and simple control strategy. Adjacent switching states are necessary between voltage levels to minimize the number of switching transitions and to reduce switching noise and losses. A reduction in redundant switching states to increase the number of obtainable voltage levels may lead to a decrease in the freedom of control over capacitor voltage balancing in asymmetrical configuration and should be considered based on current loops. All of these technical issues should be taken into account to have a proper asymmetrical configuration.

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