Full adder

A full adder is a logical circuit that performs an addition operation on three one-bit binary numbers often written as A, B, and Cin. The full adder produces a two-bit output sum typically represented with the signals Cout and S where . The full adder's truth table is:

A full adder can be implemented in many different ways such as with a custom transistor-level circuit or composed of other gates. One example implementation is with and .

Example full adder circuit diagram using only NAND and XOR gates Inputs: {A, B, Cin} Outputs: {S, Cout}

Inverter(logic gate)

In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. The truth table is shown: NPUT OUTPUT A 0 1 NOT A 1 0

This represents perfect switching behavior, which is the defining assumption in Digital electronics. In practice, actual devices have electrical characteristics that must be carefully considered when designing inverters. In fact, the non-ideal transition region behavior of a CMOS inverter makes it useful in analog electronics as a class A amplifier (e.g., as the output stage of an operational amplifier).

And gate

INPUT OUTPUT A 0 0 1 1 B A AND B 0 1 0 1 0 0 0 1

The AND gate is a digital logic gate that implements logical conjunction - it behaves according to the truth table to the right. A HIGH output (1) results only if both the inputs to the AND gate are HIGH (1). If neither or only one input to the AND gate is HIGH, a LOW output results. In another sense, the function of AND effectively finds the minimum between two binary digits, just as the OR function finds the maximum.

Or gate
INPUT OUTPUT A B A+B 0 0 1 1 0 1 0 1 0 1 1 1

The OR gate is a digital logic gate that implements logical disjunction - it behaves according to the truth table to the right. A HIGH output (1) results if one or both the inputs to the gate are HIGH (1). If neither input is HIGH, a LOW output (0) results. In another sense, the function of OR effectively finds the maximum between two binary digits, just as the complementary AND function finds the minimum.

2- 4 decoder

A decoder is a device which does the reverse of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. e.g. n-to2 , binary-coded decimal decoders. Enable inputs must be on for the decoder to function, otherwise its outputs assume a single "disabled" output code word. Decoding is necessary in applications such as datamultiplexing, 7 segment display and memory address decoding. The example decoder circuit would be an AND gate because the output of an AND gate is "High" (1) only when all its inputs are "High." Such output is called as "active High output". If instead of AND gate, the NAND gate is connected the output will be "Low" (0) only when all its inputs are "High". Such output is called as "active low output".
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Implementation using VHDL

This project we make to design a 1-bit ALU. In additon to check and verify the operation of the ALU.

VIEW TECHNOLOGY SCHEMATIC 1

SCHEMATIC 2

VIEW RTL SCHEMATIC

AND2

INV

OR GATE

DECODER U0

FULL ADDER U7

Logic simulation

TESTBENCH WAVEFORM

The result show that 1-bit ALU is function properly. When we see the a0(F0)=0 and a1(F1)=1 the waveform show that the operation do the AND process. So the result for output g0(Z)=0. The result show that the 1-bit Arithmetic and logic unit(ALU) function properly.

SC

Schematic circuit design of 1 bit alu ADD When the F0=0 and F1=0 the the decoder will select to do the ADD process. So the AND process,OR process and the NOT process will off because it receive logic 0(off). The FULL ADDER will operate to do the ADD process. Assume that A=0,B=1 and Cin=0 the result for sum=1 and Cout=0. AND When the F0=0 and F1=1 the the decoder will select to do the AND process. So that another process is off because they receive logic 0. The AND gate will operate to do the operation AND. The input we assume A=1 and B=1 so the output Z=1. OR When the F0=1 and F1=0 the the decoder will select to do the OR process. The OR gate will receive logic 1 so that it will operate and another gate will receive logic 0(off). Assume the input A=0 and B=0 so that the output Z=1. NOT When the F0=1 and F1=1 the the decoder will select to do the NOT process. So the another gate will off because it receive logic 0(off). The OR gate will operate to do the OR process. Assume that A=1 the result for output Z=0.