ARM processor processor architecture block diagram and signals Core block diagram

clock control configuration interrupts initialization

Interfacing signals
mclk wait eclk bigend irq q isync reset enin enout enouti abe ale ape dbe tbe busen highz busdis ecapclk A[31:0] Din[31:0] Dout[31:0] D[31:0] bl[3:0] r/w mas[1:0] mreq seq lock trans mode[4:0] abort Tbit

memory interface

bus control

MMU interface state

ARM7TDMI core

dbgrq breakpt dbgack exec extern1 extern0 debug dbgen rangeout0 rangeout1 dbgrqi commrx commtx

tapsm[3:0] ir[3:0] tdoen tck1 tck2 screg[3:0] drivebs ecapclkbs icapclkbs highz pclkbs rstclkbs sdinbs sdoutbs shclkbs shclk2bs TRST TCK TMS TDI TDO

TAP information

boundary scan extension

coprocessor interface power

opc cpi cpa cpb Vdd Vss

JTAG controls

It has 16 32-bit registers identified as r0-r15 in any operating mode. r13 used as stack pointer ; r14 used as link register (return address from subroutine) r15 used as programme counter. Current processor state is stored in CPSR. ARM uses 3-stage instruction pipeline- fetch, decode and execute. As there is no separate instruction/signal for I/O, so all I/O interface is memory mapped. It has seven progamming mode-user , system,supervisor, abort, undermined, IRQ and FIQ. User- normal programming mode, no privilege (rest of the modes are privileged) system - programming mode(user), with some privilege supervisor privileged mode (for OS) abort for memory protection(virtual mode) undermined emulation of co-processor IRQ normal interrupt mode FIQ fast interrupt mode (can further interrupt irq mode)

Each mode has its specific register set and status register. r15 and CSPR remain common in all modes. Except system mode which shares all registers of user mode, FIQ has 7(r8-r14), supervisor, abort, undermined and irq each has 2 (r13-r14) specific registers, all these five modes have one each SPSR(saved programme status register) register (total 37 registers) During function call , the registers are named as- r0-r3 named a1 to a4 (argument registers, for passing values, need not to be preserved , result returned in r0-r1) r4-r9 named as v1-v6 (variable registers, used internally by functions, must not be preserved) r10 named sl (stack limit/stack chunk handle) r11 named fp (frame pointer, contains zero, or points to stack backtrack structure) r12 named ip (procedure entry temporary work space) r13 named sp (stack pointer, fully descending stack, points to lowest free word) r14 named lr (lisk register, return address at function exit) r15 named pc (programme counter) After subroutine return v1-v6,sl, fp, and sp must be the same as they were before subroutine call. All instructions are 32-bit wide, therefore PC is word aligned (32-bit). On power on processor starts from 00000000H Seven types of exceptions are supported which points to predefined locations (vector) exception vector address reset 00000000 undermined inst. 00000004 software interr. 00000008 prefetch(inst) abort 0000000C data abort 00000010 IRQ 00000018 FIQ 0000001C (address location 00000014 is reserved , not used ). At these vector address instruction B label to execute routines stored at label. When exception occurs 1. copy CPSR to SPSR_mode 2. sets appropriate flags in CPSR 3. maps in appropriate banked(mode) registers 4. stores the return address in LR_mode register 5. set PC(r15) to vector address (as per exception source) on return to main programme 1. restore CPSR from SPSR_mode 2. restore PC from LR_mode register

instruction set (ARM core instructions) format of instruction set- basically there are three types of instructions data processing, branch and load/store (DP , DT and BR identified by bit 27-26 as instruction format) basic format of data processing instruction
Cond opcode S Rn Rd Operand2

Cond field(4bit) specify current status of ALU flags and instruction can conditionally executed. There are 15 conditions based of ALU operation that affects sign (N), zero (Z), carry(C) and overflow (V) flags. These conditions areEQ(z=1) NE(z!=1) HS/CS(c=1) LO/CC(c =0) MI(n=1) PL(n=1) VS(v=1) VC(v=0) HI(c=1 and z=0) LS(c=0 or z=1) GE(v=n) LT(v!=n) GT(z=0 and v=n) LE (z=1 or v!=n) S field(1-bit) is used to affect flags in CPSR if set, as all ALU operation does not affect the flags Rn is first source operand (4-bit field) operand2 is second source operand (12-bit field) Rd is destination register (4-bit field) operand2 has two modes (1) immediate data (2) data in register immediate data : format is #immed_8r it takes 8-bit constant (0-255) , (not 0-4095, maximum possible with 12-bit) this 8-bit data is rotated right through an even number of positions . ( ROR by 0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30) , 16 options (4-bit) possible this gives larger than 4096 (but only even numbers) format of operan2 is #rot count 8-bit immediate When second operand in register Rm {, shift}; Rm is holding second source operand, which can be shifted ; shift <shift_type> # shift_count (Rm itself is not affected by shift operation) shift_types (2-bit) ASR n arithmetic right shift n bits 1=n=32 (divide by 2n) LSL n logical left shift n bits 0=n=31 (multiply by 2n) LSR n logical right shift n bits 1=n=32 ( divide by 2n) ROR n rotate right n bits 1=n=31 RRX rotate right one bit with extended (carry) (when the value of n is provided in another register Rs, only first (LSB) byte is considered) format of operan2 when count (5-bit) are provided as immediate. 4-bit for Rm and Rs #shift count shift_type 0 Rm When shift count in register Rs 0 shift_type 1 Rm [cond] and [S] are optional, used if required Arithmetic/ Logical instructions- cond and S fields are optional , unless S is used, flags are not affected syntax : <operation>[cond][S] Rd, Rn, operand2 ; arithmetic operations affects if set S, N, Z , C, V flags ADD (add) , ADC (add with carry), Sub (subtract), SBC (subtract with carry), RSB (reverse

subtraction, op2-op1) , RSC ( reverse subtraction with carry) multiply instructions- operands are in registers, affects if set S, only N and Z flags syntax : MUL[cond][S] Rd, Rm, Rs ; Rd=Rm*Rs MLA[cond][S] Rd, Rm, Rs ,Rn ; Rd=Rm*Rs+Rn ; multiply and add un/ signed long multiplications UMLL[cond][S] RdHi, RdLo, Rm, Rs ; RdLo=Rm*Rs (low word) , RdHi=Rm*Rs (high word) ; UMLAL[cond][S] RdHi, RdLo, Rm, Rs ; RdLo=Rm*Rs+RdLo (low word) , RdHi=Rm*Rs +RdHi+C (high word) ; SMLL[cond][S] RdHi, RdLo, Rm, Rs ; RdLo=(signed)Rm*Rs (low word) , RdHi=(signed)Rm*Rs (high word) ; SMLAL[cond][S] RdHi, RdLo, Rm, Rs ; RdLo=(signed)Rm*Rs+RdLo (low word) , RdHi=(signed)Rm*Rs +RdHi+C
(high word) ; (RdHi, RdLo any general purpose register)

(logical operation affects N,Z and C flags if S set)

AND (logical AND), EOR (logical XOR) , ORR (logical OR), BIC (bit set; op1 AND (NOT(op2)) ) (shift and rotates are not separate instructions, but included in operand2) comparison does not affects operand but flags. syntax : <operation>[cond]Rn, operand2 CMP (subtraction), CMN (addition) , TST (logical AND), TEQ(logical XOR) data movement- load destination register from operand2 syntax : <operation>[cond][S] Rd, operand2 MOV (move operand2) , MVN (NOT of operand2) MRS[cond] Rd, SPSR ; saved programme status register to register MRS[cond] Rd, CPSR ; MSR[cond] SPSR,Rm ; load saved programme status register from register MSR[cond] CPSR,Rm ; MSR[cond] SPSR_f,#32_bit_immed ; load flags in saved programme status register from immediate MSR[cond] CPSR_f,#32_bit_immed ; Branch operations-to control the flow of execution, the destination address is PC+8+4*label_address. (PC+8 because of pipelining). lable_address is signed 24-bit immediate number. As all instructions are 32-bit aligned, EA is calculated by shifting 2-bit left B[cond] label BL[cond] label ; R15=label_address, return address NOT saved ; R14=R15 , save return address in link register ; R15=label_address

Addressing modes used in load / store operations A 1.immediate offset - +/- 12-bit unsigned immediate number is added to base register to get the effective address (EA) of source operand LDR r2, [r0, # 8] ; EA= r0 +8 ; r0 remains unchanged 2.immediate offset pre-indexed before read base register is modified with immediate offset. LDR r2, [r0, # -8]! ; EA= r0=r0 -8 ; r0 changed before read operation 3.immediate offset post-indexed after read base register is modified with immediate offset. LDR r2, [r0], # -8 ; EA= r0 ; then r0=r0-8 ; r0 changed after read operation B 1.register offset +/- another register added to base register to get the effective address (EA) of ource

operand LDR r2, [r0, r1] ; EA= r0 +r1 ; r0 remains unchanged 2. register offset pre-indexed before read base register is modified with another register. LDR r2, [r0, -r1]! ; EA= r0=r0 -r1 ;, read from r0 , r0 changed before read operation 3. register offset post-indexed after read base register is modified with another register. LDR r2, [r0], -r2 ; EA= r0 ; read from r0 then r0=r0-r2 ; r0 changed after read operation C 1.scaled register offset - +/- another register with shift operation added to base register to get the effective address (EA) of source operand, another register remains unchanged (shift operation ASR n, LSL n, LSR n , ROR n, RRX , where n (8_bit_immed) shift count) LDR r2, [r0, r1 LSL #2] ; EA= r0 +r1*4 ; r0 remains unchanged 2. scaled register offset pre-indexed before read base register is modified with another register. LDR r2, [r0, -r1 ASR#3]! ; EA= r0=r0 -r1/8 ;, read from r0 , r0 changed before read operation 3. scaled register offset post-indexed after read base register is modified with another register. LDR r2, [r0], -r2 RRX ; EA= r0 ; read from r0 then r0=r0-r2 ; r0 changed after read operation ** D PC relative used in branching Data transfer operationsread from memory LDR[cond] Rd, [address-mode1] ; read word from specified effective address as per addressing mode LDR[cond]B Rd, [address-mode1] ; read byte from specified effective address as per addressing mode LDR[cond]H Rd, [address-mode1] ; read half word from specified effective address as per addressing mode
(use SB and SH for signed byte and half word )

multiple block operation- multiple register can be read from / save into memory with single instruction. (but not within single machine cycle) The specified registers are read/ written as per little endian that is lowest register in specified register list goes to lowest memory location/ lowest memory location goes to lowest register.Base register points to the beginning address ,which can be incremented/ decremented before/after each successive read/ write. Base register may or may not be updated after the completion of instruction. This gives four typeIncrement after(IA)- base register is incremented after read/write operation Increment before(IB)- base register is incremented before read/write operation decrement after(DA)- base register is decremented after read/write operation decrement after(DB)- base register is decremented before read/write operation ARM supports both type of stacks stack grows down (default) or stack grows up . The stack pointer also has two types -points to top of stack(default full stack) or points to next to top of stack(empty stack). These option gives four types of stack operations (basically multiple load/store) full descending stack STMFD/LDMFD (default) full ascending stack STMFA/LDMFA empty descending stack STMED/LDMED empty ascending stack STMEA/LDMEA
Cond 100 P U S W L Rn 16-BIT REGISTER LIST

P-pre/post U-up/down S- W-no/writeback into base L-load/store ,one bit for each register option ! updates base register (writeback)

multiple read (block data operation ; also stack operation POP) LDM[cond]IB Rd[!],<reg_list> ; increment base register before read LDM[cond]IA Rd[!],<reg_list> ; increment base register after read, LDM[cond]DB Rd[!],<reg_list> ; decrement base register before read LDM[cond]DA Rd[!],<reg_list> ; decrement base register after read (with reference to stack POP,replace IA ->FD , IB->ED, DA->FA, DB->EA and use pc as base register with writeback ) store in memory STR[cond] Rd, [address-mode] ; save word at specified effective address as per addressing mode STR[cond]B Rd, [address-mode] ; save byte at specified effective address as per addressing mode STR[cond]H Rd, [address-mode] ; save half word at specified effective address as per addressing mode multiple read (block data operation ; also stack operation PUSH) STM[cond]IB Rd[!],<reg_list> ; increment base register before write STM[cond]IA Rd[!],<reg_list> ; increment base register after write STM[cond]DB Rd[!],<reg_list> ; decrement base register before write STM[cond]DA Rd[!],<reg_list> ; decrement base register after write (with reference to stack PUSH,replace IA ->EA , IB->FA, DA->ED, DB->FD and base register is pc with writeback ) (for un/signed Byte/Halfword load/store operation offset is 8-bit immediate , or register offset without shift ) Swap instruction atomic operation of memory read and memory write a byte or word. Exchange of contents of register and memory. Memory is pointed by swap register [Rn]. First read from [Rn],then Rm is written to swap address ,then write old memory data in Rd. [when Rd and Rm are same registers then it is exchange of content of memory and register). SWAP[cond] Rd,Rm, [Rn] ; Rm is loaded to [Rn], SWAP[cond]B Rd,Rm, [Rn] ; swap byte Software interrupt to enter to supervisor mode (OS), vector address 0X08, PC is saved in LR_svc and CPSR is saved in SPSR_svc. 24-bit_immediate in instructions is used to pass information to supervisor code. SWI #24_bit_immediate ;

examples-

multiple read LDM read from memory [r11] 6 words and save in r0-r3,r8,r9;r11 remains unchanged. r11 contains 3Ch
Mem addr Memory Mem Memory content addr content

LDM r11, [r0-3,r8,r9] ; r0<-01,r1<-FF,r2<-EE,r3<-DD,

r8<-CC,r9<-BB,r11 unchanged LDMIA r11!, [r0-3,r8,r9] ; r0<-01,r1<-FF,r2<-EE,r3<-DD, r8<-CC,r9<-BB,r11<-54 (changed) LDMIB r11!, [r0-3,r8,r9] ; r0<-FF,r1<-EE,r2<-DD,r3<-CC, r8<-BB,r9<-AA,r11<-54 (changed)

54 50 4C 48 44 40 3C 38

AA BB CC DD EE FF 01 02

r11 <-50h LDMDA r11!, [r0-3,r8,r9] ;r0<-01,r1<-FF,r2<-EE,r3<-DD,

r8<-CC,r9<-BB,r11<-38 (changed)

LDMDB r11!, [r0-3,r8,r9] ; r0<-02,r1<-01,r2<-FF,r3<-EE,

r8<-DD,r9<-CC,r11<-38 (changed) (use r15! in above example to perform PUSH and POP )

Addressing modesr11 contains 4C , r3 contains 08 , r5<-01, r6<-40h, r4<-A0000000h, carry flag=1 LDM r2, [r11,# -8] ; r2<-EE; r11 unchanged LDM r2, [r11,# 4] ; r2<-BB; r11 unchanged LDM r2, [r11,# -8]! ; r2<-EE , r11<-44(changed) LDM r2, [r11,# 4] !; r2<-BB , r11<-50(changed) LDM r2, [r11],# -8 ; r2<-CC , r11<-44(changed) LDM r2, [r11],# 4 ; r2<-CC , r11<-50(changed) LDM r2, [r11,-r3] ; r2<-EE; LDM r2, [r11,r3] ; r2<-AA; LDM r2, [r11,-r3]! ; r2<-EE , r11<-44(changed) LDM r2, [r11,r3] !; r2<-AA , r11<-54(changed) LDM r2, [r11],-r3 ; r2<-CC , r11<-44(changed) LDM r2, [r11],r3 ; r2<-CC , r11<-54(changed) LDM r2, [r11,-r5 LSL#3]! ; r2<-EE , r11<-44(changed) LDM r2, [r11,-r6 LSR#3]! ; r2<-EE , r11<-44(changed) LDM r2, [r11,r4 RRX] ; r2<-CC , r11 unchanged, carry flag=0 ADD r0 , r1, r2 ; r0= r1+r2 SUB r0,r3,r0 ; r0=r3 r0; to implement f = (g+h) (i+j); (using assembly variables) ADD t0, g,h ; to = g + h ADD t1, j , j ; t1 = i + j; SUB f , t0, t1 ; f = t0 t1 to implement g = h+ A[8] ; data at 8 offset from base A , 3rd element from base LDR r5 , [r3, #8] ; read indexed element , r3 base register representing A

ADD r1, r2, r5 ; if 8 is the index number (starting from 0) then LDR r5 , [r3, #32] ; read indexed element , r3 base register representing A to implement A[12] = h+ A[8] ; LDR r5 , [r3, #32] ; ADD r5, r2, r5; r2 represents h STR r5, [r3,#48] ; to implement
if (i==j) f= g+h ; else f = g h;

CMP r3 , r4 ; i in r3 , j in r4 BNE , LABEL_ELSE ADD r0 , r1, r2 B LABEL_EXIT LABEL_ELSE: SUB r0, r1,r2 ; LABEL_EXIT: with conditional statement CMP r3, r4 ; ADDEQ r0 , r1, r2 ; SUBNE r0, r1, r2 to implement loop : while( save[i] == k) i+ = 1; LOOP: ADD r12, r6, r3, LSL #2; r12 is save[i] LDR r0, [r12, #0] CMP r0, r5 BNE EXIT ; jump if save[i] != k ADD r3, r3, #1 ; B LOOP; repeat loop EXIT : to implement procedure
int leaf (int g, int g, int i, int j) {int f; f = (g+h) (i + h) return f; }

..... BL leaf .... leaf: SUB sp , sp, #12 ; three items to stack STR r6, [sp, #8]; save contents of regsiter STR r5 ,[sp,#4]; STR r4, [sp, #0]; ADD r5, r0, r1; g +h

ADD r6 , r2, r3 i +j SUB r4, r5, r6 ; f MOV r0, r4; return f LDR r4 , [sp , #0]; restore r4 LDR r5 , [sp , #4]; restore r5 LDR r6 , [sp , #8]; restore r6 ADD sp , sp, #12 ; adjust sp MOV pc, lr ; return to calling programme (may use LDS/STM for multiple register write/read) to implement nested procedure call- example of factorial calculation int fact( int n)
{if (n<1 ) return 1; else return (n * fact (n-1) );}

.... BL fact ... fact: SUB sp, sp, #8 STR lr , [sp, #8] ; save return address STR ro, [sp, #0] ; save argument n CMP r0 , #1 ; compare n to 1 BGE L1 ; if n> = 1 go to L1 MOV r0 , #1 ; n < 1 ADD sp, sp, #8 MOV pc , lr ; return to calling L1 : SUB r0 , r0, #1 ; n>1 , get n-1 BL fact ; call fact recursively with n-1 MOV r12, r0; save return value LDR r0 , [sp, #0] ; LDR lr, [sp, #4]; restore return address ADD sp , [sp, #8]; adjust stack MUL r0, r0, r12 ; return n * fact(n-1) MOV pc, lr ; return to calling programme

ref: http://infocenter.arm.com/help/index.jsp computer organization and design (ARM ed.) patterson,hennessy