A Low Power Reconfigurable SAR ADC

Paul R. Johnson, Mark C. Wasio, and Joel D. Wigton, University of Michigan, Ann Arbor
which is then compared to the input voltage via a clocked comparator. The output of the comparator is fed back into the FSM and tells it whether its initial guess was too high or too low. If VOUT is high, then the trial voltage was too low, so the MSB is set to 1, and the FSM continues on to the next bit. Otherwise, VOUT is low and this means the bit should be set to 0. Operation continues this way until all bits are realized. The circuit in the above figure is for illustration purposes only; the actual circuit implemented uses switched capacitors. This is for several reasons. First, the capacitors act not only as the DAC but also as the Sample and Hold components. Secondly, the resolution of the ADC will be limited partly by capacitor mismatch, which is quite good in modern CMOS processes. Lastly, it turns out that capacitors lend themselves very nicely to implementing the SAR function. II. CIRCUIT DESCRIPTION Our circuit is based largely on a method outlined by Gray and McCreary which uses a binary-weighted switched capacitor array [1]. Fig. 2 corresponds to the following method of operation. This operation is based on the sizing of the capacitors. Whenever a capacitor is switched on in this configuration, all of the capacitors to the right of it add up in parallel to the same value as the switched capacitor. Using this configuration, voltage division can be performed by storing charge on the top plate of the capacitor array.
AbstractThis paper presents the theory of operation and the design of a low power reconfigurable SAR ADC in 0.25m CMOS technology. Our device is programmable from 6-10 bits, and has a sample rate of at least 1MS/s at the highest resolution. Low power is emphasized in the design. With a VDD of 2.5V, the device consumes 1.25mW at 1MHz for a 10bit resolution. The SNDR ranges from 35.03dB to 50.25dB for 6- and 10-bit resolutions, respectively.

Index TermsSAR, Reconfigurable, Switched Capacitor Array, CMOS, Analog to Digital Converters. I. INTRODUCTION NALOG to Digital Converters (ADCs) are a popular component in nearly all electronic circuits that are used to convert one form of voltage information to another. They are most heavily needed in communications devices, such as cellular phones. One important requirement for such portable devices is low power consumption. One possible ADC configuration which typically yields low power is the Successive Approximation Register (SAR) converter, presented here. A SAR works by performing a binary search on a given input voltage. That is, it compares the sampled-and-held input to a trial voltage and based on the comparison, determines if it was correct or not. The output of the comparison is fed into a Finite State Machine (FSM), that determines which half of the current solution space the input is in, and selects the MSB accordingly. The solution space is now halved, and the comparator tries another trial voltage, this process repeats until the voltage is converted to the desired resolution. See Fig. 1.

Fig. 2: Basic Switched Capacitor DAC (5 bit illustration).

Fig. 1: Simple 8-bit SAR ADC.

As seen in Fig. 3, during sample mode switch SA is closed and the top plates are grounded. The bottom plates are then connected to Vin, which stores a total charge of -2CVin on the capacitors. Then in hold mode (see Fig. 4), switch SA is opened. This causes the top plates to float. All of the switches on the bottom plates are then switched to ground, which causes the voltage on the top plates to drop to Vin to conserve charge.

The SAR control logic tries an initial guess to begin with, 1

Latch. One last benefit that this comparator provides is the fact that the enable transistor completely shields the core from the input during regeneration phase. This will be discussed further in Section III.

Fig. 3: Sample Mode. Fig. 5: Block diagram of comparator

Fig. 4: Hold Mode.

The ADC then goes into redistribution mode. During this cycle, the bottom plate of the MSB is switched to VRef., causing the top plate of the capacitor array to rise to Vin+VRef/2. The comparator determines whether this value is above or below 0V. If the estimate was too high, the FSM will open the switch on the MSB. If the estimate was too low, the FSM will keep the MSB switch closed and move on to the MSB-1 switch. This process is repeated for all of the remaining bits. Using this method, the redistribution mode takes n clock cycles to resolve n bits. In our implementation, for practical reasons, during sample mode the top plate actually switches to VRef instead of ground. Likewise, the negative input to the comparator is set to VRef. This implementation shifts all of the voltage levels up by VRef so that the comparator never experiences a negative input. Throughout the design of the ADC, we made several choices to reduce the power consumption as much as possible. For example, we decided to use a single-ended implementation instead of a fully-differential one. This decreased the amount of circuitry needed and hence power decreased by about half. This is also the reason why we did not utilize any offset-cancellation techniques, as they would have increased power consumption. Furthermore, any offset from the comparator will only shift the DC response of our ADC, but will not introduce any non-linearity. We based our comparator core off of a design by Razavi and Wooley [2]. We chose this design partly because it only uses one clock signal during its operation. This reduces the load on the clock and also eliminates any problems with clock skew that is associated with a dualclock design. Furthermore, this design provides outputs that are strong enough to drive an SR Latch. This reduces the power consumption because some other comparator cores would require buffers to be able to drive the SR

One challenge of this design is the fact that at 10-bit resolution, the comparator must be able to correctly compare a voltage difference of only 1.25V/210=1.22mV. Designing a standalone core to achieve this amount of resolution over process and temperature corners would be extremely difficult. To relax this specification, we placed a pre-amplifier in front of the comparator core. With a gain of approximately 3.5, the preamp allows the comparator to resolve a difference of less than 800V. The preamp also reduces the effect of kickback from the comparator core. Another benefit of the preamp is that it reduces the effective offset of the comparator by a factor of APreamp. The outputs of the comparator core are then fed into an SR latch, which is composed of two cross-coupled NAND gates. This brings the outputs to CMOS logic levels that the FSM can accurately process. The overall block diagram of our comparator can be seen in Fig. 5. III. CIRCUIT ANALYSIS A. Comparator Operation Our comparator, like many, operates in two consecutive phases tracking and regeneration (or latching). The device is pictured in Fig. 6.

Fig. 6: Comparator core.

In the first phase, tracking, CLK is low. The enable transistor, M1, is off, disabling the bottom cross-coupled 2

NMOS pair. M2 is on, and current flows from VDD through M5 and M6 and on through the diff. pair. In this phase, the voltage across the output terminals is reset by M2, which acts as a resistor. A voltage difference across the diff. pair allows for a tiny amplified voltage across M2. This voltage difference is then amplified in the next stage. When CLK is raised, the core enters the regeneration phase. M1 is turned on, giving power to the cross-coupled NMOS pair. MDrain is also on, which shunts away current from the diff. pair. This effectively disables the input pair, meaning changes in the input voltage will not affect the output once in regeneration a desirable feature. Regeneration cross-coupled pairs M5/M6 and M3/M4 exponentially amplify the small voltage difference set up across M2 during the tracking phase, and ramp out those nodes to nearly the supply rails very quickly. Note here that CLK for the comparator is actually CLK_BAR for the FSM, but is called CLK here for clarity. The comparator still sees only one clock, and there are no clock timing issues. B. Comparator Device Sizing Device sizing for the comparator revolved around meeting several specifications. Firstly, we had a metastability goal of 1 in 108, which meant our comparator had to have a large amount of gain. We also had to operate at high speed, as for every sample clock cycle, the comparator must perform approximately n clock cycles (for n-bit resolution). In the end, metastability was a tighter goal, which meant we also met the speed requirements. The devices were also sized according to Pelgrom theory to reduce mismatch offset. On top of this, our goal was to minimize power consumption. The SR latch we ended up choosing because it used minimum power was just a simple cross-coupled pair of NAND gates. Through testing various input waveforms to the latch, we found that a deviation of VL 0.5V from VDD/2 would successfully latch the correct digital value. From the equation

where A0 is the preamp gain and gm is of the regeneration transistor, C is the capacitance seen at the output node, and t is the time during the regeneration phase. We calculated the device parameters for the 0.25m IBM CMOS process to get a gm of 3E-5 WL , and with a regeneration time of 25ns (conservative operation speed), and a load capacitance extracted from the simulator of 600fF, we get the sizing constraints:

W L W L

= 14 N = 42 P

For just the comparator core (excluding the preamp and SR latch), there are three major transistor pairs that contribute to Pelgrom offset. These are both regeneration pairs, and the diff. pair input. According to theory [3], the total noise is given by

AVT A A + VT + VT . WL WL WL

Then for a total core offset voltage of 10mV and assuming roughly equal size transistors, we obtain WL = 3, and this is our second sizing constraint needed to size the regeneration transistors and the core diff. pair transistors. Lastly, during the tracking phase, the core gain is about A = Gm R , with R being the resistance seen at the output node, through the bottom NMOS and the reset PMOS. We designed for a core gain of one during the tracking phase, giving us the final constraint necessary to size the input diff. pair transistors and the regeneration pair.

Regeneration (P): 10.5m/0.25m Regeneration (N): 7m/0.5m Diff. Pair: 4m/0.75m

PE =

2 VL , VR Acomp

As mentioned, a preamp gain of at least 3 enables us to resolve the necessary voltage differences of 1.22mV. Using resistor loads with practical values of 10K each, we have enough information to size the preamp transistors.

we calculate a required gain of Acomp = 4E7 for the maximum resolution. Hand calculations on the final comparator verified a gain of at least this much. Regenerative gain can be approximated roughly by

Preamp:

6m/0.5m

A = A0 e

gm t C

The actual sizes used give the comparator core an offset voltage of 10mV. This offset gets divided by the measured gain of the preamp stage when finding the overall offset. This results in:

 overall

100 10mV = = 6.56mV . + 6 0.5 3.2

One minor problem with this implementation is that the main capacitors are in series with the parasitic switch capacitance which results in a small ADC offset.

This offset is acceptable since it does not affect linearity but only shifts the codes one direction or another. Our simulated comparator worked below the minimum resolvable voltage, all the way down to 800V. C. Switched Capacitor DAC The DAC was implemented using a switched capacitor array. A standard binary weighted capacitor array was used with a unit capacitance of 20fF. For each bit slice, three NMOS switches were used to switch in ground, VIN, or VREF to the bottom plate of the capacitor. All series switches were eliminated in order to reduce the switch sizes and therefore capacitance in order to save power. One common switch was used connecting VREF to the top plate of the capacitors during sample mode. To minimize switch junction capacitance and therefore minimize ADC offset, the switch was sized as small as possible while still meeting the following settling time constraint:

Fig. 7: Bit slice 5 & 6 of DAC

D. FSM The FSM that controls all the switches in the DAC is based of the one proposed by Rossi [4]. The FSM supports three main operations: shift the initial guess right by one bit, load the new result from the comparator, and to hold the previous state for higher order bits that have already been determined. Some modifications had to be made in order to support reconfigurability and to support the sample and hold phases of operation. To support reconfigurability, the FSM had to initialize to the correct state depending on the desired amount of bits. For example, if the desired number of bits is 6 then the initialization state during the first redistribution cycle sets bit 5 high and all the other bits low (rather than always setting the MSB high). The FSM was custom made without Verilog using both standard cells and custom-made cells. The worst case delay of the FSM was about 1ns. IV. RESULTS SPICE simulation data was imported into MATLAB and the DNL, INL, and SNDR were determined. DNL measurements were taken using data under nominal operating conditions. To calculate the DC characteristics, we simulated a ramp input voltage in steps of LSB/4 and plotted the resulting digital codes. For the 6-bit case, we swept over the entire voltage range of the ADC. For the 10-bit case however, to save simulation time we simulated voltage ranges over the major code transitions such as over codes 252-260, 508-516, and 774-782. The results from both simulations were the same. The response of our ADC to this input using 6-bit resolution as compared to the response of an ideal ADC can be seen in Fig. 8.

RON _ BOTTOM = + RSWITCH _ TOP CTOTAL 2 and 6 = t CYCLE

Where RSWITCH =

n C OX

W (VGS VTh ) L

In order to minimize the impact of voltage dependant charge injection, the top plate switch is closed before any of the bottom plate switches. In this topology, input swing is mostly limited by the NMOS switches. During sample mode the switch connected to VIN can only pass VDD Vth, where Vth > Vth0 since VBS is not zero. Since we must also design for a low supply condition of VDD = 2.25V, we limited the input from 0 to 1.25V. In order to meet the requirements for reconfigurability, the switches that control the higher order reconfigurable bits (6:9) are encoded in a partially one-hot manner. When a higher order bit is needed, the switches are one-hot, so either ground, VREF, or VIN will be connected to the bottom plate of the capacitor. However, if a higher order bit isnt needed all the bottom plate switches are open, effectively disabling that bit. All the lower order bits have the normal one-hot encoding of a traditional switching capacitor based SAR ADC.

Digital Output to a Ramp Input 18 16 14 12

40

Simulated Ideal

Normalized 64-bin FFT, 10-bit resolution 80

60

Code

10
Power (dB)

8 6

20

4 2 0
-20

0.05

0.1

0.15 Vin

0.2

0.25

0.3

0.35

-40

10

15 Bin

20

25

30

35

Figure 8: ADC response to a ramp input Our ADC achieves excellent linearity. All of the codes are 1 LSB wide, so we conclude that our worst case |DNL| is always less than 0.25LSB. However, this plot does reveal that there is a 1 LSB offset. As mentioned previously, this is primarily due to the parasitic switch capacitances in series with the main DAC capacitors. Using these results, we cannot accurately measure INL because of the low resolution of the DNL measurement. However, because we know we have no missing codes, we can assume INL is low. The SNDR, SFDR, THD, and ENOB were calculated for the device by running a 64-bin FFT on the output codes for a sampled sine wave. The sine wave points were generated by MATLAB and then run in a parametric simulation. This was done both for the 6-bit and the 10-bit resolutions. For the code, please see the Appendix. Note that the ENOB is close to ideal for 6-bits but is more of a deviation for the 10-bit case. We believe the reason is twofold. First, the offset from the comparator and the capacitor array does not change with desired precision. Thus as we get into higher resolution sampling, decisions which would have been correct at low resolution might now be less-accurate. Secondly, the noise floor increases as we decrease the number of bins. Therefore, for a FFT of only 64 bins, we get a lot of additional noise. We believe if the simulations were run at higher bin numbers, the ENOB would more closely reflect the desired precision, however, they cannot be run for the 10-bit case due to impractical simulation times. We also calculated the figure of merit (FOM) of our ADC. As described by Stacy Ho of Analog Devices, Inc., the FOM can be found from the following equation:

Figure 9: FFT (10-bit resolution)

Normalized 64-bin FFT, 6-bit resolution 60

40

20

Power (dB)

-20

-40

-60

-80

10

15 Bin

20

25

30

35

Figure 10: FFT (6-bit resolution) For 10-bit resolution, the FOM is low at 2.36pJ/conversion step. However, at 6-bit resolution, the FOM is a bit higher at 12.88pJ/conversion step. This is because the 6-bit conversion can operate at a higher frequency than the 10-bit conversion; however, its bandwidth is set at 1MS/s. The 6bit conversion has been simulated at 5MS/s, which brings its FOM close to that of the 10-bit case. All of the performance characteristics of our ADC can be seen in Table 1. @ 1MS/s Power (mW) ENOB SNDR (dB) @ 46.875kHz SFDR (dB) @ 46.875kHz THD (dB) @ 46.875kHz |DNL| (LSB) FOM (pJ/step)
Table 1: DC Results.

FOM =

power 2 BW 2 ENOB
5

6 bit 1.19 5.53 35.03 41.04 -37.25 <0.25 12.88

10 bit 1.25 8.05 50.25 52.06 -55.95 <0.25 2.36

V. CONCLUSION

[2] We have successfully designed and simulated a reconfigurable SAR ADC. It operates correctly over process and temperature corners. However, DNL and SNDR were not collected at these corners because of excessive simulation time required. The performance of the ADC is respectable, but the DC characteristics could be more accurately measured if the granularity of the simulations was finer. For example, more FFT bins would improve the SNDR and ENOB of the 10-bit case. Future work includes offset reduction and power reduction. APPENDIX The ADC design and MATLAB code is located in:
/afs/engin.umich.edu/class/W06/eecs511/group3/SAR_ADC/ /afs/engin.umich.edu/class/W06/eecs511/group3/matlab/.

[3]

[4]

[5]

[6]

[7] REFERENCES [1] J. L. McCreary and P. R. Gray, All-MOS Charge Redistribution Analog-to-Digital Conversion TechniquesPart I, IEEE Journal of Solid-State [8]

Circuits, vol. SC-10, no. 6, pp. 371-379, 1975. B. Razavi and B.A. Wooley, A 12-b 5-MSample/s Two-Step CMOS A/D Converter, IEEE JSSC Vol. 27, No. 12, December 1992. M. J. M. Pelgrom, AAD-C. J. Duenmaijer, and A. P. G. Welbers, Matching Properties of MOS Transistors, IEEE Journal of Solid-State Circuits, vol. 24, no. 4, pp. 1433-1440, 1989. A. Rossi and G. Fucili, Nonredundant successive approximation register for A/D converters, Electronics letters, Vol.32, No.12, 6th June 1996. Thomas Kugelstadt, The operation of the SAR-ADC based on charge redistribution, Texas Instruments Analog Applications Journal, Feb. 2000, pp. 10-11. S. ODriscoll, T.H. Meng, Adaptive ADC design for neuro-prosthetic interfaces: base ADC cell, Proceedings of the 2005 European Conference on Circuit Theory and Design, vol. 1, pp. 301-304. G.M. Yin, F. Opt Eynde, and W. Sansen, A HighSpeed CMOS Comparator with 8-b Resolution, IEEE JSSC, vol. 27, no. 2, February 1992. B. Razavi and B.A. Wooley, Design Techniques for High-Speed, High-Resolution Comparators, IEEE JSSC, vol. 27, no. 12, December 1992.

Figure A1: ADC simulation test bench schematic