M11 8085 Programming

EE 201 : Digital Circuits and Microprocessors
Dr. Amit Sethi Room 303, EEE Dept. 2529, amitsethi
Objectives for this session

Introduce the 8085 Microprocessor
Introduction to 8085 programming model Introduction to 8085 instruction set
Computer: Basic definitions

Computer is a machine that sequentially and automatically carries out a sequence of arithmetic or logical operations given as instructions in form of a program, which can be changed readily, allowing the computer to solve more than one kind of problem Data and programs can be read from memories, storage or input devices Data can be written into memory, storage and output devices
All computers are based on the Turing Machine concept

In 1937, Alan Turing described this abstract idea of a computer Turing Machines consist of:
A tape of infinite length with symbols printed in cells A read-write head that can move along the tape to read and write symbols A state from a finite set stored inside the machine A finite set of instructions that translate the current state and the read symbol into an action which can be:
Change to another state Move to another place on the tape Write a symbol on the tape
Von Neumann Architecture
Based on TM concept Employs a single data bus to fetch both the instruction and the data Has a CPU with a control unit, an Arithmetic and Logic Unit (ALU) and registers to temporarily store data for the two to use Memory and I/O are addressed by a separate address bus
8085 has become a popular microprocessor for teaching

A simple 8-bit design, introduced by Intel in 1977 compatible with the more-famous Intel 8080 Relatively easy to study and operate:
Required less supporting hardware than 8080 "5" is for +5-volt (V) power supply rather than the +5V, -5V and +12V supplies the 8080 needed
Had a long life as a microcontroller (with added peripherals) Its actual name is 8085A, and it is NMOS device containing ~6,500 transistors and 40 pins
8085 Architecture
Another View
8085 Pin Diagram
8085 Programming Model

There are 6 general purpose registers, 8-bits wide each
16-bit 15 14 13 12 11 10 9 8-bit 7 A BC DE 6 5 4 B D PC SP 3 2 1 Accumulator 8 0 7 7 S 6 6 Z 5 5 4 4 C E L 3 3 2 2 P 1 1 0 0 0 AC 0 1 CY F
HL H B, C, D, E, H, and L PC SP They are used as needed. Can be used as 16-bit register pairs: BC, DE, HL
The accumulator is technically part of the ALU

It is 8-bits wide It is one of the inputs to every ALU operation The result of any operation is always stored in it It is known as Register A
Source: 7305862-Introduction-to-8085-Instructions.ppt by Dr. Bassel Soudan
The 8085 Programming Model

The ALU includes five flag flip-flops that are set or reset after an operation:
They are Z (zero), CY (carry), S (sign), P (parity) and AC (Auxiliary Carry) These flags are used when the microprocessor tests for data conditions These make up the Flags Register
16-bit 15 14 13 12 11 10 9 8-bit 7 A BC DE HL PC SP 6 5 4 B D H 3 2 1 Accumulator
8 0
7 7 S
6 6 Z
5 5
4 4 C E L
3 3
2 2 P
1 1
0 0
0 AC 0
1 CY F
PC SP
8-bit data bus
16-bit address bus
The 8085 Instructions

Since the 8085 is an 8-bit device it can have up to 28 (256) instructions However, the 8085 only uses 246 combinations that represent a total of 74 instructions
Most of the instructions have more than one format
These instructions can be grouped into five different groups:

Data Transfer Operations Arithmetic Operations Logic Operations Branch Operations Control Operations
Instruction and Data Formats

Each instruction can have two parts, e.g. ADD B:
The first part is the task or operation to be performed
This part is called the opcode (operation code) This part is essential for all instructions In 8085, all opcodes are 8-bits wide
The second part is the data to be operated on

Called the operand
Operand Types
There are different ways for specifying the operand:
There may not be an operand (implied operand)
CMA
The operand may be an 8-bit number (immediate data)

ADI SUB LDA 4FH B 4000H
The operand may be an internal register (register) The operand may be a 16-bit address (memory address)
Instruction Size
Depending on the operand type, the instruction may have different sizes. It will occupy a different number of memory bytes:
Instructions with implied operand occupy one byte Instruction that contains immediate data or a memory address occupy 2 or 3 bytes:
Instructions that include immediate data use two bytes:
One for the opcode and the other for the 8-bit data.
Instructions that include a memory address occupy three bytes:

One for the opcode, and the other two for the 16-bit address.
Instruction with Immediate Data

Operation: Load an 8-bit number into the accumulator
MVI A, 32
Operation: MVI A Operand: The number 32 Binary Code (Hex code):
0011 1110 0011 0010
3E 32
1st byte. 2nd byte.
Instruction with a Memory Address

Operation: go to address 2085
Instruction: JMP 2085
Opcode: JMP Operand: 2085 Binary code (Hex code):
1100 0011 1000 0101 0010 0000
C3 85 20
1st byte. 2nd byte 3rd byte
Note: Error in book on page 146.

Addressing Modes
The microprocessor has different ways of specifying the data for the instruction. These are called addressing modes: The 8085 has four addressing modes:
Implied Immediate Direct Indirect CMA MVI B, 45 LDA 4000 LDAX B
Load the accumulator with the contents of the memory location whose address is stored in the register pair BC).
A simple program
Objective: Add 3216 and 4816
Step English 1 Load 3216 into accumulator 2 Load 4816 into register B 3 Add B to A 4 Halt Mnemonic (Assembly) MVI A,32H MVI B,48H ADD B HLT Memory Address C000 C001 C002 C003 C004 C005 Hex 3E 32 06 48 80 76 Binary (Machine) 0011 1110 0011 0010 0000 0110 0100 1000 1000 0000 0111 0110
Notice that:
Possible instructions are defined by the programming model There is a 1-to-1 relation between an instruction in English, its mnemonic, Hex and binary. In the lab, you will get a handout for this
8085 learning resources

Books:
Microprocessor architecture, programming, and applications with the 8085, 5th Ed, by Gaonkar Digital and Microprocessor Fundamentals: Theory and Application, 4th Ed, by Kleitz
Tutorials:
http://en.wikipedia.org/wiki/Intel_8085 http://www.computer-solutions.co.uk/info/Embedded_tutorials/8085_tutorial.htm http://webphysics.davidson.edu/faculty/dmb/py310/8085.pdf
Instruction sets:
http://ce.sharif.ir/courses/86-87/1/ce126/resources/root/instructionset8085.pdf http://www.8085projects.info/page/8085-Instruction-set-list.aspx http://webphysics.davidson.edu/faculty/dmb/py310/emac_primer/8085.instructionset.full.pdf
Pin description
http://www.8085projects.info/pin_diagram.asp http://www.8085projects.info/Pindiagram-and-pin-description-of-8085.html http://www.8085projects.info/Pin-description-of-8085.html
More about DYNA kit

http://www.dynalogindia.com/index.php?page=shop.product_details&flypage=flypage.tpl&product_id=21 9&category_id=20&option=com_virtuemart&Itemid=20&vmcchk=1&Itemid=99 http://www.youtube.com/watch?v=xKxbNZz2Ufw
Simulators (simulates an 8085 kit):

http://8085simulator.codeplex.com/
Revision: 8085 Programming Model

Can address 64K 8-bit wide locations Has 6 general purpose registers, 8-bits wide each
B, C, D, E, H, and L They are used as needed. Can be used as 16-bit register pairs:
BC, DE, HL
16-bit 15 14 13 12 11 10 9 8-bit 7 A BC DE HL PC SP 6 5 4 B D H PC SP 3 2 1 Accumulator 8 0 7 7 S 6 6 Z 5 5 4 4 C E L 3 3 2 2 P 1 1 0 0 0 AC 0 1 CY F
The accumulator (or A) is part of the ALU

It is 8-bits wide It is one of the inputs to every ALU operation The result of any operation is always stored in it
8-bit data bus
16-bit address bus
Flag register contains the following bits:

Z (zero), CY (carry), S (sign), P (parity) and AC (Auxiliary Carry)
Program counter (also called the instruction pointer) indicates the memory address of the instruction to be executed Stack pointer points to top of the (subroutine) call stack
8085 Addressable Locations

Bi-directional 8-bit data bus 1 byte word Unidirectional 16 bit address bus (lower 8 multiplexed with data bus)
8085 is an 8-bit P
All calculations manipulate 8-bits of data Operations and data with more bits is broken down into 8-bits
64K locations (2 byte address)
It can handle 16-bit memory

8085 addressable locations
Memory has 64k addressable locations These locations are divided into:
User addressable (stored in a RAM) EEPROM I/O ports (connected to devices)
The 8085 Instructions

Since the 8085 is an 8-bit device it can have up to 28 (256) instructions However, the 8085 only uses 246 combinations that represent a total of 74 instructions
Most of the instructions have more than one format
These instructions can be grouped into five different groups:

Data Transfer Operations Arithmetic Operations Logic Operations Branch Operations Control Operations
Data Transfer Operations

These operations simply COPY the data from the source to the destination MOV, MVI, LDA, and STA They transfer:
Data between registers Data Byte to a register or memory location Data between a memory location and a register Data between an I/O Device and accumulator
The data in the source is not changed.

Arithmetic Operations
Addition (ADD, ADI):
Any 8-bit number. The contents of a register. The contents of a memory location.
Can be added to the contents of the accumulator and the result is stored in the accumulator.
Subtraction (SUB, SUI):

Any 8-bit number The contents of a register The contents of a memory location
Can be subtracted from the contents of the accumulator. The result is stored in the accumulator
Arithmetic Operations
Increment (INR) and Decrement (DCR):
The 8-bit contents of any memory location or any register can be directly incremented or decremented by 1 No need to disturb the contents of the accumulator
Logic Operations
These instructions perform logic operations on the contents of the accumulator
ANA, ANI, ORA, ORI, XRA and XRI
Source: Accumulator and
An 8-bit number The contents of a register The contents of a memory location
Destination: Accumulator
ANA ANI ORA ORI XRA XRI R/M # R/M # R/M # AND Accumulator With Reg/Mem AND Accumulator With an 8-bit number OR Accumulator With Reg/Mem OR Accumulator With an 8-bit number XOR Accumulator With Reg/Mem XOR Accumulator With an 8-bit number
Complement:
1s complement of the contents of the accumulator
CMA No operand
Branch Operations
Two types:
Unconditional branch
Go to a new location no matter what
Conditional branch
Go to a new location if the condition is true
Unconditional Branch
JMP CALL RET
Return from a subroutine
Address Address
Jump to the address specified (Go to)
Jump to the address specified but treat it as a subroutine
The addresses supplied to all branch operations must be 16-bits
Conditional Branch
Go to new location if a specified condition is met
JZ JNZ JC JNC JP JM Address (Jump on Zero) Address (Jump on NOT Zero) Address (Jump on Carry) Address (Jump on No Carry) Address (Jump on Plus) Address (Jump on Minus)
Go to address specified if the Zero flag is set Go to address specified if the Zero flag is not set Go to the address specified if the Carry flag is set Go to the address specified if the Carry flag is not set Go to the address specified if the Sign flag is not set Go to the address specified if the Sign flag is set
Machine Control
HLT
Stop executing the program
NOP
No operation Exactly as it says, do nothing Usually used for delay or to replace instructions during debugging
Program 1: Read a 16-bit number from memory, take its 1s complement and store it back in memory
Step English 1 Load number pointer of lower 8-bits to H 2 Move lower 8-bits to A 3 Complement A 4 Write A to C052 Mnemonic (Assembly) LXI H,C050 Memory Address C000 C001 C002 C003 C004 C005 C006 C007 C008 C009 C00A C00B C00C C00D C00E Hex 21 50 C0 7E 2F 32 52 C0 23 7F 2F 32 53 C0 76 Binary (Machine) 0010 0001 0101 0000 1100 0000 0111 1110 0010 1111 0011 0010 0101 0010 1100 0000 0010 0011 0111 1111 0010 1111 0011 0010 0101 0011 1100 0000 0111 0110
MOV A,M CMA STA C052
5 Increment H 6 Move upper 8-bits to A 7 Complement A 8 Write A to C053
INX H MOV A,M CMA STA C053
9 Halt
HLT
Program 2: Generate a Fibonacci sequence

//Fibonacci Series Generation //To run the Program simply load at // memory location C050=01,C051=01 START : MVI C,09 //Counter LXI H,C050 X: MOV A,M INX H MOV B,M INX H ADD B DAA MOV M,A DCX H DCR C JNZ X HLT //Memory Pointer

Understand the Memory Map Learn about interfacing with I/O devices
Note: The following slides have been adapted from works of others, primarily: 8085architecturememoryinterfacing1-100523023313-phpapp01.ppt by Pratik Amlani and 1204-ppi-8255-100523023201-phpapp02.ppt by Unknown
Memory Mapping
8085 has 16-bit Address Bus The complete address space is thus given by the range of addresses 0000H FFFFH The range of addresses allocated to a memory device is known as its memory map
Memory map: 64K memory device

Address lines required: 16 (A0 A15) Memory map: 0000H - FFFFH
Memory map: 32K memory device

Address lines required: 15 (A0 A14) Memory map: depends on how address line A15 is connected
U1 36 1 2 5 6 9 8 7 10 11 29 33 39 35 38 4 37 3 RST-IN X1 X2 SID TRAP RST 5.5 RST 6.5 RST 7.5 INTR INTA S0 S1 HOLD READY HLDA SOD CLKO RST-OT 8085 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ALE A8 A9 A10 A11 A12 A13 A14 A15 IO/M WR RD 12 13 14 15 16 17 18 19 30 21 22 23 24 25 26 27 28 1 34 2 32 74LS32 U5A 3 3 4 7 8 13 14 17 18 11
U2 D0 D1 D2 D3 D4 D5 D6 D7 G Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OC 2 5 6 9 12 15 16 19 1 10 9 8 7 6 5 4 3
U4 A0 A1 A2 A3 A4 A5 A6 A7 O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19
74LS373 25 24 21 23 2 26 27 20 22 1 A8 A9 A10 A11 A12 A13 A14 CE OE VPP 27C256
RAM
Memory device is selected only if IO/M = 0 & A15 = 0 You can do other things with A15=1, such as communicate with devices
31
So the memory map of the RAM in the previous slide is

A15 A14 A13 A12 0 0 0 0
A11 to A0 0. 0 0
= 0000H to
A15 A14 A13 A12
A11 to A0
1. 111
= 7FFFH
Interfacing I/O Devices

Using I/O devices data can be transferred between the microprocessor and the outside world. This can be done in groups of 8 bits using the entire data bus. This is called parallel I/O. The other method is serial I/O where one bit is transferred at a time using the SI and SO pins on the Microprocessor.
Interfacing I/O devices with 8085

I/O Interface I/O Devices
System Bus
8085
Memory Interface Memory Devices
8085 Communication with I/O devices

Involves the following three steps:
1.Identify the I/O device (with address) 2.Generate Timing & Control signals 3.Data transfer takes place
Techniques for I/O Interfacing

Memory-mapped I/O
Consider them like any other memory location.
They are assigned a 16-bit address within the address range of the 8085. The exchange of data with these devices follows the transfer of data with memory. The user uses the same instructions used for memory.
Peripheral-mapped (or I/O-mapped) I/O

Treat them separately from memory:
I/O devices are assigned a port number within the 8-bit address range of 00H to FFH. The user in this case would access these devices using the IN and OUT instructions only.
1.Identify the I/O device (with address)

1. Memory-mapped I/O (16-bit address) 2. Peripheral-mapped I/O (8-bit address)
2.Generate Timing & Control Signals

Memory-mapped I/O
Reading Input: IO/M = 0, RD = 0 Write to Output: IO/M = 0, WR = 0
Peripheral-mapped I/O
Reading Input: IO/M = 1, RD = 0 Write to Output: IO/M = 1, WR = 0
3. Data transfer takes place
Memory-mapped I/O
8085 uses its 16-bit address bus to identify a memory location Memory address space: 0000H to FFFFH 8085 needs to identify I/O devices also I/O devices can be interfaced using addresses from memory space 8085 treats such an I/O device as a memory location This is called Memory-mapped I/O Same commands are used to communicate with I/O devices that are memory mapped, e.g.
MOV STA
Memory-mapped I/O Instructions

I/O devices are identified by 16-bit addresses 8085 communicates with an I/O device as if it were one of the memory locations Memory related instructions are used For e.g. LDA, STA LDA 8000H
Loads A with data read from input device with 16-bit address 8000H
STA 8001H
Stores (Outputs) contents of A to output device with 16-bit address 8001H
Example Program
WAP to read a number from input port (port address 8000H) and display it on ASCII display connected to output port (port address 8001H) LDA 8000H;reads data value 03H(example) into ;accumulator, A = 03H MVI B, 30H;loads register B with 30H ADD B ;A = 33H, ASCII code for 3 STA 8001H;display 3 on ASCII display
Peripheral-mapped I/O
8085 has a separate 8-bit addressing scheme for I/O devices I/O address space: 00H to FFH This is called Peripheral-mapped I/O or I/Omapped I/O The chip used to interface with peripherals is 8255 also called PPI (programmable Peripheral Interface) This uses different commands, e.g.
IN OUT
Peripheral I/O Instructions

IN Instruction
Inputs data from input device into the accumulator It is a 2-byte instruction Format: IN 8-bit port address Example: IN 01H
Peripheral I/O Instructions

OUT Instruction
Outputs the contents of accumulator to an output device It is a 2-byte instruction Format: OUT 8-bit port address Example: OUT 02H
Example Program
WAP to read a number from input port (port address 01H) and display it on ASCII display connected to output port (port address 02H) IN 01H ;reads data value 03H (example) into ;accumulator, A = 03H from Port 01H MVI B, 30H;loads register B with 30H ADD B ;A = 33H, ASCII code for 3 OUT 02H ;display 3 on ASCII display Port 02H
Programmable Interface Devices

Used to interface a I/O device to the microprocessor
System Bus
8085
Programmable I/O Interface
I/O Devices
Can be programmed/configured to perform various I/O functions by writing software instructions
8255 A programmable parallel I/O device

Designed to be compatible with 8085 It consists of
Three I/O ports
Port A Port B Port C
Port C can be used as two 4-bit ports

PCu (Port C upper 4 bits) PCl (Port C lower 4 bits)
Example of I/O Interfacing using 8255

Port A System Bus
Port Cu
8-bit ADC
Temperature Sensor
8085
8255
Port Cl
LED Port B DISPLAY
Problem example
Let us say that we want to read an 8-bit input, take its complement, and display the result on 8 LEDs Here are the steps to follow:
1. Configure the 8255 ports 2. Write program to:
1. Read input from an 8255 port 2. Take its complement 3. Write output to an 8255 port, which is connected to LEDs
1. Configure 8255 I/O Ports

Port A
8-bit input
System Bus Port Cu Port Cl
8085
8255
LED Port B DISPLAY
To configure 8255, we need to know its Modes of Operation

Two primary modes of operation
1. Parallel I/O mode

Mode 0 (Simple Input/Output) Mode 1 (Input/Output with Handshake) Mode 2 (Bidirectional data transfer)
2. Bit Set/Reset Mode

This application uses
Parallel I/O mode - Mode 0
Control Word for 8255

8255 has a 8-bit Control word register 8255 ports can be configured for operation by writing a appropriate control word in it
for Parallel I/O
0 (No BSR) 0 0 90H 0 (dont care) 1 0 0 1
Application Programming
1. Configure 8255 I/O ports
1. MVI A, 90H 2. OUT CWR
Writing value 90H in Control Word Register of 8255 CWR represents the 8-bit port address of Control Word Register
Application Programming
2. Write program:
1. 2. 3. 4. 5. MVI A, 90H OUT CWR IN PORTA CMA OUT PORTB
3. Note that the output will have to be buffered, because the P output is fleeting (remains for a very short time)
8255 Chip selection & Port Addresses
A7 A6 A5 A4 A3 A2 A1 A0 A1 A0 CS
A = 80H B = 81H
8255
C = 82H
A1 A0 Port 0 0 1 1 0 1 0 1 A B C CWR
Programming with port addresses

OUT CWR IN PORTA OUT PORTB OUT 83H IN 80H OUT 81H

Understand how interrupts work
Classification of interrupts Processing of interrupts in 8085 Using interrupts for I/O interfacing
Definition and Classification

Interrupt is a process where an external device can get the attention of the microprocessor.
The process starts from the I/O device. The process is asynchronous.
Classification of Interrupts
Based on priority:
Maskable Interrupts (Can be delayed or Rejected) Non-Maskable Interrupts (Can not be delayed or Rejected)
Based on where the interrupt service routine is:

Vectored (the address of the service routine is hard-wired) Non-vectored (the address of the service routine needs to be supplied externally by the device)
Source: www.aust.edu/cse/moinul/interrupt.ppt by Moinul Hoque
What happens when an interrupt is generated?

An interrupt is a signal that requires microprocessors attention.
The Microprocessor may respond to it as soon as possible.
What happens when P is interrupted ?

When the Microprocessor receives an interrupt signal, it suspends the currently executing program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt (if not masked). Each interrupt will most probably have its own ISR.
Responding to Interrupts
Responding to an interrupt may be immediate or delayed depending on whether the interrupt is maskable or non-maskable and whether interrupts are being masked or not. There are two ways of redirecting the execution to the ISR depending on whether the interrupt is vectored or non-vectored.
Vectored: The address of the subroutine is already known to the Microprocessor Non Vectored: The device will have to supply the address of the subroutine to the Microprocessor
The 8085 Interrupts

When a device interrupts, it actually wants the P to give a service which is equivalent to asking the P to call a subroutine. This subroutine is called ISR (Interrupt Service Routine) The EI instruction is a one byte instruction and is used to Enable the non-maskable interrupts. The DI instruction is a one byte instruction and is used to Disable the non-maskable interrupts. The 8085 has a single Non-Maskable interrupt.
The non-maskable interrupt is not affected by the value of the Interrupt Enable flip flop.
The 8085 Interrupts

The 8085 has 5 interrupt inputs.
The INTR input.
The INTR input is the only non-vectored interrupt. INTR is maskable using the EI/DI instruction pair.
RST 5.5, RST 6.5, RST 7.5 are all automatically vectored.
RST 5.5, RST 6.5, and RST 7.5 are all maskable.
TRAP is the only non-maskable interrupt in the 8085

TRAP is also automatically vectored
8085 Interrupts
Interrupt name INTR RST 5.5 RST 6.5 RST 7.5 TRAP
Maskable Yes Yes Yes Yes No
Vectored No Yes Yes Yes Yes
TRAP RST7.5 RST6.5 RST 5.5 INTR INTA 8085
Interrupt Vectors and Vector Table

An interrupt vector is a pointer to where the ISR is stored in memory. All interrupts (vectored or otherwise) are mapped onto a memory area called the Interrupt Vector Table (IVT).
The IVT is usually located in memory page 00 (0000H - 00FFH). The purpose of the IVT is to hold the vectors that redirect the microprocessor to the right place when an interrupt arrives.
Example
Let , a device interrupt the Microprocessor using the RST 7.5 interrupt line.
Because the RST 7.5 interrupt is vectored, Microprocessor knows, in which memory location it has to go using a call instruction to get the ISR address. RST7.5 is known as Call 003CH to Microprocessor. Microprocessor goes to 003C location and will get a JMP instruction to the actual ISR address. The Microprocessor will then, jump to the ISR location
The 8085 Non-Vectored Interrupt Process

1. 2. 3. The interrupt process should be enabled using the EI instruction. The 8085 checks for an interrupt during the execution of every instruction. If INTR is high, P completes current instruction, disables the interrupt and sends INTA (Interrupt acknowledge) signal to the device that interrupted INTA allows the I/O device to send a RST instruction through data bus. Upon receiving the INTA signal, P saves the memory location of the next instruction on the stack and the program is transferred to call location (ISR Call) specified by the RST instruction.
4. 5.

6. Microprocessor Performs the ISR. 7. ISR must include the EI instruction to enable the further interrupt within the program. 8. RET instruction at the end of the ISR allows the P to retrieve the return address from the stack and the program is transferred back to where the program was interrupted.

The 8085 recognizes 8 RESTART instructions: RST0 - RST7.
each of these would send the execution to a predetermined hard-wired memory location:
Restart Instruction RST0 RST1 RST2 RST3 RST4 RST5 RST6 RST7
Equivalent to CALL 0000H CALL 0008H CALL 0010H CALL 0018H CALL 0020H CALL 0028H CALL 0030H CALL 0038H
Restart Sequence
The restart sequence is made up of three machine cycles
In the 1st machine cycle:
The microprocessor sends the INTA signal. While INTA is active the microprocessor reads the data lines expecting to receive, from the interrupting device, the opcode for the specific RST instruction.
In the 2nd and 3rd machine cycles:

the 16-bit address of the next instruction is saved on the stack. Then the microprocessor jumps to the address associated with the specified RST instruction.
Hardware Generation of RST Opcode

How does the external device produce the opcode for the appropriate RST instruction?
The opcode is simply a collection of bits. So, the device needs to set the bits of the data bus to the appropriate value in response to an INTA signal.
77

The following is an example of generating RST 5: RST 5s opcode is EF = D D 76543210 11101111

During the interrupt acknowledge machine cycle, (the 1st machine cycle of the RST operation):
The Microprocessor activates the INTA signal. This signal will enable the Tri-state buffers, which will place the value EFH on the data bus. Therefore, sending the Microprocessor the RST 5 instruction.
The RST 5 instruction is exactly equivalent to CALL 0028H

Issues in Implementing INTR Interrupts

How long must INTR remain high? The microprocessor checks the INTR line one clock cycle before the last T-state of each instruction. The INTR must remain active long enough to allow for the longest instruction. The longest instruction for the 8085 is the conditional CALL instruction which requires 18 T-states. Therefore, the INTR must remain active for 17.5 T-states. If f= 3MHZ then T=1/f and so, INTR must remain active for [ (1/3MHZ) * 17.5 5.8 micro seconds].

How long can the INTR remain high?
The INTR line must be deactivated before the EI is executed. Otherwise, the microprocessor will be interrupted again. Once the microprocessor starts to respond to an INTR interrupt, INTA becomes active (=0).
Therefore, INTR should be turned off as soon as the INTA signal is received.

Can the microprocessor be interrupted again before the completion of the ISR?
As soon as the 1st interrupt arrives, all maskable interrupts are disabled. They will only be enabled after the execution of the EI instruction.
Therefore, the answer is: only if we allow it to. If the EI instruction is placed early in the ISR, other interrupt may occur before the ISR is done.
Multiple Interrupts & Priorities

How do we allow multiple devices to interrupt using the INTR line?
The microprocessor can only respond to one signal on INTR at a time. Therefore, we must allow the signal from only one of the devices to reach the microprocessor. We must assign some priority to the different devices and allow their signals to reach the microprocessor according to the priority.
The Priority Encoder

The solution is to use a circuit called the priority encoder (e.g. 74148).
This circuit has 8 inputs and 3 outputs. The inputs are assigned increasing priorities according to the increasing index of the input.
Input 7 has highest priority and input 0 has the lowest.
The 3 outputs carry the index of the highest priority active input.
Multiple Interrupts & Priorities

Note that the opcodes for the different RST instructions follow a set pattern.
Bit D5, D4 and D3 of the opcodes change in a binary sequence from RST 7 down to RST 0. The other bits are always 1. This allows the code generated by the 74366 to be used directly to choose the appropriate RST instruction.
The one draw back to this scheme is that the only way to change the priority of the devices connected to the 74366 is to reconnect the hardware.
The 8085 Maskable/Vectored Interrupts

The 8085 has 3 Masked/Vectored interrupt inputs.
RST 5.5, RST 6.5, RST 7.5
They are all maskable. They are automatically vectored according to the following table:
Interrupt RST 5.5 RST 6.5 RST 7.5 Vector 002CH 0034H 003CH
The vectors for these interrupt fall in between the vectors for the RST instructions. Thats why they have names like RST 5.5 (RST 5 and a half).
Masking RST 5.5, RST 6.5 and RST 7.5

These three interrupts are masked at two levels:
Through the Interrupt Enable flip flop and the EI/DI instructions.
The Interrupt Enable flip flop controls the whole maskable interrupt process.
Through individual mask flip flops that control the availability of the individual interrupts.
These flip flops control the interrupts individually.
The 8085 Maskable/Vectored Interrupt Process

1. The interrupt process should be enabled using the EI instruction. 2. The 8085 checks for an interrupt during the execution of every instruction. 3. If there is an interrupt, and if the interrupt is enabled using the interrupt mask, the microprocessor will complete the executing instruction, and reset the interrupt flip flop. 4. The microprocessor then executes a call instruction that sends the execution to the appropriate location in the interrupt vector table.
The 8085 Maskable/Vectored Interrupt Process

5. When the microprocessor executes the call instruction, it saves the address of the next instruction on the stack. 6. The microprocessor jumps to the specific service routine. 7. The service routine must include the instruction EI to re-enable the interrupt process. 8. At the end of the service routine, the RET instruction returns the execution to where the program was interrupted.
Manipulating the Masks

The Interrupt Enable flip flop is manipulated using the EI/DI instructions. The individual masks for RST 5.5, RST 6.5 and RST 7.5 are manipulated using the SIM instruction.
This instruction takes the bit pattern in the Accumulator and applies it to the interrupt mask enabling and disabling the specific interrupts.
How SIM Interprets the Accumulator

7 6 5 4 3 2 1 0
SDO SDE XXX R7.5 MSE M7.5 M6.5 M5.5
Serial Data Out
RST5.5 Mask RST6.5 Mask RST7.5 Mask
0 - Available 1 - Masked
Enable Serial Data 0 - Ignore bit 7 1 - Send bit 7 to SOD pin
Mask Set Enable 0 - Ignore bits 0-2 1 - Set the masks according to bits 0-2
Not Used
Force RST7.5 Flip Flop to reset
SIM and the Interrupt Mask

Bit 0 is the mask for RST 5.5, bit 1 is the mask for RST 6.5 and bit 2 is the mask for RST 7.5. If the mask bit is 0, the interrupt is available. If the mask bit is 1, the interrupt is masked. Bit 3 (Mask Set Enable - MSE) is an enable for setting the mask. If it is set to 0 the mask is ignored and the old settings remain. If it is set to 1, the new setting are applied. The SIM instruction is used for multiple purposes and not only for setting interrupt masks. It is also used to control functionality such as Serial Data Transmission. Therefore, bit 3 is necessary to tell the microprocessor whether or not the interrupt masks should be modified
SIM and the Interrupt Mask

The RST 7.5 interrupt is the only 8085 interrupt that has memory.
If a signal on RST7.5 arrives while it is masked, a flip flop will remember the signal. When RST7.5 is unmasked, the microprocessor will be interrupted even if the device has removed the interrupt signal. This flip flop will be automatically reset when the microprocessor responds to an RST 7.5 interrupt.
Bit 4 of the accumulator in the SIM instruction allows explicitly resetting the RST 7.5 memory even if the microprocessor did not respond to it. Bit 5 is not used by the SIM instruction
Maskable Interrupts and vector locations

RST7.5 Memory RST 7.5
M 7.5
RST 6.5
M 6.5
RST 5.5
M 5.5
INTR
Interrupt Enable Flip Flop
Triggering Levels
RST 7.5 is positive edge sensitive.
When a positive edge appears on the RST7.5 line, a logic 1 is stored in the flip-flop as a pending interrupt. Since the value has been stored in the flip flop, the line does not have to be high when the microprocessor checks for the interrupt to be recognized. The line must go to zero and back to one before a new interrupt is recognized.
RST 6.5 and RST 5.5 are level sensitive.

The interrupting signal must remain present until the microprocessor checks for interrupts.
Using the SIM Instruction to Modify the Interrupt Masks

Example: Set the interrupt masks so that RST5.5 is enabled, RST6.5 is masked, and RST7.5 is enabled.
First, determine the contents of the accumulator
- Enable 5.5 bit 0 = 0 - Disable 6.5 bit 1 = 1 - Enable 7.5 bit 2 = 0 - Allow setting the masks bit 3 = 1 - Dont reset the flip flop bit 4 = 0 - Bit 5 is not used - Dont use serial data - Serial data is ignored
bit 5 = 0 bit 6 = 0 bit 7 = 0
Contents of accumulator are: 0AH
EI MVI A, 0A SIM
; Enable interrupts including INTR ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5 ; Apply the settings RST masks
SDO SDE XXX R7.5 MSE M7.5 M6.5 M5.5 0 0 0 0 1 0 1 0
Determining the Current Mask Settings

RIM instruction: Read Interrupt Mask
Load the accumulator with an 8-bit pattern showing the status of each interrupt pin and mask.
RST 7.5
7 6 5 4 3 2 1 0
RST7.5 Memory
M 7.5
SDI P7.5 P6.5 P5.5 IE M7.5 M6.5 M5.5
RST 6.5
M 6.5
RST 5.5
M 5.5 Interrupt Enable Flip Flop Source: www.aust.edu/cse/moinul/interrupt.ppt by Moinul Hoque
How RIM sets the Accumulators different bits
5 4
SDI P7.5 P6.5 P5.5 IE M7.5 M6.5 M5.5
Serial Data In RST5.5 Interrupt Pending RST6.5 Interrupt Pending RST7.5 Interrupt Pending
RST5.5 Mask RST6.5 Mask RST7.5 Mask
0 - Available 1 - Masked
Interrupt Enable Value of the Interrupt Enable Flip Flop
The RIM Instruction and the Masks

Bits 0-2 show the current setting of the mask for each of RST 7.5, RST 6.5 and RST 5.5
They return the contents of the three mask flip flops. They can be used by a program to read the mask settings in order to modify only the right mask.
Bit 3 shows whether the maskable interrupt process is enabled or not.

It returns the contents of the Interrupt Enable Flip Flop. It can be used by a program to determine whether or not interrupts are enabled.
The RIM Instruction and the Masks

Bits 4-6 show whether or not there are pending interrupts on RST 7.5, RST 6.5, and RST 5.5
Bits 4 and 5 return the current value of the RST5.5 and RST6.5 pins. Bit 6 returns the current value of the RST7.5 memory flip flop.
Bit 7 is used for Serial Data Input.

The RIM instruction reads the value of the SID pin on the microprocessor and returns it in this bit.
Pending Interrupts
Since the 8085 has five interrupt lines, interrupts may occur during an ISR and remain pending.
Using the RIM instruction, it is possible to can read the status of the interrupt lines and find if there are any pending interrupts.
TRAP
TRAP is the only non-maskable interrupt.
It does not need to be enabled because it cannot be disabled.
It has the highest priority amongst interrupts. It is edge and level sensitive.
It needs to go high and stay high to be recognized. Once it is recognized, it wont be recognized again until it goes low, then high again.
TRAP is usually used for power failure and emergency shutoff.

The 8085 Interrupts

Interrupt Name INTR RST 5.5 / RST 6.5 RST 7.5 Maskable Masking Method DI / EI DI / EI SIM DI / EI SIM None Vectored Memory Triggering Method Level Sensitive Level Sensitive Edge Sensitive Level & Edge Sensitive
Yes Yes Yes
No Yes Yes
No No Yes
TRAP
No
Yes
No
Stacks and Subroutines
The Stack
The stack is an area of memory identified by the programmer for temporary storage of information. The stack is a LIFO structure.
Last In First Out.
The stack normally grows backwards into memory.

In other words, the programmer defines the bottom of the stack and the stack grows up into reducing address range.
Source: Stack_and_Subroutine.pdf by Moinul Hoque
The Stack
Given that the stack grows backwards into memory, it is customary to place the bottom of the stack at the end of memory to keep it as far away from user programs as possible. In the 8085, the stack is defined by setting the SP (Stack Pointer) register.
LXI SP, FFFFH
This sets the Stack Pointer to location FFFFH (end of memory for the 8085). The Size of the stack is limited only by the available memory.
Saving and retrieving information on the Stack

Information is saved on the stack by PUSHing it on. It is retrieved from the stack by POPping it off. The 8085 provides two instructions:
PUSH for storing information on the stack POP for retrieving it back.
Both PUSH and POP work with register pairs ONLY

The PUSH Instruction

PUSH B (1 Byte Instruction)
Decrement SP Copy the contents of register B to the memory location pointed to by SP Decrement SP Copy the contents of register C to the memory location pointed to by SP
The POP Instruction

POP D (1 Byte Instruction)
Copy the contents of the memory location pointed to by the SP to register E Increment SP Copy the contents of the memory location pointed to by the SP to register D Increment SP
Operation of the Stack

During pushing, the stack operates in a decrement then store style.
The stack pointer is decremented first, then the information is placed on the stack.
During POPping, the stack operates in a use then increment style.

The information is retrieved from the top of the stack and then the pointer is incremented.
The SP pointer always points to the top of the stack
LIFO
The order of PUSHs and POPs must be opposite of each other in order to retrieve information back into its original location. PUSH B PUSH D ... POP D POP B Reversing the order of the POP instructions will result in the exchange of the contents of BC and DE
The PSW Register Pair

The 8085 recognizes one additional register pair called the PSW (Program Status Word).
This register pair is made up of the Accumulator and the Flags registers.
It is possible to push the PSW onto the stack, do whatever operations are needed, then POP it off of the stack.
The result is that the contents of the Accumulator and the status of the Flags are returned to what they were before the operations were executed
Push & Pop PSW Register Pair

PUSH PSW (1 Byte Instruction)
Decrement SP Copy the contents of register A to the memory location pointed to by SP Decrement SP Copy the contents of Flag register to the memory location pointed to by S
POP PSW (1 Byte Instruction)

Copy the contents of the memory location pointed to by the SP to Flag register Increment SP Copy the contents of the memory location pointed to by the SP to register A Increment S
Subroutines
A subroutine is a group of instructions that will be used repeatedly in different locations of the program.
Rather than repeat the same instructions several times, they can be grouped into a subroutine that is called from the different locations.
In Assembly language, a subroutine can exist anywhere in the code.

However, it is customary to place subroutines separately from the main program.
Subroutines
The 8085 has two instructions for dealing with subroutines.
The CALL instruction is used to redirect program execution to the subroutine. The RET instruction is used to return the execution to the calling routine.
CALL Instruction
CALL 4000H (3 byte instruction)
When CALL instruction is fetched, the MP knows that the next two Memory location contains 16bit subroutine address in the memory.
CALL Instruction
MP Reads the subroutine address from the next two memory location and stores the higher order 8bit of the address in the W register and stores the lower order 8bit of the address in the Z register Push the address of the instruction immediately following the CALL onto the stack [Return address] Loads the program counter with the 16-bit address supplied with the CALL instruction from WZ register
RET Instruction
RET (1 byte instruction)
Retrieve the return address from the top of the stack Load the program counter with the return address
Things to be considered in Subroutine

The CALL instruction places the return address at the two memory locations immediately before where the Stack Pointer is pointing.
You must set the SP correctly BEFORE using the CALL instruction.
The RET instruction takes the contents of the two memory locations at the top of the stack and uses these as the return address.
Do not modify the stack pointer in a subroutine. You will loose the return address.
Things to be considered in Subroutine

Number of PUSH and POP instruction used in the subroutine must be same, otherwise, RET instruction will pick wrong value of the return address from the stack and program will fail.
Conditional CALL and RTE Instructions

The 8085 supports conditional CALL and conditional RTE instructions.
The same conditions used with conditional JUMP instructions can be used. CC, call subroutine if Carry flag is set. CNC, call subroutine if Carry flag is not set RC, return from subroutine if Carry flag is set RNC, return from subroutine if Carry flag is not set Etc.
A Proper Subroutine
According to Software Engineering practices, a proper subroutine:
Is only entered with a CALL and exited with an RET Has a single entry point
Do not use a CALL statement to jump into different points of the same subroutine.
Has a single exit point
There should be one return statement from any subroutine.
Program 4: Use a subroutines for bubble sorting 5 numbers

//Implementing bubble sort START: MVI D,05 //Outer loop W: LXI H,C020 MVI C,05 //Inner loop X: CALL COMP_SWAP DCR C JNZ X DCR D JNZ W HLT COMP_SWAP: MOV A,M INX H MOV B,M CMP B CP STORE_BACK RET
STORE_BACK: MOV M,A DCX H MOV M,B INX H RET
Appendix: Programming the 8255
The interfacing of output devices

Output devices are usually slow. Also, the output is usually expected to continue appearing on the output device for a long period of time. Given that the data will only be present on the data lines for a very short period (microseconds), it has to be latched externally.
To do this the external latch should be enabled when the ports address is present on the address bus, the IO/M signal is set high and WR is set low.
The resulting signal would be active when the output device is being accessed by the microprocessor. Decoding the address bus (for memory-mapped devices) follows the same techniques discussed in interfacing memory.
Interfacing of input devices

The basic concepts are similar to interfacing of output devices.
The address lines are decoded to generate a signal that is active when the particular port is being accessed. An IORD signal is generated by combining the IO/M and the RD signals from the microprocessor.
A tri-state buffer is used to connect the input device to the data bus. The control (Enable) for these buffers is connected to the result of combining the address signal and the signal IORD.
Examples of Interfacing I/O Devices

To illustrate the techniques of interfacing I/O devices we will design the circuits needed to interface 8 LEDs to display the contents of the accumulator as well as 8 switches to set the contents of the accumulator.
Interfacing the LEDs

Lets first design the external circuit.
The data on the data bus from the microprocessor stays for an extremely short amount of time. So, in order to keep it long enough for displaying, we will need an external latch.
We will use an 8-bit latch to hold the data we need to connect the 8 LED to the latches outputs.
However, the latch will not be able to source enough current. So, we will use the inverted outputs and make it sink the current instead.
When should the latch be enabled?

It needs to be enabled when the data is on the data bus.
That happens when the ALE signal is low. However, we only want to display the data that is being sent to the I/O, we dont want to display the data being saved in memory. So, the latch needs to be enabled only during I/O operations. That happens when IO/M=1 Finally we only want to display data intended for our port. We must decide on a port number.
Lets say FFH.
Now, we can design the control circuit.
Interfacing the LEDs (Control Circuit)

The Latch will be enabled when:
WR = 0 IO/M = 1 The address on A8 A15 = FFH
A15
A8 IO/M WR
Latch Enable
Interfacing the LEDs (Latch & LEDs)
Interfacing the LEDs (the program)

When a bit on the AD bus is 1, the corresponding Q will be zero and the LED will have 5 volts on the anode and 0 on the cathode. Therefore, it will be on. Finally, to write the program:
MVI A, Data OUT FF HLT ;load the data to be displayed ;send the data to output port FF ;End
Interfacing the switches

The binary value from the switches will have to be carried by the data bus. However, the data bus is a shared bus. So, the switches must be connected to the data bus using Tri-state buffers. Similar to the latch, the buffers must be enabled only on I/O Read operation from this I/O port. Lets choose I/O port 0FH for the switches. So, the buffers must be enabled when:
RD = 0 IO/M = 1 A8-A15 = 0FH
Source: http://www.kulo.in/micro/8085ss/Chapter%25204.ppt
Interfacing the Switches (Control Circuit)
Buffer Enable A8 IO/M RD
Interfacing the Switches (Latch & Switches)
Interfacing the Switches (the program)

Finally, the program:
IN 0FH HLT ;input data from port 0F into A ;END
If we combine both circuits, then we can write the following program:

INPUT: IN 0FH OUT FFH JMP INPUT

M11 8085 Programming

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M11 8085 Programming

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EE 201 : Digital Circuits and Microprocessors

Dr. Amit Sethi Room 303, EEE Dept. 2529, amitsethi

Objectives for this session

Computer: Basic definitions

All computers are based on the Turing Machine concept

Von Neumann Architecture

8085 has become a popular microprocessor for teaching

8085 Pin Diagram

8085 Programming Model

The accumulator is technically part of the ALU

Source: 7305862-Introduction-to-8085-Instructions.ppt by Dr. Bassel Soudan

The 8085 Programming Model

16-bit 15 14 13 12 11 10 9 8-bit 7 A BC DE HL PC SP 6 5 4 B D H 3 2 1 Accumulator

8-bit data bus

16-bit address bus

Source: 7305862-Introduction-to-8085-Instructions.ppt by Dr. Bassel Soudan

The 8085 Instructions

These instructions can be grouped into five different groups:

Source: 7305862-Introduction-to-8085-Instructions.ppt by Dr. Bassel Soudan

Instruction and Data Formats

The second part is the data to be operated on

The operand may be an 8-bit number (immediate data)

Source: 7305862-Introduction-to-8085-Instructions.ppt by Dr. Bassel Soudan

Instructions that include a memory address occupy three bytes:

Source: 7305862-Introduction-to-8085-Instructions.ppt by Dr. Bassel Soudan

Instruction with Immediate Data

0011 1110 0011 0010

1st byte. 2nd byte.

Source: 7305862-Introduction-to-8085-Instructions.ppt by Dr. Bassel Soudan

Instruction with a Memory Address

1100 0011 1000 0101 0010 0000

1st byte. 2nd byte 3rd byte

Note: Error in book on page 146.

8085 learning resources

More about DYNA kit

Simulators (simulates an 8085 kit):

Revision: 8085 Programming Model

The accumulator (or A) is part of the ALU

8-bit data bus

16-bit address bus

Flag register contains the following bits:

Source: 7305862-Introduction-to-8085-Instructions.ppt by Dr. Bassel Soudan

8085 Addressable Locations

64K locations (2 byte address)

It can handle 16-bit memory

The 8085 Instructions

These instructions can be grouped into five different groups:

Source: 7305862-Introduction-to-8085-Instructions.ppt by Dr. Bassel Soudan

Data Transfer Operations

The data in the source is not changed.

Subtraction (SUB, SUI):

Source: 7305862-Introduction-to-8085-Instructions.ppt by Dr. Bassel Soudan

Source: 7305862-Introduction-to-8085-Instructions.ppt by Dr. Bassel Soudan

Source: 7305862-Introduction-to-8085-Instructions.ppt by Dr. Bassel Soudan

Jump to the address specified (Go to)

Jump to the address specified but treat it as a subroutine

The addresses supplied to all branch operations must be 16-bits

Source: 7305862-Introduction-to-8085-Instructions.ppt by Dr. Bassel Soudan

Source: 7305862-Introduction-to-8085-Instructions.ppt by Dr. Bassel Soudan

Source: 7305862-Introduction-to-8085-Instructions.ppt by Dr. Bassel Soudan

MOV A,M CMA STA C052

5 Increment H 6 Move upper 8-bits to A 7 Complement A 8 Write A to C053

INX H MOV A,M CMA STA C053