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Switched-Mode Power Supply Design Manual

Switched-Mode Power Supply Design Manual

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Table of Contents

Table of Contents
Chapter 1 Introduction and the State Averaging Process .................................... 1-1
SMPS Design ........................................................................................................... Document Organization............................................................................................ Examples........................................................................................................................... Windows ........................................................................................................................ UNIX .............................................................................................................................. Hints and Tips .......................................................................................................... State Averaging ....................................................................................................... Features and Limitations of the Models ............................................................................ Converter Topologies ........................................................................................................

1-1 1-1
1-2 1-2 1-2

1-2 1-3
1-5 1-6

Chapter 2 Boost Converter ................................................................................................. 2-1


Setting Parameters............................................................................................................ Operation of the Boost Topology-Block............................................................................. Time-Domain Simulation ............................................................................................... Frequency-Domain Simulation ...................................................................................... 2-2 2-3 2-3 2-7

Chapter 3 Buck-Boost Converter ..................................................................................... 3-1


Setting Parameters............................................................................................................ Operation of the Buck-Boost Topology-Block ................................................................... Time-Domain Simulation ............................................................................................... Frequency-Domain Simulation ..................................................................................... 3-2 3-3 3-3 3-7

Chapter 4 Buck Converter ................................................................................................... 4-1


Setting Parameters............................................................................................................ 4-2 Operation of the Buck Topology-Block.............................................................................. 4-2 Time-Domain Simulation ............................................................................................... 4-3

Chapter 5 Flyback Converter ............................................................................................. 5-1


Setting Parameters........................................................................................................... Operation of the Flyback Topology-Block ......................................................................... Time-Domain Simulation ............................................................................................... Frequency-Domain Simulation ..................................................................................... 5-4 5-4 5-5 5-8

Table of Contents TOC1

Table of Contents

Chapter 6 Forward Converter ............................................................................................ 6-1


Setting Parameters............................................................................................................ Operation of the Forward Topology-Block......................................................................... Time-Domain Simulation .............................................................................................. Frequency-Domain Simulation ...................................................................................... 6-2 6-2 6-3 6-5

Chapter 7 C uk Converter.................................................................................................. 7-1


Parameters....................................................................................................................... Operation of the C uk Topology-Block ............................................................................. Time-Domain Simulation ............................................................................................... Frequency-Domain Simulation ..................................................................................... 7-3 7-3 7-4 7-7

Chapter 8 Current-Mode Control ...................................................................................... 8-1


Cycle-By-Cycle Current-Mode Control .............................................................................. 8-1 Voltage-Mode Control with In-Cycle Current Limit ............................................................ 8-2 Slope Compensation ......................................................................................................... 8-3

Chapter 9 Multiple-Output Forward Converter ........................................................... 9-1


Setting Parameters............................................................................................................ Operation of the Multiple-Output Forward Topology-Block ............................................... Time-Domain Simulation ................................................................................................... Frequency-Domain Simulation .......................................................................................... 9-2 9-4 9-4 9-6

Chapter 10 Multiple-Output Flyback Converter .......................................................... 10-1


Setting Parameters......................................................................................................... 10-3 Operation of the Multiple-Output Flyback Model ............................................................. 10-4 Time-Domain Simulation ................................................................................................ 10-4 Frequency-Domain Simulation ...................................................................................... 10-11

Chapter 11 Current-Mode Boost Converter ................................................................. 11-1


Setting Parameters.......................................................................................................... 11-3 Operation of the Current-Mode Boost Topology Block.................................................... 11-3 Time-Domain Simulation ................................................................................................. 11-5 Frequency-Domain Simulation ...................................................................................... 11-10

TOC2 VeriBest Switched-Mode Power Supply Design Manual

Table of Contents

Chapter 12 Frequency-Domain Analysis ....................................................................... 12-1


Simulation Method for Frequency Analysis ..................................................................... Performing Frequency Analysis ...................................................................................... Breaking the Feedback Loop....................................................................................... Determination of Frequency-Source Bias Voltage .......................................................... Frequency-Domain Simulation ........................................................................................ Simulate VBA .................................................................................................................. 12-1 12-2 12-2 12-3 12-5 12-5

Chapter 13 IC Model Description ..................................................................................... 13-1


Pulse Width Modulator Control Integrated Circuits ......................................................... 13-1

Chapter 14 SG3524 Model .................................................................................................... 14-1


Setting Parameters.......................................................................................................... 14-2

Chapter 15 SG3525 and SG3527 Models ....................................................................... 15-1


Setting Parameters.......................................................................................................... 15-2

Chapter 16 TL494 Model ....................................................................................................... 16-1


Setting Parameters.......................................................................................................... 16-2

Chapter 17 Ancillary Devices ............................................................................................. 17-1


Load Model...................................................................................................................... Power Supply Failure Model ........................................................................................... Setting Parameters...................................................................................................... Generic Opto-Coupler Models......................................................................................... Setting Parameters...................................................................................................... Generic Operational Amplifier Models............................................................................. Setting Parameters...................................................................................................... Generic Isolation Buffer Model ........................................................................................ Setting Parameters...................................................................................................... 17-1 17-2 17-2 17-2 17-3 17-3 17-3 17-4 17-4

Table of Contents TOC3

Table of Contents

Chapter 18 UC3840 Model.................................................................................................... 18-1


Slope Compensation ....................................................................................................... 18-4

Chapter 19 UC3842 and UC3844 Models ....................................................................... 19-1 Chapter 20 UC3846 Model.................................................................................................... 20-1
Setting Parameters......................................................................................................... 20-2

Chapter 21 AC Supply Failure Model .............................................................................. 21-1


Setting Parameters.......................................................................................................... 21-1 Operation of the Power Supply Failure Block.................................................................. 21-2

Index ...................................................................................................................... IX-1

TOC4 VeriBest Switched-Mode Power Supply Design Manual

Chapter 1 Introduction and the State Averaging Process


SMPS Design
Switched-Mode Power Supply (SMPS) design is a slow iterative process involving cycles of calculation and experimentation on real hardware. Simulations of SMPS circuits by conventional methods is slow because many switching operations need processing. State-averaging provides all major SMPS characteristics quickly without simulating individual switching cycles, but retaining the transfer characteristics of the circuit. State averaged models of power supply configurations form the basis of this product. The software described in this manual alleviates the problem of excessive simulation time and allows simulation of switching power supplies in both time- and frequency-domains. Various standard configurations of power supplies have been modeled, each of which can be tailored to a designers required application. This software has been designed to run exclusively with the VeriBest Analog Simulation Engine (VBASE), and the VeriBest DIABLO Behavioral Language Option. Detailed information about DIABLO can be found in the VeriBest Analog Simulation Engine Reference Manual. A technique known as state-averaging was used to produce the models for this design aid. The stateaveraging technique will be explained in detail in this chapter, but briefly, state-averaging allows the designer to examine the overall transfer-characteristic of the supply without performing any switching operations. This leads to fast simulation runs and allows examination of the usual test criteria such as step-load-changes, overshoot, settling time and gain- and phase-margin.

Document Organization
The Users Guide is divided into 21 chapters. Chapter 1 describes the state-averaging process, its advantages and limitations, and hints and tips to aid the designer. Chapters 2 to 7 describe the different converter topologies. These chapters are quite detailed and, in some cases, show comparisons between real and simulated power supplies. Chapter 8 describes how current-mode control has been implemented and how the models are used. Chapters 9, 10, and 11 describe the following converter models: multiple-output forward, multipleoutput flyback, and current-mode boost. Chapter 12 explains frequency-domain simulation techniques. Chapter 13 describes the use of the controller IC models.

Introduction and the State Averaging Process 11

Introduction and the State Averaging Process Chapters 14 to 16 describe the switched-mode controller ICs that have been state-averaged for use with the converters. Chapter 17 explains the use of ancillary components such as load-banks and the following ancillary devices: opto-coupler, op-amp, and buffer models Chapters 18, 19, and 20 describe the UC3840, UC3842, UC3844, and UC3846 regulating pulsewidth modulators. Chapter 21 documents an AC supply failure model.

Examples
The examples described throughout the manual in Chapters 2 to 7 are loaded in the demonstration directory. The pathname to this directory is

Windows
<drive>\veribest\vba\examples\vba\smps\<convertor type>

UNIX
/<home>/vbest14/vba/examples/vba/smps/<convertor type> Details on how to run these examples are outlined in the relevant chapters.

Hints and Tips


This manual and the software models that accompany it are designed as a tool to help engineers design switched-mode power supplies. The purpose of the demonstration circuits is to show technique and not to provide ready-made circuits for use in applications. The design tool provides extremely versatile models that are, to a large extent, configurable to the users requirements for a large variety of power supply designs. It is not intended to replace the initial design process, but provides a tool whereby a design can be checked and finely tuned to meet the required specification. The importance of parasitic elements on components such as output capacitors and inductors cannot be over emphasized as they have an extremely marked effect on the stability of the power supply. Stray resistance in connectors or wires carrying high currents can result in significant voltage drop at the output terminals, especially during switched load changes. These resistances should be incorporated, where appropriate, to ensure accurate simulation results. The designer may experience problems with simulator convergence. This is an inherent problem when designing circuits employing high loop-gain such as those often used in switched-mode power supplies. If convergence problems persist, the circuit configuration should be checked with particular reference to feedback and compensation circuitry.

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State Averaging

State Averaging
This section describes the advantages and limitations of the state-averaging process. It is important that the limitations are understood before this power supply design tool is used to help design a Switched-Mode Power Supply. State-Averaging is a simplification process that is widely used by designers, usually to determine the steady-state of switching circuits. The technique can be readily applied to switching power supplies to determine the steady-state or, in the case of this power supply design aid, both the steady-and transient-states of power supply operation. State-Averaging has been performed on six configurations of power supply. The following describes in simplified form the state-averaging process used to create the models. No calculations of the form set out below are required to use the design aid but it is useful when using the tool to know how it works. Details of the way that the models perform transient analysis will not be described in detail because the method is complex, but steady-state analysis is described. For each of the six converter topologies comprehensive instructions are given to guide the user through transient simulation. Frequencydomain simulation is described in Chapter 12 and applies to all closed-loop converter topologies. In the six chapters describing the converter topologies, example circuits are given to demonstrate the use of the tool. The circuits and setup files to run the simulations are provided with the design-aid. The initial examination of the state-averaging process will be carried out on a Buck (un-isolated stepdown) converter. This type of converter is the simplest of the power supply configurations and is therefore easy to understand. Figure 1-1 shows a simple Buck converter. Steady-state operation of the circuit is as follows:

Figure 1-1: Simple Buck Converter

When the switch is closed, a voltage is applied across the inductor. The diode is reverse biased and may be ignored (diode recovery characteristics are not modeled). Current builds up through the inductor and flows into the reservoir capacitor C and the load Rl. The increase in current through the inductor from the time that the switch is turned on to the time it is turned off is proportional to both the voltage across the inductor during this time, and the time that the voltage was applied. When the switch is turned off, the inductor current cannot instantaneously fall to zero, but instead draws current through the freewheel diode and decays at a rate proportional to the voltage across the inductor. The fall in current from the time the switch is turned off to the time it next turns on is again proportional to both the voltage across the inductor during this time, and the time for which the voltage was applied (the off time of the switch). In both of the two states described above, the volt-second product across the inductor determines the change in inductor current. If the volt-second product for the switch-closed state is exactly cancelled by the volt-second product for the switch-open state, the supply is in steady-state and the average

Introduction and the State Averaging Process 1 3

Introduction and the State Averaging Process inductor current will not change from one cycle to the next. If on the other hand a volt-second balance does not exist, a transient change in output voltage or duty cycle must have occurred. The steady-state transfer function of the Buck converter is:
Vout = Vin ( 1 )Vd

where Vout is the output voltage, Vin is the input voltage and is the duty-cycle (the proportion of the period where the switch is ON). For steady-state operation the current-second product flowing into the reservoir capacitor must add up to zero if averaged over one complete cycle. This does not have to be considered for the Buck converter because any discrepancy in the current second product varies the output voltage and therefore the volt-second product across the inductor. However, for some of the other supply configurations the current-second product into the capacitor must be considered. If the volt-second product across the inductor is zero over one switching cycle, the voltage at point A (see Figure 1-1) must average out as Vout during steady-state operation. Consider now replacing the input voltage, the switch and the diode with a voltage source Vx of value equal to the right hand side of equation 1 (see Figure 1-2).

Figure 1-2: State-Averaged Buck Converter

The mean output voltage would remain the same but no switching noise would be present. Calculation of the voltage at Vx involves a number of variables including Vd, the diode voltage. Vd must be calculated by considering a theoretical freewheel diode, calculating the current that would flow through it and from this the voltage across it. Just as state-averaging can be used to calculate steady-state operation by directly using the supply transfer characteristic, it can also be used to calculate transient characteristics. In the case of the Buck converter no further work has to go into the model to get transient analysis to work. All the system poles are in place and are at the correct frequencies (determined by the values of L and C). With the Boost converter the pole frequency is partly dependent on the switching duty cycle. and calculation of the transfer function involves further analysis. The model of the Buck converter in the design aid incorporates switch resistance, inductor resistance and diode resistance to allow the correct Q factor to be set (although a resistive load has more effect on Q factor than the parasitic resistances). Parasitic resistances may have a marked effect on supply operation, especially the series parasitic resistance in the reservoir capacitors (not shown in Figure 12) which adds a zero to the frequency response of the supply. The power supply design aid provides a method for the user to vary the inductor, inductor resistance, diode resistance and a number of other model specific parameters. The value of inductors and capac-

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State Averaging itors should be set to the same values that will be used when the real circuit is built, however the value for inductor resistance should be set to the AC resistance value rather than the DC value. Non-linearities in the inductor value due to saturation or operating frequency, are not modeled in the design aid. Furthermore the value of the inductor resistance is set to a constant value. In a real inductor, the effective resistance may be determined by measuring the heat dissipation from the whole component. This heat dissipation will be made up of copper-losses and core hysteresis losses. Both must be accounted for when determining the value of RL (the inductor resistance). The small-signal DC loss (just the copper loss) will only account for a fraction of the total effective resistance. As current builds up in an inductor, the magnetic field induced by the current causes the current distribution in the windings to be non-uniform and current tends to bunch up on one side of the wire, increasing the effective resistance. At high frequencies skin-effect starts to have an effect and further increases the effective resistance. It is common for an inductor to have an AC resistance many times greater than the DC value. A factor of between 10 and 100 is not unusual. All the power-supply configurations except the C uk converter allow the user to define the reservoir capacitors by picking up the standard capacitor from the generic library and adding it to the schematic. A simple capacitor is not a very useful model of an electrolytic capacitor because electrolytics have quite a large effective series resistance (ESR), for instance a 4700F capacitor used in some of the demonstration circuits described in later chapters, had an ESR of 50 m. If this is not included in the circuit then the frequency response characteristics will almost certainly be incorrect. Resistance in the reservoir capacitors causes a zero to appear in the frequency response characteristic and may have a significant effect on the stability of the supply. When performing frequency analysis, it is important to note that the simulation results are only accurate up to half the switching frequency of the supply. For most situations this will not impose any limitations because the closed-loop gain will be less than unity at this frequency. The simulator will allow the user to specify a much higher stop frequency which will lead to a part of the Bode plot showing meaningless results. This is explained more comprehensively in the chapter on frequency analysis. The Buck converter is the least complex of the state-averaged converter topology models. Other converter types are more complex and discontinuities occur in the transfer functions as operation changes from continuous- to discontinuous-current mode. An explanation of the modeling technique used to create the state-averaged models is beyond the scope of this manual. All that is required is that the user should be able to use the models. Only functional descriptions of the models will be given from here on.

Features and Limitations of the Models


The models have the following characteristics and limitations: Frequency-domain analysis is valid up to half the switching frequency. No switching, or ripple due to switching, will be present on any inputs or outputs of the modeled supply. All currents flowing into or out of the topology-block (converter model) are averaged over one switching cycle. The Buck, Forward and Cuk converters are designed to work only in continuous-current mode. The parameters should be set using VeriBest Analog Model Library Manager of the topology-block before commencement of any simulations. For all topology-blocks except the Buck and Forward converters, the frequency term must be filled in as well as the values of the components.

Introduction and the State Averaging Process 1 5

Introduction and the State Averaging Process Inductor saturation is not modeled. The inductors are presumed ideal except for a user-definable fixed resistance. In the case of transformer coupled circuits the coupling-coefficient is unity. In most topology blocks the turned on switch is modeled as a constant voltage drop in series with a resistance. The switch can therefore be made to act like either a BJT or a MOSFET. In the case of the Cuk converter the switch is presumed ideal.

Converter Topologies
Six power supply converter topologies are provided in the Switched-Mode Power Supply design aid. These are: Boost Converter (boost) Buck-Boost Converter (bb) Buck Converter (buck) Flyback (isolated Buck-Boost) Converter (fb) Forward (isolated) Converter (fwrd) C uk (non-isolated) Converter (cuk)

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Chapter 2 Boost Converter

The Boost converter is a non-isolated circuit topology that may be used when the required output voltage of a supply may be greater than or equal to the input voltage. Figure 2-1 shows a basic boost converter with no parasitic elements included.

Figure 2-1: Simple Boost Converter

Two modes of operation are possible with this circuit, namely continuous-and discontinuous-current modes. In the former, the input current never falls to zero, and in the latter the input current falls to zero during each switching cycle. In neither case is the diode current continuous. The diode current of the state-averaged model, being the average diode current over one cycle, is always continuous. The equations for steady state operation of a Boost converter, omitting the diode voltage drop are set out below. In the continuous mode, the steady-state transfer function is:
Vin Vout = ----------1

where Vout is the output voltage, Vin is the input voltage and is the duty-cycle (the proportion of the period where the switch is ON). In the discontinuous mode, the output voltage is not directly defined. The steady-state output-current equation is given by:
Vin lout = -------------------------------------2fl ( Vout Vin )
2 2

where Vin is the input voltage, Vout is the mean output voltage, is the operating frequency, l is the inductor value and is the duty-cycle.

Boost Converter 21

Boost Converter The model of the Boost converter is not suitable for current-mode control. No indication of the peak incycle current is available at the model terminals. Operation must be restricted to circuits employing only voltage feedback loops.

Figure 2-2: Graphic Symbol

Features of the model are set out below. The input terminal IN will sink the average input current (averaged over one switching cycle). No voltage or current ripple, which would naturally result from converter switching action, will appear on this input. The input terminal CNTL must be set to a voltage between 0V and 1V relative to the datum node GND (not the GROUND terminal on the Boost topology-block which may or may not be connected to GND). The applied voltage represents a value numerically equal to the required switching duty-cycle. The CNTL terminal is compatible with the CNTL output provided on the switched-mode controller IC models described in Chapter 13. The voltage on the CNTL terminal is usually controlled by a feedback loop comprising the operational-amplifier in a controller IC, and external components, often including a compensation network. The output terminal OUT will deliver the mean output current (averaged over one switching cycle). As for the IN terminal, no voltage or current ripple will appear on this output. The terminal GROUND will conduct the average switch current (averaged over one switching cycle). Again, no voltage or current ripple, will be seen on this output. The GROUND terminal may take any voltage lower than the voltage on the IN terminal.

Setting Parameters
Before starting a simulation, the parameters of the Boost-converter model must be set. This is achieved by modifying the parset SA_BST settings of the model using the VeriBest Analog Model Library Manager. For further details, please refer to Chapter 4 of the VeriBest Analog Users Guide. The following table shows a list of the parameters and their meanings . FREQ L RL VS Switching frequency (Hz) Inductor value (H) (1) Inductor parasitic resistance (ohm) Switch saturation voltage (V)

22 VeriBest Switched-Mode Power Supply Design Manual

RS RD

Switch on-state resistance (ohm) Diode resistance (ohm)

(1) The value entered for the inductor resistance RL should be the AC resistance of the inductor and not the DC value. The AC resistance is always greater than the DC value because of the core losses, the skin effect, and current bunching effects. The AC resistance may be up to 100 times the DC resistance for high frequency and high current supplies. The switch resistance may be obtained from the data-sheet for the switching transistor being used. The SMPS is a very complex system with quite powerful feedback with potential for instability. This may cause some convergence problems which used to occur in discontinuous current modes or on the border of continuous and discontinuous current modes. Recently, we have upgraded our models, practically eliminating convergence problems. Nevertheless, should non-convergence occur, try reducing the load resistance to increase the initial current. This will ensure that the supply is operating in continuous-current mode. The other likely cause of non-convergence is that the supply is unstable. In this case the feedback loop should be broken and the supply should be run in the frequency domain to ascertain the phase and gain margins. Compensation can then be added to provide stability and the frequency-domain simulation repeated to confirm that the system is stable. Time-domain simulation can then be performed and convergence should be successful.

Operation of the Boost Topology-Block


The Boost topology-block is a state-averaged model of the boost converter of Figure 2-1. The parasitic resistances and switch saturation voltage listed in the previous table are included in the model to make simulations more accurate. Simulations using the Boost topology-block can be performed in both frequency- and time-domains. These are detailed separately below.

Time-Domain Simulation
In the time domain, information regarding output voltage, input and output currents and transient response can be obtained. No information pertaining to ripple voltage or ripple current is available. A demonstration circuit is shown in Figure 2-3 and the state-averaged equivalent circuit is shown in Figure 2-4. This circuit, and the setup file to run this test (tran.vas), are available in the SMPS design aid boost directory.

Boost Converter 2 3

Boost Converter

Figure 2-3: Boost Circuit

The circuit in Figures 2-3 and 2-4 is a non-isolated Boost converter designed around a Silicon General SG3524 controller IC. The circuit was designed to operate with a nominal 12V (10.2V to 14.5V) input and to deliver 30V regulated output at up to 2.5 amperes. A bread-board version of the circuit was built to enable a comparison between simulated and measured characteristics. Figure 2-5 shows the measured transient response of the circuit to a step load change from 0.65 to 1.5 amps. The waveforms are taken from a LeCroy digitizing oscilloscope. The top trace shows the output voltage and the bottom, the output current. The oscilloscope was AC coupled and so no DC voltage shift can be seen.

24 VeriBest Switched-Mode Power Supply Design Manual

Figure 2-4: State-Averaged Power Supply

The parameters of the Boost topology-block must be set up for each circuit prior to the commencement of any simulations. For the circuit in Figures 2-3 and 2-4 the following parameters were set for the Boost-block and the load. The GEAR integration method was selected. Following the changes outlined above, time domain analysis was selected. See Chapter 17 for instructions on the use of the SM_LOAD load-bank. The results are shown in Figure 2-6. The parameters of the Boost block, SA_BST, were as follows: Parameter FREQ L RL VS RS RD Value 65K 63m 160m 0 80m 10m Units Hz H ohm V ohm ohm

Operating frequency Inductor Value Inductor resistance Switch saturation voltage Switch resistance Diode resistance

The Settings dialog was changed as follows: Integration method GEAR

Boost Converter 2 5

Boost Converter The parameters of the load SM_LOAD were also changed as follows: Supply voltage Current 1 (low current) Current 2 (high current) V I1 I2 30 0.65 1.5 V A A

Parasitic resistors and inductors were included in series with the electrolytic capacitors C6, C7 and C8. The resistors have a very marked effect on the stability of the circuit and must be included in the simulation. The data-sheet value for the effective series resistance (ESR) of C6 and C7 was 50 mohm. The ESR of C8 (a better quality capacitor than either C6 or C7), was 25 mohm. The series resistance is quoted for operation at 100 Hz. The effective series inductance (ESL) of the capacitors was also included.

Figure 2-5: Measured Transient Response

Figure 2-6 shows the simulated results from the state-averaged circuit. As no switching noise is present, the transient response is easier to see than is the case with the real circuit. The overall transient voltage response is similar to the top trace in Figure 2-5. The lower trace is the output current when the load resistor is changed from 46 ohm to 20 ohm corresponding to load currents of 0.65 and 1.5 amps respectively.

26 VeriBest Switched-Mode Power Supply Design Manual

Figure 2-6: Simulated Transient Response

Frequency-Domain Simulation
In the frequency domain, simulations providing information about loop stability are possible. Chapter 12 describes a method, common to all power supply topologies, which allows open-loop Bode-plots to be derived.

Boost Converter 2 7

Boost Converter

Figure 2-7: Open_Loop Test Circuit

The circuit in Figure 2-7 was used to obtain information about the transfer characteristics of a typical open-loop boost converter. The voltage on the CNTL terminal, representing a duty-cycle of equal numerical value, was varied from 0 to 0.8 in steps of 0.1. The frequency response in the form of a Bode plot, from the input terminal IN to the output terminal OUT was derived for each value of dutycycle. The results are shown in Figure 2-8. For each simulation the power supply was running in continuous mode and the parameters for the Boost topology-block were set at their default values. The input supply VIN was a frequency-swept source with a DC offset of +10V to ensure that the supply was operating in continuous current mode. The frequency sweep was from 1Hz to 1kHz Note the variation in the resonant frequency as the duty-cycle is changed. Figure 2-9 shows the open-loop Bode plot for the power supply in Figures 2-3 and 2-4. To obtain the Bode plot, the input signal was injected on the right hand side of RBKLOOP (point X in Figure 2-4: State-Averaged Power Supply), using the voltage source with DC value equal to the steady state voltage at this point, and 1V AC component (see sources in freq.vas). The frequency response characteristics were taken from the left hand side (point Y). Chapter 12 explains the method for carrying out frequency-domain analysis, therefore only the results are shown here. The setup file to run this simulation is called freq.vas and can be found in the BOOST directory of the power supply design tool.

28 VeriBest Switched-Mode Power Supply Design Manual

88

Figure 2-8: Effect on frequency Response of Variations in Duty-Circle

The results shown below in Figure 2-9 show that the power supply has a phase margin of 35 degrees when the output current is 0.65A into a resistive load.

Figure 2-9: Open-loop Bode Plot of Boost Circuit

Boost Converter 2 9

Boost Converter

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Chapter 3 Buck-Boost Converter

The Buck-Boost converter is a non-isolated circuit configuration that may be used when the required output voltage of a supply may be greater than or less than the input voltage. Figure 3-1 shows a simplified Buck-Boost converter with no parasitic elements included.

Figure 3-1: Simple Buck-Boost Converter

Two states of operation are possible with this circuit, namely continuous-and discontinuous-current modes. In the former, the inductor current never falls to zero, and in the latter the inductor current falls to zero during each switching cycle. In neither case is the diode current continuous. The diode current of the state-averaged model, being the average diode current over one cycle, is always continuous. The equations for steady state operation of a Buck-Boost converter, omitting the diode voltage drop are set out below. In continuous mode the steady-state transfer function is: 1 Vout = -----------Vin 1 where Vout is the output voltage, Vin is the input voltage and period where the switch is closed.) is the duty cycle (the proportion of the

In discontinuous mode the output is not directly defined. The steady-state output current (Iout) equation is:
Vin lout = -----------------2flVout
2 2

where Vin is the mean input voltage, Vout is the mean output voltage, f is the operating frequency, l is the inductor value and is the duty-cycle. The model of the Buck-Boost converter is not suitable for current mode control. No indication of the peak in-cycle current is available at the model terminals. Operation must be restricted to circuits employing only voltage feedback loops.

Buck-Boost Converter 31

Buck-Boost Converter Figure 3-2 shows the graphic symbol for the Buck-Boost converter in the SMPS design and library.

Figure 3-2: Graphic Symbol

The input terminal IN will sink the mean input current (averaged over one switching cycle). No switching or current ripple, which would naturally result from converter switching action, will appear on this input. The input terminal CNTL must be set to a voltage between 0V and 1V relative to the datum node GND (not the GROUND terminal on the Buck-Boost topology-block which may or may not be connected to GND). The applied voltage represents a value numerically equal to the required switching duty-cycle. The CNTL terminal is compatible with the CNTL output provided on the switched-mode controller IC models described in Chapter 13. The voltage on the CNTL terminal is usually controlled by a feedback loop comprising the operational-amplifier in a controller IC, and external components, often including a compensation network. The output terminal OUT will deliver the mean output current (averaged over one switching cycle). As for the IN terminal, no voltage or current ripple will appear at this output. The terminal GROUND will conduct the average switch current (averaged over one switching cycle). Again, no voltage or current ripple will be seen on this output. The GROUND terminal may take any voltage below the voltage on the IN terminal.

Setting Parameters
Before starting a simulation, the parameters of the Buck-Boost converter model must be set. This is achieved by modifying the parset SA_BB settings of the model using the VeriBest Analog Model Library Manager. FREQ Switching frequency (Hz) L Inductor value (H) RL (1) Inductor parasitic resistance (ohm) VS Switch saturation voltage (V) RS Switch on-state resistance (ohm) RD Diode resistance (ohm) (1) The value entered for the inductor resistance RL should be the AC resistance of the inductor and not the DC value. The AC resistance is always greater than the DC value because of the skin effect and current bunching effects. The AC resistance may be up to 100 times the dc resistance for high frequency and high current supplies. The switch resistance may be obtained from the data-sheet for the switching transistor being used.

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The parameters of the Buck-Boost model are now defined. The rest of the simulation environment must be set before simulation can commence. It is recommended that GEAR integration is used. These options can be found in the Settings option of the Setup dialog. The SMPS is a very complex system with quite powerful feedback with potential for instability. This may cause some convergence problems which used to occur in discontinuous current modes or on the border of continuous and discontinuous current modes. Recently, we have upgraded our models, practically eliminating convergence problems. Nevertheless, should non-convergence occur, try reducing the load resistance to increase the initial current. This will ensure that the supply is operating in continuous-current mode. The other likely cause of non-convergence is that the supply is unstable. In this case the feedback loop should be broken and the supply should be run in the frequency domain to ascertain the phase and gain margins. Compensation can then be added to provide stability and the frequency-domain simulation repeated to confirm that the system is stable. Time-domain simulation can then be performed and convergence should be successful.

Operation of the Buck-Boost Topology-Block


The Buck-Boost topology-block is a state-averaged model of the Buck-Boost converter of Figure 3-2. The parasitic resistances and switch saturation voltage listed in the previous table are included in the model to make simulations more accurate. Simulations using the Buck-Boost topology-block can be performed in both frequency- and time-domains. These are detailed separately below.

Time-Domain Simulation
In the time domain, information regarding output voltage, input and output currents and transient response can be obtained. No information pertaining to ripple voltage or ripple current is available. A demonstration circuit is shown in Figure 3-3 and the state-averaged equivalent circuit is shown in Figure 3-4. This circuit, and the setup file to run this test (tran.vas), are available in the SMPS design and bb directory. The circuit in Figures 3-3 and 3-4 is a non-isolated Boost converter designed around a Silicon General SG3524 controller IC. The circuit was designed to operate with a nominal 12V input and to deliver 15V regulated output at up to 5 amperes. A bread-board version of the circuit was built to enable a comparison between simulated and measured characteristics.

Buck-Boost Converter 3 3

Buck-Boost Converter

Figure 3-3:Buck-Boost Circuit

Figure 3-5 shows the measured transient response of the circuit to a step load change from -0.5 to 1.5 amps. The waveforms are taken from a LeCroy digitizing oscilloscope. The top trace shows the output voltage and the bottom, the output current. The oscilloscope was AC coupled and so no DC voltage shift can be seen. The parameters of the Buck-Boost topology-block must be set up for each circuit prior to the commencement of any simulations. For the circuit in Figures 3-3 and 3-4 the following parameters were set for the Buck-Boost block and the load.

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Figure 3-4: State Averaged Power Supply

Following the changes outlined above, time domain analysis was selected. See Chapter 17 for instructions on the use of the SM_LOAD load-bank. The results are shown in Figure 3-6. The parameters of the Boost block were as follows: Parameter FREQ L RL VS RS RD Value 65K 63 160m 0 80m 10m Units Hz H ohm V ohm ohm

Operating frequency Inductor Value Inductor resistance Switch saturation voltage Switch resistance Diode resistance

The parameters of the load SM_LOAD were also changed as follows: Supply voltage Current 1 (low current) Current 2 (high current) V I1 I2 30 0.65 1.5 V A A

Buck-Boost Converter 3 5

Buck-Boost Converter The Settings dialog was changed as follows: Integration Method GEAR

The 4700 F capacitors were measured and found to be 6000 F. they were changed to this value using the property list within VBDC. Parasitic resistors and inductors were included in series with the electrolytic capacitors C6, C7 and C8. The resistors have a very marked effect on the stability of the circuit and must be included in the simulation. The data-sheet value for the effective series resistance (ESR) of the 4700mF capacitors is approximately 50mohm at 100 Hz. The effective series inductance (ESL) was also include.

Figure 3-5: Measured Transient Response

Figure 3-6 shows the simulated results from the state-averaged circuit. As no switching noise is present, the transient response is easier to see than is the case with the real circuit. The overall transient voltage response is similar to the top trace in Figure 3-5. The lower trace is the output current when the load resistor is changed from 30ohm to 10ohm corresponding to load currents of 0.5 and 1.5 amps respectively

36 VeriBest Switched-Mode Power Supply Design Manual

Figure 3-6: Simulated Transient Response

Frequency-Domain Simulation
In the frequency domain, simulations providing information about loop stability are possible. Chapter 12 describes a method, common to all power supply topologies, which allows open-loop Bode-plots to be derived.

Buck-Boost Converter 3 7

Buck-Boost Converter

Figure 3-7: Open-Loop Test Circuit

The circuit in Figure 3-7 was used to obtain information about the transfer characteristics of a typical Buck-Boost converter open-loop. The voltage on the CNTL terminal, representing a duty-cycle of equal numerical value, was varied from 0.1 to 0.9 in steps of 0.1. The frequency response in the form of a Bode plot, from the input terminal IN to the output terminal OUT was derived for each value of duty-cycle. The results are shown in Figure 3-8. For each simulation the power supply was running in continuous mode and the parameters for the Buck-Boost topology-block were set at their default values. The input supply VIN was a frequency-swept source with a DC offset of +10V. The frequency sweep was from 1Hz to 1kHz. Note the variation in the resonant frequency as the duty-cycle is changed. Figure 3-9 shows the openloop Bode plot for the power supply in Figures 3-3 and 3-4. To obtain the Bode plot, the input signal was injected on the right hand side of RBKLOOP (point X in Figure 3-4) and the frequency response characteristics are taken from the left hand side (point Y). Chapter 12 explains the method for carrying out frequency-domain analysis, therefore only the results are shown here. The setup file to run this simulation is called freq.vas and can be found in the bb directory of the SMPS design aid.

Figure 3-8: Effect on Frequency Response of Variations in Duty-Cycle

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The results shown below in Figure 3.9 show that the power supply has a phase margin of 43 degrees when the output current is 0.5A into a resistive load. In this example the simulation was first performed with 4700mF reservoir capacitors. The transient response was found to vary from that of the real power supply and therefore modifications were made to the simulated circuit to determine the component that caused the discrepancy. It was found that varying the resistance and capacitance of the reservoir capacitors had a marked effect on the operation of the circuit. A reasonable match between the response of real and simulated circuits was obtained when the reservoir capacitors were changed to 6000 F and the resistance (ESR) of the capacitors was 50 mohm. Having determined these parameters, a frequency-domain simulation was performed (see fig 3.9). In this case the frequency will be close to half of the switching frequency and simulation may not be very accurate.

Figure 3-9:Open loop Bode Plot of Buck-Boost Circuit

Buck-Boost Converter 3 9

Buck-Boost Converter

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Chapter 4 Buck Converter

The Buck configuration is a non-isolated converter topology that is used when the required output voltage of a supply is always less than the input voltage. The model is designed for operation in continuous-current mode where the input current never falls to zero. Figure 4-1 shows a simplified buck converter. No parasitic elements are included on the diagram.

Figure 4-1:Simple Buck Converter

The equation for steady state operation of a Buck converter is as follows:


Vout = Vin ( 1 )Vd

where is the duty-cycle (the proportion of the period when the switch is ON). Other parameters are as shown in Figure 4-1. The model of the Buck converter is not suitable for current mode control. No indication of the peak incycle current is available at the model terminals. Operation must be restricted to circuits employing only voltage feedback loops. Figure 4-2 shows the graphic symbol for the buck converter in the SMPS design aid library. Features of the model are as follows.

Figure 4-2: Graphic Symbol

Buck Converter 41

Buck Converter The input terminal IN will conduct the average input current (averaged over one switching cycle). No voltage or current ripple, resulting from converter switching action, will be present on this input. The input terminal CNTL must be set to a voltage between 0V and 1V relative to the datum node GND (not the GROUND terminal on the Buck topology-block which may or may not be connected to GND). The applied voltage represents a value numerically equal to the required switching duty-cycle. The CNTL terminal is compatible with the CNTL output provided on the switched-mode controller IC models described in Chapters 13-16. The voltage on the CNTL terminal is usually controlled by a feedback loop comprising the operational-amplifier in a controller IC, and external components, often including a compensation network. The output terminal OUT will conduct the average output current (averaged over one switching cycle). As for the IN terminal, no voltage or current ripple appear on this output. The terminal GROUND will conduct the average switch current (averaged over one switching cycle). Again, no voltage or current ripple will be seen on this output. The GROUND terminal may be floated at any voltage lower than the voltage on the IN input.

Setting Parameters
Before starting a simulation, the parameters of the Buck-converter model must be set. This is achieved by modifying the parset, SA_BUCK, settings of the model using the VeriBest Analog Model Library Manager. The following table shows a list of the parameters and their meanings. L RL VS RS RD Inductor value (H) (#1) Inductor parasitic resistance (ohm) Switch saturation voltage (V) Switch on-state resistance (ohm) Diode resistance (ohm)

(#1) The value entered for the inductor resistance RL should be the AC resistance of the inductor and not the DC value. The AC resistance is always greater than the DC value because of the skin effect and current bunching effects. The AC resistance may be up to 100 times the DC resistance for high frequency and high current supplies. The switch resistance and saturation voltage can be obtained from the data-sheet for the switching transistor being used. Similarly, if fast load switching transitions occur, convergence in transient analysis may fail. It is recommended that GEAR integration is used. This option can be found in the Settings dialog. If convergence problems persist it is likely that the supply is unstable. In this case the feedback loop should be broken and the supply should be run in the frequency domain to ascertain the phase and gain margins. Compensation can then be added to provide stability and the frequency-domain simulation repeated to confirm that the system is stable. Time-domain simulation can then be performed and convergence should be successful.

Operation of the Buck Topology-Block


The Buck topology-block is a state-averaged model of the buck converter of Figure 4-1. The parasitic resistances and switch saturation voltage listed in the previous table are included in the model to make simulations more accurate.

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Simulations using the Buck topology-block can be performed in both frequency- and time-domains. These are detailed separately below.

Time-Domain Simulation
In the time domain, information regarding output voltage, input and output currents and transient response can be obtained. No information pertaining to ripple voltage or ripple current is available. An example circuit is shown in Figure 4-3 and the state-averaged equivalent circuit is shown in Figure 4-4. This circuit, and the setup file to run this test (tran.vas), is available in the SMPS design aid buck directory.

Figure 4-3: Buck Circuit

Buck Converter 43

Buck Converter

Figure 4-4:Example State-Averaged Buck Circuit

The circuit in Figures 4-3 and 4-4 is a non-isolated Buck converter designed around a Silicon General SG3524 controller IC. The circuit was designed to operate with a nominal 24V input and to deliver 5V regulated output at up to 10A. A bread-board version of the circuit was built to enable a comparison between simulated and measured characteristics to be made. The parameters of the Buck topology-block must be set up for each circuit prior to the commencement of any simulations. For the circuit in Figures 4-3 and 4-4 the following parameters were set for the Buck-block and the load. The value of resistance for the inductor was set at 60 mohm although the DC small signal resistance was only 6 mohm. This is because the AC resistance is much greater than the DC value due to the magnetic field in the inductor causing the current distribution in the wires to vary and the effective resistance to rise. Following the changes outlined above, time domain analysis was selected. See Chapter 17 for instructions on the use of the SM_LOAD load-bank. The parameters of the Buck SA_BUCK block were as follows: Parameter Inductor Value Inductor resistance Switch saturation voltage Switch resistance Diode resistance L RL VS RS RD Value Units 110U 60m 2.05 1 1m H ohm V ohm ohm

44 VeriBest Switched-Mode Power Supply Design Manual

The parameters of the load SM_LOAD were also changed as follows: Supply voltage Current 1 (low current) Current 2 (high current) V I1 I2 5 2.5 6 V A A

The Settings dialog was changed as follows: Integration Method GEAR

Figure 4.5 shows the measured transient response of the circuit to a step load change from 2.5 to 6 amps. The waveforms are taken from a LeCroy digitizing oscilloscope. The top trace shows the output voltage and the bottom, the output current.

Figure 4-5: Measured Transient Response

Figure 4.6 shows the simulated results from the state-averaged circuit. No switching noise is present, although secondary parasitic oscillations can be seen on the voltage waveform (top trace). The overall transient voltage response is similar to the top trace in Figure 4-5. The lower trace shows the output current when the load resistor is changed from 2ohm to 0.83ohm corresponding to load currents of approximately 2.5 and 6 amps respectively once resistance of the load switch has been taken into account.

Buck Converter 45

Buck Converter

Figure 4-6: Simulated Results from State-Averaged Buck Circuit

In frequency domain, simulations can be performed to provide information about loop stability. Chapter 12 describes a method common to all power supply topologies, that allows open-loop Bode-plots to be obtained.

46 VeriBest Switched-Mode Power Supply Design Manual

Figure 4-7: Open-Loop Test Circuit

The circuit in Figure 4-7 was used to obtain information about the transfer characteristics of a typical buck converter open-loop. The voltage on the CNTL terminal, representing a duty-cycle of equal numerical value, was varied from 0 to 0.9 in steps of 0.1. The frequency response in the form of a Bode plot, from the input terminal IN to the output terminal OUT was derived for each value of dutycycle. The results are shown in Figure 4-8. For each simulation, the parameters of the Buck topology block were set at their default values. The input supply VIN was a frequency-swept source with a DC offset of +10V. The frequency sweep was from 1Hz to 1kHz. Phase and group-delay traces have been removed for clarity. Figure 4-9 shows the open-loop Bode plot for the power supply in Figures 4-3 and 4-4. To obtain the Bode plot, the input signal was injected on the right hand side of RBKLOOP (point X in Figure 4-4), and the frequency response characteristics are taken from the left hand side (point Y). Chapter 12 explains the method for carrying out frequency-domain analysis, therefore only the results are shown here.

Figure 4-8: Effect on Frequency Response of Variations in Duty-Cycle

Buck Converter 47

Buck Converter

Figure 4-9: Open-Loop Bode Plot of Buck Circuit Gain

The setup file to run this simulation is called freq.vas and can be found in the buck directory of the power supply design tool. The results shown in Figure 4-9 show that the power supply has a phase margin of 55 degrees when the output current is 2.5A into a resistive load.

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Chapter 5 Flyback Converter

The Flyback converter is an isolated circuit topology that may be used when the required output voltage may be greater or less than the input voltage. Figure 5.1 shows two basic flyback converters with all parasitic elements left out. In configuration 1 the switch is in the positive input side and in configuration 2 the switch is in the negative side. Both configurations are electrically identical if parasitic inter-winding capacitance is not taken into account. The graphic symbol for the flyback converter in the SMPS design aid resembles configuration 1, but a circuit using configuration 2 can be simulated using the same model. The model of the Flyback converter will enable simulation of three windings, two silicon diodes and a switch. The switch can be configured to resemble a perfect switch, a BJT or a MOSFET. The input and output windings (see Figure 5-1) have an associated turns ratio, while the turns ratio between the input winding and the catch winding is fixed at one. The equations set down later in this chapter refer to the transfer function from input to output considering only the input and output windings. A catch winding is incorporated into the circuit and has the effect of clamping the output voltage to a maximum value dependent on the input voltage Vin, the turns ratio N and the voltage drop of the silicon diode. In the state averaged circuit this is its only function. In a real circuit the catch winding has a second purpose. It is used to protect the switch by coupling the flux from the input winding that does not cut the output winding. The energy stored in this uncoupled flux is discharged back into the input of the supply. Although the catch winding should protect the switch, it is probable that, on a real circuit, snubbing will be required to provide further protection. There will still be some leakage inductance in the input winding causing flux that is cut by neither the catch or output windings. The associated stored energy must be dissipated either in a snubbing network or in the switch, if it is avalanche rated. In the state-averaged model, the coupling coefficients are all unity and no snubbing has been included.

Flyback Converter 51

Flyback Converter

Figure 5-1: Simple Fly-Back Converters

Two modes of operation are possible with this circuit, namely continuous-and discontinuous-current modes. In the former, the overall inductor current (the sum of the currents flowing into the dotted end of the three windings) never falls to zero, and in the latter this current falls to zero during each switching cycle. In neither case is the output diode current continuous in the real circuit, but in the stateaveraged model the output diode current is continuous and assumes a value of the mean diode current of the real circuit on a cycle by cycle basis. The equations for steady state operation of a Flyback converter are similar to those of the Buck-Boost except for the addition of a turns ratio term N. The following equations assume that the catch winding is not conducting any current. The equations, omitting the diode voltage drop and parasitic resistances, are set out below. In the continuous mode, the steady-state transfer function is:

52 VeriBest Switched-Mode Power Supply Design Manual

Vout = -------------------- Vin N(1 )

where Vout is the mean output voltage, Vin is the input voltage, N is the turns ratio and cycle (the proportion of the period where the switch is ON).

is the duty-

In the discontinuous mode, the output voltage is not directly defined. The steady-state output-current equation is given by:
Vin Iout = -------------------------2fLinVout
2 2

where Vin is the input voltage, Vout is the mean output voltage, f is the operating frequency, Lin is the input inductor value and is the duty-cycle. The model of the flyback converter is not suitable for current-mode control. No indication of the peak in-cycle current is available at the model terminals. Operation must be restricted to circuits employing only voltage feedback loops. Figure 5-2 shows the graphic symbol for the Flyback converter in the SMPS design aid library.

Figure 5-2: Graphic Symbol

The input terminal IN will sink the average input current (averaged over one switching cycle). No voltage or current ripple, which would naturally result from converter switching action, will appear on this input. The input terminal CNTL must be set to a voltage between 0V and 1V relative to the datum node GND (not the GROUND terminal on the Flyback topology-block which may or may not be connected to GND). The applied voltage represents a value numerically equal to the required switching duty-cycle. The CNTL terminal is compatible with the CNTL output provided on the switched-mode controller IC models described in Chapter 13. The voltage on the CNTL terminal is usually controlled by a feedback loop comprising the operational-amplifier in a controller IC, and external components, often including a compensation network. The output terminals OUTP and OUTN will deliver respectively the positive and negative mean output current (averaged over one switching cycle). As for the IN terminal, no voltage or current ripple will appear on this output.

Flyback Converter 5 3

Flyback Converter The terminal GROUND will conduct the average switch current (averaged over one switching cycle). Again, no voltage or current ripple, will be seen on this output. The GROUND terminal may take any voltage lower than the voltage on the IN terminal.

Setting Parameters
Before starting a simulation, the parameters of the Flyback-converter model must be set. This is achieved by modifying the parset SA_FB of the model using the VeriBest Analog Model Library Manager. The following table shows a list of the parmeters and their meanings. FREQ L N RL1 RL2 VS RS RD Switching frequency (Hz) Primary inductance value (H) Turns ratio (1) Inductor primary winding resistance (ohm) (1) Inductor secondary winding resistance (ohm) Switch saturation voltage (V) Switch on-state resistance (ohm) Diode resistance (ohm)

(1) The value entered for the inductor resistance RL should be the AC resistance of the inductor and not the DC value. The AC resistance is always greater than the DC value because of the skin effect and current bunching effects. The AC resistance may be up to 100 times the DC resistance for high frequency and high current supplies. The switch resistance may be obtained from the data-sheet for the switching transistor being used. The parameters of the Flyback model are now defined. The rest of the simulation environment must be set before simulation can commence. Under some circumstances the Flyback topology-block requires more iterations to obtain DC convergence than is standard in the default setup for the simulator. It is recommended that GEAR integration is used. If convergence problems are experienced it is possible that the supply is operating on the border of continuous and discontinuous inductor-current operation. In this case an increase in the load current will cause the supply to run well into continuous inductor-current mode and convergence should be more successful. If problems still persist, it is possible that the supply is unstable. In this case run the supply in frequency domain and check the phase and gain margins. Compensate the supply if necessary. As a last resort, the value of GMIN in the Settings dialog can be increased to 1E9 if a transconductance amplifier is being used such as in the SG3524, SG3525 or SG3527 controller models, or 1E-8 if the TL494 is being used. Changing GMIN should be of considerable assistance in aiding convergence, but it will have a detrimental effect on the accuracy of the simulation, especially if the circuit relies on high impedances for some aspect of its operation such as the error amplifier.

Operation of the Flyback Topology-Block


The Flyback topology-block is a state-averaged model of the Flyback converter of Figure 5-1. The parasitic resistances and switch saturation voltage listed in following table are included in the model to make simulations more accurate. Simulations using the Flyback topology-block can be performed in both frequency- and time-domains. These are detailed separately below.

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Time-Domain Simulation
In the time domain, information regarding output voltage, input and output currents and transient response can be obtained. No information pertaining to ripple voltage or ripple current is available. A demonstration circuit is shown in Figure 5-3 and the state-averaged equivalent circuit is shown in Figure 5-4. This circuit, and the setup file to run this test (tran.vas), are available in the SMPS design aid FB directory. The circuit in Figures 5-3 and 5-4 is a non-isolated Flyback converter designed around a Silicon General SG3524 controller IC. The circuit was designed to operate with a nominal 100V input and to deliver 5V regulated output at up to 10 amps.

Figure 5-3: Flyback Circuit

Parasitic resistors and inductors were included in series with the electrolytic capacitors C6,C7 and C8 in Figure 5-4. The resistors have a very marked effect on the stability of the circuit and must be included in the simulation. The data-sheet values for parasitics for a typical 4700mF capacitor are 50 mohm for the effective series resistance (ESR) and 30nH for the effective series inductance (ESL).

Flyback Converter 5 5

Flyback Converter

Figure 5-4: State-Averaged Power Supply

The parameters of the Flyback topology-block must be set up for each circuit prior to the commencement of any simulations. For the circuit in Figures 5-3 and 5-4 the following parameters were set for the Flyback block SA_FB and the load. Parameter FREQ L N RL1 RL2 VS. RS RD Value 50K 1m 15 10m 10m 0.1 100m 50m Units Hz H ohm ohm V ohm ohm

Operating frequency Inductor Value Turns ratio Primary winding resistance Secondary winding resistance Switch saturation voltage Switch resistance Diode resistance

The parameters of the load SM_LOAD were also changed as follows: Supply voltage Current 1 (low current) Current 2 (high current) V I1 I2 5 5 10 V A A

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Following the changes outlined, time domain analysis was selected. See Chapter 17 for instructions on the use of the SM_LOAD load-bank. The results of time-domain analysis are shown in Figure 5-5.

Figure 5-5: Simulated Transient Response

Flyback Converter 5 7

Flyback Converter

Frequency-Domain Simulation
In the frequency domain, simulations providing information about loop stability are possible. Chapter 12 describes a method, common to all power supply topologies, which allows open-loop Bode-plots to be derived.

Figure 5-6: Open-Loop Test Circuit

The circuit in Figure 5-6 was used to obtain information about the transfer characteristics of a typical Flyback converter open-loop. The voltage on the CNTL terminal, representing a duty-cycle of equal numerical value, was varied from 0.1 to 0.5 in steps of 0.1. The frequency response in the form of a Bode plot, from the input terminal IN to the output terminal OUT was derived for each value of dutycycle. The results are shown in Figure 5-7. For each simulation the power supply was running in continuous mode and the parameters for the Flyback topology-block were set at their default values. The input supply VIN was a frequency-swept source with a DC offset of +100V. The frequency sweep was from 0.1Hz to 10kHz. When the turns ratio N is one, the gain of the converter never exceeds 0dB by very much because of the presence of the catch-winding and clamp diode. If the output voltage of the supply is required to be larger than the input voltage then the turns ratio should be made fractional and less than one. The frequency response curves are shown for values of duty-cycle from 0.1 to 0.5 and no higher. This is because the catch winding will come into effect at duty-cycles greater than 0.5 and limit the gain to just over 0dB (over 0dB because of the diode voltage drop).

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Figure 5-7: Effect on Frequency Response of Variations in Duty-Cycle from 0.1 to 0.5 Figure 5-8 shows the open-loop Bode plot for the power supply in Figures 5-3 and 5-4. To obtain the Bode plot, the input signal was injected on the right hand side of RBKLOOP (point X in Figure 5-4) and the frequency response characteristics are taken from the left hand side (point Y). Chapter 12 explains the method for carrying out frequency-domain analysis, therefore only the results are shown here. The environment file to run this simulation is called freq.vas and can be found in the FB directory of the power supply design aid. The results shown below in Figure 5-8 show that the power supply has a phase margin of 62 degrees when the output current is 5 amps into a resistive load.

Figure 5-8: Open-Loop Bode Plot

Flyback Converter 5 9

Flyback Converter

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Chapter 6 Forward Converter

The Forward converter is essentially an isolated Buck converter. The topology allows wider output voltage range while retaining the simplicity of the Buck circuit. Figure 6-1 shows a simplified forward converter. No parasitic elements are included on the diagram.

Figure 6-1:Simple Forward Converter

The equation for steady state operation of a Forward converter is


Vin Vswitch Vout = ----------------------------------- Vd N

where is the duty-cycle (the proportion of the period when the switch is ON) and N is the turns ratio of the transformer. Other parameters are as shown in Figure 6-1. The model of the Forward converter is not suitable for current mode control. No indication of the peak in-cycle current is available at the model terminals. Operation must be restricted to circuits employing only voltage feedback loops.

Figure 6-2: Graphic Symbol

Forward Converter 61

Forward Converter The input terminals IN1 and IN2 will conduct the average input current (averaged over one switching cycle). No voltage or current ripple, resulting from converter switching action, will be present on these terminals. The input terminal CNTL must be set to a voltage between 0V and 1V relative to the datum node GND (Note that there is no GROUND terminal on the forward converter block). The applied voltage represents a value numerically equal to the required switching duty-cycle. The CNTL terminal is compatible with the CNTL output provided on the switched-mode controller IC models described in Chapters 1316. The voltage on the CNTL terminal is usually controlled by a feedback loop comprising the operational-amplifier in a controller IC, and external components, often including a compensation network. The output terminals OUT1 and OUT2 will conduct the average output current (averaged over one switching cycle). Again, no voltage or current ripple, resulting from converter switching action, will be present on these terminals.

Setting Parameters
Before starting a simulation, the parameters of the Forward-converter model must be set. This is achieved by modifying the parset of the model using the VeriBest Analog Model Library Manager. The following table shows a list of the parameters and their meanings. L RL VS RS RD N Inductor value (H) (1) Inductor parasitic resistance (ohm) Switch saturation voltage (0 for MOS, approx 0.2 for BJT) Switch on-state resistance (ohm) Diode resistance (ohm) Transformer turns ratio

(1) The value entered for the inductor resistance RL should be the AC resistance of the inductor and not the DC value. The AC resistance is always greater than the DC value because of the skin effect and current bunching effects. The AC resistance may be up to 100 times the DC resistance for high frequency and high current supplies. The switch resistance and saturation voltage can be obtained from the data-sheet for the switching transistor being used If fast load switching transitions occur, convergence in transient analysis may fail. It is recommended that GEAR integration is used.

Operation of the Forward Topology-Block


The Forward topology-block is a state-averaged model of the forward converter of Figure 6-1. The parasitic resistances and switch saturation voltage listed in the table have been included in the model to make simulations more realistic. Simulations using the Forward topology-block can be performed in both frequency- and time-domains. These are detailed separately below.

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Time-Domain Simulation
In time domain, information regarding output voltage, input and output currents and transient response can be obtained. No information pertaining to ripple voltage or ripple current is available. The stateaveraged example circuit is shown in Figure 6-3. This circuit, and the setup file to run this test (tran.vas), is available in the SMPS design aid forward directory.

Figure 6-3: Example State-Averaged Forward Circuit

The circuit is an un-isolated Forward converter designed around a Silicon General SG3524 controller IC. It was designed to operate with a nominal 220V input and to deliver 5V regulated output at up to 60A. The parameters of the Forward topology-block must be set up for each circuit prior to the commencement of any simulations. For the circuit in Figure 6-3, the following parameters were set for the Forward-block and the load. The parameters of the following block were changed: Forward Block SA_FWRD Parameter Inductor Value Inductor resistance Switch saturation voltage Switch resistance Diode resistance Turns ratio L RL VS. RS RD N Value Units 8.6u 10m 1 1 1m 5 H ohm V ohm ohm

Forward Converter 6 3

Forward Converter The parameters of the load SM_LOAD were also changed as follows: Supply voltage Current 1 (low current) Current 2 (high current) V I1 I2 5 15 30 V A A

The Settings dialog was changed as follows: Integration Method GEAR

The value of resistance for the inductor was set at 10 mohm although the DC small signal resistance would only be approximately 2mohm. This is because the AC resistance is much greater than the DC value due to the magnetic field in the inductor causing the current distribution in the wires to vary and the effective resistance to rise. Figure 6-4 shows the simulated results from the state-averaged circuit. No switching noise is present, although secondary parasitic oscillations can be seen on the voltage waveform (top trace). The lower trace is the output current when the load resistor is changed from 0.333 ohm to 0.167 ohm corresponding to load currents of 15 and 30 amps respectively.

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Figure 6-4: Simulated Transient Response The load change was performed using the model SM_LOAD which is a voltage controlled resistor. The operation of this device, which is effectively a model of a load-bank, is detailed in Chapter 17. The value of resistance for the inductor was set at 10 mohm although the DC small signal resistance would be much lower. This is because the AC resistance is much greater than the DC value due to the magnetic field in the inductor causing the current distribution in the wires to vary and the effective resistance to rise.

Frequency-Domain Simulation
In frequency domain, simulations can be performed to provide information about loop stability. Chapter 12 describes a method common to all power supply topologies, that allows open-loop Bode-plots to be obtained.

Figure 6-5: Open-Loop Test Circuit

The circuit in Figure 6-5 was used to obtain information about the transfer characteristics of a typical forward converter open-loop. The voltage on the CNTL terminal, representing a duty cycle of equal numerical value was varied from 0.1 to 1.0 in steps of 0.1. The frequency response in the form of a Bode plot, from the input terminal IN to the output terminal OUT was derived for each value of dutycycle. The results are shown in Figure 6-6.

Forward Converter 6 5

Forward Converter

Figure 6-6: Effect on Frequency Response of Variations in Duty-Cycle.

For each simulation the parameters of the Forward topology block were set at their default values. The input supply VIN was a frequency-swept source with a DC offset of +220V. The frequency sweep was from 1Hz to 10KHz. Phase and group-delay traces have been removed for clarity. Figure 6-7 shows the open-loop Bode plot for the power supply in Figure 6-3. To obtain the Bode plot, the input signal was injected on the right hand side of RBKLOOP (point X in Figure 6-3), and the frequency response characteristics are taken from the left hand side (point Y).

Figure 6-7: Open-Loop Bode Plot for Example Power Supply Gain

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Chapter 12 explains the method for carrying out frequency-domain analysis, therefore only the results are shown here. The setup file to run this simulation is called freq.vas and can be found in the forward directory of the power supply design aid. The results shown in Figure 6-7 show that the power supply has a phase margin of 50 degrees when the output current is 15A into a resistive load.

Forward Converter 6 7

Forward Converter

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Chapter 7 C uk Converter

The Cuk converter model, unlike the other models in this manual, is written in DIABLO. The basic cir cuit for a C uk converter is shown in Figure 7-1 and as can be seen, three energy-storage elements are involved in the circuit, two inductors and one capacitor.

Figure 7-1: Simple Cuk Converter A feature of the circuit is that the output voltage is always negative with respect to the input. Continuous input and output current is possible, and in the case of the state-averaged model in the design aid, is a requirement as discontinuous current mode is not modeled. Operation of the circuit is quite complex, but a simplified description follows. Consider the situation where the link capacitor is charged up in the direction shown in Figure 7-1. When the switch switches on, the left hand side of the capacitor is grounded and the voltage on the right hand side becomes negative. Both the input and output inductor currents rise and energy is transferred from the capacitor to the load and output inductor. During this stage the diode is reverse biased. When the switch switches off, the input inductor current continues to flow and charges up the link capacitor. Both the output inductor current and the capacitor current flow through the diode. Figure 7-2 shows the input and output inductor currents and the state of the switch over a number of operating cycles.

C uk Converter 71

C uk Converter

Figure 7-2: C uk Converter Operation The transfer function for the Cuk converter in continuous mode is:
Vout = ----------------Vin (1 )

is the duty-cycle (proportion of the where Vout is the output voltage, Vin is the input voltage and cycle when the switch is on). In reality the transfer function is rather more complex and involves the operating frequency, the values of all the energy-storage components and the parasitic resistances. The state-averaged model uses this more complex transfer function. The equation describing it is too complex to explain in this manual. The model of the Cuk converter is not suitable for current-mode control. No indication of the peak incycle current is available at the model terminals. Operation must be restricted to circuits employing only voltage feedback loops, or open-loop operation

Figure 7-3: Graphic Symbol

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The input terminal IN will sink the average input current (averaged over one switching cycle). No voltage or current ripple, which would naturally result from converter switching action, will appear on this input. The input terminal CNTL must be set to a voltage between 0V and 1V relative to the datum node GND (not the GROUND terminal on the Cuk topology-block which may or may not be connected to GND). The applied voltage represents a value numerically equal to the required switching duty-cycle. The CNTL terminal is compatible with the CNTL output provided on the switched-mode controller IC models described in Chapter 13. The voltage on the CNTL terminal is usually controlled by a feedback loop comprising the operational-amplifier in a controller IC, and external components, often including a compensation network. The output terminal OUT will deliver the mean output current (averaged over one switching cycle). As for the IN terminal, no voltage or current ripple will appear on this output. The terminal GROUND will conduct the average switch current (averaged over one switching cycle). Again, no voltage or current ripple, will be seen on this output. The GROUND terminal may take any voltage lower than the voltage on the IN terminal.

Parameters
Before starting a simulation, the parameters of the C uk converter model must be set. This is achieved by modifying the parset SA_CVK of the model using the VeriBest Analog Model Library Manager. C FREQ LIN LOUT N RD RIN ROUT Capacitor value (F) Switching frequency (Hz) Input Inductor value (H) Output Inductor value (H) Diode emission coefficient Diode resistance (ohm) (1) Input inductor resistance (ohm) (1) Output inductor resistance (ohm)

(1) The value entered for the inductor resistance RL should be the AC resistance of the inductor and not the DC value. The AC resistance is always greater than the DC value because of the skin effect and current bunching effects. The AC resistance may be up to 100 times the dc resistance for high frequency and high current supplies. The parameters of the Cuk model are now defined. The rest of the simulation environment must be set before simulation can commence. It is recommended that GEAR integration is used. These options can be found in the Settings dialog.

Operation of the C uk Topology-Block


The Cuk topology-block is a state-averaged model of the Cuk converter of Figure 7-1. The parasitic resistances listed in the table are included in the model to make simulations more accurate. The fol lowing equation is the simplified transfer function of the C uk converter.

C uk Converter 7 3

C uk Converter

Vout = ----------------Vin (1 )

When the parasitic components and the diode characteristics are included in the model the transfer function varies slightly. Figure 7-4 shows a graph of output voltage versus applied duty-cycle for dutycycle varying from 0 to 1 (X axis). The input voltage was fixed at 30 volts and the load was a 10ohm resistor. All the model parameters were set at their default values. Note that at high duty-cycles the output voltage does not tend to infinity, as is suggested by equation 10, but drops off towards zero. The point at which this turn-around occurs is dependent on the values of the components in the circuit.

Figure 7-4: Typical C uk Converter Transfer Function Simulations using the C uk topology-block can be performed in both frequency- and time-domains. These are detailed separately below.

Time-Domain Simulation
In the time domain, information regarding output voltage, input and output currents and transient response can be obtained. No information pertaining to ripple voltage or ripple current is available. A state-averaged demonstration circuit is shown in Figure 7-5. This circuit, and the setup file to run this test (tran.vas), are available in the SMPS design aid CUK directory.

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Figure 7-5: State-Averaged Power Supply

The circuit is designed to operate with an input supply of between 20V and 30V and to give an output of 24V. The control circuitry is based on a Texas Instruments TL494 PWM controller IC, details of which are given in Chapter 16. The closed loop gain of the op-amp in the TL494 is set at just 16.5 because of the difficulties stabilizing this supply topology. Certain parameters must be changed before the simulation can commence. The parameters of the SA_CUK parset were changed. Parameter Capacitor value C Frequency FREQ Input inductor value LIN Output inductor value LOUT Diode emission coefficient N Diode resistance RD Input inductor resistance RLIN Output inductor resistance RLOUT Value 1U 100K 0.5m 02m 1 10m 50m 50m Units H Hz H H ohm ohm ohm

The Settings dialog was changed as follows: Integration Method GEAR

C uk Converter 7 5

C uk Converter The parameters of the load SM_LOAD were also changed as follows: Supply voltage Current 1 (low current) Current 2 (high current) V I1 I2 2.4 20.1 1 V A A

The demonstration circuit is designed to operate with a maximum output current of 1 amp. Figure 7-6 shows the output voltage-transient and output current for a step load-change from -0.1A to -1A in 10 ms after a 0.5ms delay, and a further step change from -1A to -0.1A 15 ms after the first transition. The voltage waveform shows that the output voltage varies by nearly 40mV which is better than 0.2% variation.

Figure 7-6: Simulated Transient Response Waveforms Output Current

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Frequency-Domain Simulation
In the frequency domain, simulations providing information about loop stability are possible. Chapter 12 describes a method, common to all power supply topologies, which allows open-loop Bode-plots to be derived.

Figure 7-7:Open-Loop Test Circuit

The circuit in Figure 7-7 was used to obtain information about the transfer characteristics of a typical Cuk converter open-loop. The voltage on the CNTL terminal, representing a duty-cycle of equal numerical value, was varied from 0.1 to 0.9 in steps of 0.1. The frequency response in the form of a Bode plot, from the input terminal IN to the output terminal OUT was derived for each value of dutycycle. The results are shown in Figure 7-8. For each simulation the power supply was running in con tinuous mode and the parameters for the C uk topology-block were set at their default values. The input supply VIN was a frequency-swept source with a DC offset of +10V. The frequency sweep was from 10Hz to 10kHz. Note the variation in the resonant frequency as the duty-cycle is changed.

Figure 7-8: Effect on Frequency Response of Variations in Duty-Cycle

C uk Converter 7 7

C uk Converter Figure 7-9 shows the open-loop Bode plot for the power supply in Figure 7-5. To obtain the Bode plot, the input signal was injected on the right hand side of RBKLOOP (point X in Figure 7-5) and the frequency response characteristics are taken from the left hand side (point Y). Chapter 12 explains the method for carrying out frequency-domain analysis, therefore only the results are shown here. The setup file to run this simulation is called freq.vas and can be found in the cuk directory of the power supply design aid.

Figure 7-9: Open Loop Bode Plot of C uk Circuit

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Chapter 8 Current-Mode Control

Current-mode control is a supported feature in some models of the power-supply design aid. This chapter explains how this form of control has been implemented and how the models can be used. Guidelines for the use of individual controller models are given in the appropriate chapter for the device in question. A general overview is given here. Current mode control can be implemented in many ways. The methods supported by the models in the accompanying SMPS design aid library support in-cycle current limited voltage mode control (UC3840) and cycle-by-cycle current-mode control (UC3842, UB3844, and UC3846).

Cycle-By-Cycle Current-Mode Control


Cycle-by-cycle current level monitoring is the most common method for control of the inner loop in a current-mode power-supply. This strategy can be implemented in various ways. Consider a powersupply which uses a signal derived from the inductor current as the timing ramp as when a Unitrode UC3842 or UC3844 controller is used. Figure 8-1 shows a simplified boost-converter power circuit. The voltage developed across the resistor RSENSE may be used as a timing ramp in a switching supply. This is the approach used in circuits using the UC3842 and UC3846 controller ICs. The voltage developed across RSENSE is shown in Figure 8-2. As can be seen, the waveforms are not continuous, but in both continuous and discontinuous modes there is a ramp that can be used in the control circuit. Most other topologies can be considered in a similar manner; for instance, the transformer in the flyback converter, even with many output windings, acts as an inductor when the switch is closed and the inductor-current displays similar characteristics to those shown in Figure 8-2.

Figure 8-1: Simplified Boost Circuit

Current-Mode Control 81

The voltage waveform Vsense is as shown in Figure 8-2.

Figure 8-2: Vsense Voltage

No switching operations occur in the state-averaged models but information about the normal inductor current waveform must be made available to the controller. This information is supplied to the controller from three terminals on the converter blocks. These three terminals merely provide signals conveying ramp information. The signals are the voltages that would be present across Rsense at the instants when the switch opens and closes, and also the slope of the current waveform when the switch is conducting. The signals will be referred to as IPK, ITR and ISL respectively. All are voltages, ISL having a value of 1V per amp/microsecond. In a practical circuit, the sense voltage Vsense is compared with the output voltage from the voltage feedback error amplifier in the control IC. When the Vsense voltage exceeds the error-amplifier voltage the mark-period of the switching cycle is terminated. This control mechanism gives pulse-by-pulse current limiting and is a simple and efficient method of controlling a power-supply. In most cases this control methodology requires slope compensation to ensure stability. This will be discussed later. The SMPS design aid provides state-averaged models for various current-mode control ICs and converter topologies. In order to facilitate current-mode control it is necessary to provide the control ICs with the IPK, ITR and ISL signals if full current-mode control is to be implemented, or just the IPK signal if in-cycle current limit is required. This information is passed to the control IC by connecting up appropriate control terminals as shown in Figure 8-3.

Figure 8-3: Connections Between Control IC and Converter Models for a Circuit Employing Full Current-mode Control

Voltage-Mode Control with In-Cycle Current Limit


The Unitrode UC3840 is a more complex controller than the UC3842, UC3844 or UC3846. A voltage ramp is generated internally and is used instead of Vsense (Figure 8-1) as the ramp in the timing circuit. The controller is capable of operating in both current-mode and voltage-modes, and can switch between modes during operation. The device model is explained in detail in Chapter 18, only a simple explanation of operation is given here. Figure 8-4 shows the schematic symbol for the Boost converter and Figure 8-5 shows the symbol for the UC3840. Only one of the three current sensing terminals provided in the Boost converter model,

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the peak inductor current I PK, is required for circuit operation. The controller is designed to operate in voltage-mode (as opposed to current mode) with in-cycle peak current limiting. The peak inductor-current signal is passed to the controller which uses the signal to terminate the mark-time of the switching cycle and limit the converter current should this become necessary. If the peak-current threshold is not reached then the converter operates in voltage-mode. A demonstration circuit is provided in the chapter on the current-mode Boost converter (Chapter 11). This circuit shows both the effect of current-limiting and circuit operation in voltage-mode. The model of the UC3840 controller is simplified. All the ancillary circuitry providing shutdown and start-up as well as under-voltage lockout, has been removed from the model, because the tool is designed to be used for circuit stabilization and examination of the transient response during normal operation. The additional circuitry that would be required to implement the rest of the functionality present on the IC would cause simulations to progress more slowly without adding to the utility of the model.

Figure 8-4: Schematic Diagram of a Boost Converter

Figure 8-5: Schematic Diagram of UC3840 Model

Slope Compensation
Some current-mode converter topologies require slope compensation to ensure stability when operating in continuous current mode with duty-cycles in excess of fifty percent. Slope compensation is usually implemented by adding a proportion of the ramp signal to the positive input of the duty-cycle

Current-Mode Control 83

comparator, reducing the error signal required to terminate the switch mark-time in proportion to the duty-cycle. This technique cannot be implemented directly on a state-averaged version of a controller because there is no ramp signal or comparator. To overcome this problem, an alternative scheme has been developed. A user configurable parameter has been added to the UC3842, UC3844 and UC3846 controllers to enable the state-averaged equivalent of the ramp-signal to be added to the duty-cycle comparator. In the case of the UC3840, the solution is simpler and conventional slope compensation circuitry can be used. With the UC3842, UC3844 and UC3846 controller models, slope compensation is accomplished by connecting the three control signals described earlier, IPK, ITR and ISL. From these signals it is possible to reconstruct the ramp signal characteristics. A ramp-compensation factor must then be set using the Property Override dialog. This technique is described in detail in the appropriate control IC chapter. In the case of the UC3840 controller, slope compensation is accomplished in a more conventional manner. Resistors are added to the circuit in the same way as in a practical circuit. No switching ramps are available, but the voltage of the internally-generated ramp at the time that switching occurs is provided as an output from the UC3840 model. Adding a proportion of this signal to the error-amplifier input signal is equivalent to providing slope compensation in a practical circuit. The slope compensation signal has effect only by modifying the instant at which switching would occur.

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Chapter 9 Multiple-Output Forward Converter

The topology of the multiple-output forward (m_fwrd) converter is similar to the simple forward converter described in Chapter 6, but with extra secondary windings added to the transformer. The models provided with the design tool allow forward converters with two or three outputs to be simulated. The output inductors may be coupled by setting the appropriate parameters in the parset file. The input terminals IN1 and IN2 will sink and source respectively the average input current. No voltage or current ripple, normally present and resulting from converter switching action, will be present on these terminals. The input terminal CNTL must be set to a voltage between 0V and 1V relative to the datum node GND (Note that there is no GROUND terminal on the forward converter block). The applied voltage represents, and is a numerically equal to the required switching duty-cycle. The CNTL terminal is compatible with the CNTL output provided on the switched-mode controller IC models described in Chapters 14-16. The voltage on the CNTL terminal is usually controlled by a feedback loop comprising the operational-amplifier in a controller IC, and external components, often including a compensation network.

Multiple-Output Forward Converter 91

Figure 9-1: Graphic Symbols

The output terminals OUT1 and OUT2 will source and sink the average output current. No voltage or current ripple, resulting from converter switching action, will be present on these terminals. Note that a pair of output terminals are provided for each output from the multiple-output forward converter blocks.

Setting Parameters
Before starting a simulation, the parameters of the Forward-converter model must be set. You achieve this by modifying the parset file using the VeriBest Analog Model Library Manager. The following table shows a list of the parameters and their meanings for the three-output forward converter. The two-output converter model has a subset of these parameters available. The switch resistance and saturation voltage can be obtained from the data-sheet for the switching transistor being used.

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Model Parameters Meanings Input Stage N VS RS Number of turns in Primary Switch saturation voltage Switch Resistance (ohm) Output A A_N A_L A_RL A_RD Number of turns in secondary Inductor value (H) Inductor parasitic resistance (ohm) Diode resistance (ohm) Output B B_N B_L B_RL B_RD Number of turns in secondary Inductor value (H) Inductor parasitic resistance (ohm) Diode resistance (ohm) Output C C_N C_L C_RL C_RD Number of turns in secondary Inductor value (H) Inductor parasitic resistance (ohm) Diode resistance (ohm) Output inductor coupling coefficients (see note below) K_AB K_BC K_CA Coupling; inductor A to inductor B Coupling; inductor B to inductor C Coupling; inductor C to inductor A

Note: All three output inductor coupling coefficients must be defined for correct operation of the converter.

Multiple-Output Forward Converter 93

Operation of the Multiple-Output Forward Topology-Block


The parasitic resistances and switch saturation voltage listed in the previous table have been included in the model to make simulations more realistic. Simulations using the Multiple-output Forward Topology-block can be performed in both frequencyand time-domains. These are detailed separately below.

Time-Domain Simulation
In time-domain, information regarding output voltage, input and output currents and transient response can be obtained. No information pertaining to ripple voltage or ripple current is available. The stateaveraged example circuit is shown in Figure 9-2. This circuit, and the setup file to run this test (tran.vas), is available in the SMPS design aid m_fwrd directory.

Figure 9-2: Example State-Average Multiple-Output Forward Circuit

The parameters of the Forward topology-block must be set up for each circuit prior to the commencement of any simulations. For the circuit in Figure 9-2, the following parameters were set for the For-

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ward-block, SA_FWRD3, and the output loads. Note that due to multiple use of the LOAD block, only one of them (LOAD1) uses parset SM_LOAD, the others use the instant specific analog parameters placed near the symbol using the Property List dialog. During elaboration, these parameters override the parset parameter. Another way of dealing with multiple use of a block, especially useful for blocks with long parameter lists, is to close the parset to a slightly different name, use a specific name and use this name as the model name for specific instance of the block. Then, each instance will have its own, unique parset. Parameter Forward block: Number of turns in primary Switch saturation voltage Switch resistance (ohm) Output A Number of turns in secondary Inductor value (H) Inductor parasitic resistance (ohm) Diode resistance (ohm) Output B Number of turns in secondary Inductor value (H) Inductor parasitic resistance (ohm) Diode resistance (ohm) Output C Number of turns in secondary Inductor value (H) Inductor parasitic resistance (ohm) Diode resistance (ohm) Output inductor coupling coefficients Inductor A to inductor B Inductor B to inductor C Inductor C to inductor A Load (5 volt output): Output voltage V 5 K_AB K_BC K_CA 800m 800m 800m C_N C_L C_RL C_RD 13 250u 4m 1m B_N B_L B_RL B_RD 13 250u 4m 1m A_N A_L A_RL A_RD 6 50u 4m 1m Name Value

N VS RS

78 1 1

Multiple-Output Forward Converter 95

Parameter Current for 0V control signal Current for 1V control signal Load (+12 and -12 volt outputs): Output voltage Current for 0V control signal Current for 1V control signal

Name I1 I2

Value 10 20

V I1 I2

12 5 10

Figure 9-3 shows the simulated results from the state-averaged circuit. No switching noise is present, although secondary parasitic oscillations can be seen on the voltage waveforms. The load changes were performed using the model SM_LOAD which is a voltage controlled resistor. The operation of this device, which is effectively a model of a load-bank, is detailed in Chapter 17. Feedback is taken from the 5V output. In a practical circuit, post regulation would be used on the +12V and -12V outputs to give acceptable regulation.

Figure 9-3: Simulated Transient Response

Frequency-Domain Simulation
In the frequency-domain, simulations may be performed to provide information about loop stability. Chapter 12 describes a method, common to all power-supply topologies, that allows open-loop Bode plots to be obtained.

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Figure 9-4 shows the open-loop Bode plot for the power-supply in Figure 9-2. An input signal was injected on the right hand side of RBKLOOP (point X in Figure 9-2), and the frequency response characteristics are taken from the left hand side (point Y).

Figure 9-4: Open-Loop Bode Plot for Example Power Supply

Chapter 12 explains the method for carrying out frequency-domain analysis, therefore only the results are shown here. The setup file to run this simulation is called freq.vas and can be found in the m_fwrd directory of the power supply design tool. The results shown in Figure 9-4 show that the power supply has a phase margin of 25 degrees. The simulation was performed with the parameters of the topology and load blocks set as described for the transient analysis and with the load control signals at 0V.

Multiple-Output Forward Converter 97

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Chapter 10 Multiple-Output Flyback Converter

The Multiple-Output Flyback Converter model (f3op) has three output windings in addition to an internally connected catch winding. The turns ratio between the primary and secondary windings can be individually set. The model is suitable for fixed frequency operation in both current- and voltage-mode. Figure 10-1 shows the basic flyback converter with parasitic elements omitted. Note that only one of the three output windings on the model is shown in this diagram. The flyback converter model allows basic switch characteristics to be set. The switch can be configured to operate with either a constant voltage drop (that is, resembling a bipolar transistor), or a constant resistance (that is, resembling a MOSFET), or a combination of the two.

Figure 10-1: Flyback Converter

The model is capable of simulating both the continuous- and discontinuous-current modes of operation. In the former, the total inductor current (the sum of the currents flowing into the dotted ends of the windings) is always greater than zero, whereas in the latter the current falls to zero during each switching cycle. In the practical circuit the output diode currents are always discontinuous. In a state-averaged implementation where all switching has been removed, the output currents will be continuous and each assumes a value equal to the mean diode current for the respective output.

Multiple-Output Flyback Converter 101

The equations for steady-state operation of a flyback converter are similar to those of the Buck-Boost configuration except for the addition of the turns ratios and inherent current sharing characteristics. The following equation assumes that the catch winding is not conducting. Omitting the diode, switch losses and parasitic resistances, the continuous mode steady-state transfer function is:
Vin Vout = ----------- -------1 N

where Vout and Vin are as shown in Figure 10-1, N is the transformer turns ratio from primary to secondary, that is, N0/Nn where n refers to one of the three secondary windings. In the discontinuous mode, the output voltage is not directly defined. The circuit transfers a calculable amount of energy from the input to the outputs on each switching cycle. The output windings and diodes act as an analog-OR gate transferring energy as required to maintain the correct voltage balance. This implies that the flyback configuration automatically shares current across windings, and if one output should fall below the specified output voltage, more of the energy transferred by the converter, will be directed to that output. The equations describing this sharing action are beyond the scope of this manual, suffice to say that the voltage per turn of the output windings is uniform. It is important to note that energy balance is always adhered to by the state-averaged model as well as by the practical circuit. This energy balance includes energy stored in the inductor.

Figure 10-2: Graphic Symbol

The input terminal IN will sink the average input current (averaged over one switching cycle). No voltage or current ripple, which would naturally result from converter switching action, will appear on this input. The input terminal CNTL must be set to a voltage between 0V and 1V relative to the datum node GND (not the GROUND terminal on the flyback model, which is not necessarily connected to GND).

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The applied voltage represents the required switching duty-cycle, to which it is numerically equal. The CNTL terminal is compatible with the CNTL output provided on the current-mode controller IC models. The voltage on the CNTL terminal is usually controlled by a feedback loop comprising the operationalamplifier in a controller IC, and external components, often including a compensation network. The output terminals are un-named on the schematic, but are associated with ratio identifiers Nn where n is 1, 2 or 3. The outputs are in pairs and output polarity may be determined from the diodes on the schematic symbol. The terminal GROUND will conduct the average switch current (averaged over one switching cycle). Again, no voltage or current ripple will be seen at this terminal. The GROUND terminal may take any voltage lower than the voltage on the IN terminal. Three additional terminals are provided on this model to facilitate current-mode control. The IPK and ITR terminals are outputs and have zero output impedance. The voltages on these terminals are respectively the voltage that would be developed across RSENSE at the instant before the switch opens and the instant after the switch closes. The voltages are referenced to the datum node GND (node 0 in the netlist). A further terminal, ISL, supplies a voltage proportional to the slope of the inductor current waveform during the switch mark-time. The output voltage is one volt per amp/microsecond of rate of change of inductor current. This is used in conjunction with the input and output voltages to determine the slope of the inductor down-slope for current mode slope-compensation.

Setting Parameters
Before commencing a simulation, the parameters of the flyback converter model must be set. This is achieved by modifying the FB30P parset of the model. Model Parameters Meanings F L RL1 ND RDIODE RSENSE RSWITCH VSWITCH N0 N1 N2 N3 R1 R2 R3 Operating Frequency (Hz) Primary winding inductance (H) Resistance of primary winding (ohm) * Diode emission coefficient ** Diode resistance (ohm) Sense resistor resistance (ohm) Switch resistance (ohm) Switch voltage drop (V) Number of turns on the primary and catch windings Number of turns on output winding 1 Number of turns on output winding 2 Number of turns on output winding 3 Resistance of output winding 1 (ohm) * Resistance of output winding 2 (ohm) * Resistance of output winding 3 (ohm) *

** This parameter should be set to 1 for silicon diodes.

Multiple-Output Flyback Converter 103

* The value entered for the inductor resistances should be the effective ac resistances of the inductors and not the dc values. The ac resistance is always greater than the dc value because of skin and proximity effects. The switch resistance may be obtained from the data-sheet for the switching transistor being used.

Operation of the Multiple-Output Flyback Model


The multiple-output flyback model is a state-averaged model of the flyback converter of Figure 10-1. The parasitic resistances and switch saturation voltage listed in the table are included in the model to make simulations more accurate. Simulations using the model can be performed in both frequency- and time-domains. These two types of simulation are described separately below.

Time-Domain Simulation
In the time-domain, information regarding output voltage, input and output currents and transient response can be obtained. No information about the ripple voltage or ripple current is available because of the state-averaged nature of the model, however, the peak and trough input currents can be viewed by examining the IPK and ITR terminals on the flyback topology block. A state-averaged demonstration circuit is shown in Figure 10-3. This circuit, and the setup file to run the simulations (tran.vas) are available in the SMPS design aid fb3op directory. The circuit in Figure 10-3 is a non-isolated three output flyback converter designed around a Unitrode UC3844 current mode controller IC. The circuit was designed to operate with a nominal 100V supply input and to deliver +5V, +12V and +24V output regulated on the 5V line with up to 30 amps output on the 5V rail. Parasitic resistors and inductors are included in series with the electrolytic capacitors because they have an effect on the transient response. The data-sheet values for the effective series resistance (ESR) of a typical 3300mF capacitor is 20mohm and the effective series inductance (ESL) is 30 nH. The demonstration power-supply has 60 turns on the input winding, and 6, 13 and 25 turns on the output windings. Taking a diode-drop of 0.8V into account, the expected duty-cycle when operating in continuous mode and regulating on the 5V rail is approximately:
60 5.8 ----6 DutyCycle = ---------------------------- = 0.37 60 5.8 ----- + 100 6

If point X is viewed when the circuit is operated closed loop, the simulated duty cycle is found to be 0.373; the error results because the diode drop is not exactly 0.8V and there are other losses in the circuit. The setup file tran.vas performs switching tests on the circuit. The current on the 5V rail is switched from 5A to 30A after 10 ms and back again at 20 ms. At 40 ms the 12V rail is switched from 500 mA to 1.5A and back to 500 mA at 50 ms. At 60 ms the 24V rail is switched from 100 mA to 300 mA and at 70 ms it is switched back to 100 mA. The loads are purely resistive and the above currents apply only when the outputs are exactly at the specified output voltages. Figures 10-4 to 10-10 show various aspects of the performance of the supply under switching conditions. The envelope of the peak and trough voltage waveforms across RSENSE are shown in Figure

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10-6. The peak and trough input currents are equal to these voltages divided by the value of the sense resistor RSENSE. The circuit in Figure 10-3 will operate in continuous or discontinuous modes. The continuous mode is the more difficult mode to obtain a reasonable transient response from. The transient response in discontinuous mode is better than that in continuous mode.

Figure 10-3: Multiple-Output Flyback Converter

The parameters of the flyback model must be set up for each circuit prior to the commencement of any simulations. For the circuit in Figures 10-3 and 10-4 the following parameters were set for the flyback block and the loads. The parameters of the Flyback block stored in FB30P are as follows: Operating frequency Inductor Value Inductor resistance Diode emission coefficient Diode resistance Sense resistor resistance Switch resistance Switch saturation voltage Number of primary turns Number of turns (winding 1) Number of turns (winding 2) F L RL1 ND RDIODE RSENSE RSWITCH VSWITCH N0 N1 N2 50k 750u 10m 1 100m 100m 80m 0 60 6 13 Hz H ohm ohm ohm ohm V

Multiple-Output Flyback Converter 105

Number of turns (winding 3) Winding 1 resistance Winding 2 resistance Winding 3 resistance

N3 R1 R2 R3

25 10m 10m 10m

ohm ohm ohm

The parameters of the load SM_LOAD blocks were as follows: SM_LOAD (5V rail) Supply voltage Current 1 (low current) Current 2 (high current) SM_LOAD (12V rail) Supply voltage Current 1 (low current) Current 2 (high current) SM_LOAD (24V rail) Supply voltage Current 1 (low current) Current 2 (high current)

V I1 I2

5 5 30

V A A

V I1 I2

12 500m 1.5

V A A

V I1 I2

24 100m 300m

V A A

The parameters for the UC3844 controller are as follows: Operating frequency Duty cycle limit Reference voltage Slope compensation F DUT_LIM VREF SLCOMP 100K 500m 5 400m Hz V

Note that the slope compensation is given relative to the slope of the up-slope rather than that of the down-slope. For this application, the downslope in continuous mode steady-state operation is:
downslope = upslope ---------------(1 )

The slope compensation should be greater than 50% of the down-slope value. The up-slope is:
Vin 100 upslope = -------- = ------------------------- = 0.1333 Amperespermicro sec ond 6 L 750 10

and the down-slope is therefore 0.0783 amps per microsecond. The minimum slope compensation for a circuit able to operate at duty-cycles greater than 50% would be half this figure. The number that should be entered in the SLCOMP field is:
SLCOMP = ------------------- = 0.2936 2( 1 )

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The value 0.4 has been substituted to ensure greater than necessary slope compensation. The above relations only apply to buck-boost and flyback circuits. Simulation results for the circuit follow.

Figure 10-4: Flyback Converter Outputs

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Figure 10-5: Output Voltage from the 5V Rail

Figure 10-5 shows that the output voltage changes only one percent for a load change from 5A to 30A.

Figure 10-6: Outputs from the IPK and ITR Terminals

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Figure 10-7: Duty-Cycle (CNTL Terminal)

The simulation results shown in Figures 10-8 to 10-10 show the converter changing operating modes from discontinuous to continuous and back again. To perform this simulation, the loads were set up as shown previously, except that the 5V load has been changed to switch from 100mA to 5A and back. When the 5V rail is only sourcing 100mA the supply operates discontinuously.

Figure 10-8: Output Voltages with Modified Load Settings

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Figure 10-9: Peak and Trough Voltage Across RSENSE

When the trough voltage in Figure 10-9 is zero, the supply is operating in discontinuous mode. Figure 16-10 shows that the duty-cycle drops when the supply operates in discontinuous mode.

Figure 10-10: Duty-Cycle (CNTL Terminal)

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Frequency-Domain Simulation
The frequency-domain response of the converter operating in current-mode differs from that in voltage-mode. With current-mode control the pole introduced by the flyback inductor is effectively removed from the control loop. This has the effect that the gain roll-off occurs at a higher frequency than in a voltage-mode supply. A pole has been included in the control loop at 1250 Hz to stop high frequency oscillations. Figure 10-11 shows the frequency response for the supply operating in continuous mode with the 5V rail supplying 5A. The setup file for this test is freq1.vas. Figure 10-12 shows the frequency response when the supply is operating in discontinuous mode with the 5V rail supplying 100 mA. The setup file for this test is freq2.vas. Chapter 12 describes a method for obtaining the frequency response of any state-averaged powersupply. The bias point for the frequency-source applied to point X was found by examining the VBASE file and finding the DC convergence value for point X after a closed loop transient simulation. This voltage was then applied to point X and the frequency response examined at point Y.

Figure 10-11: Frequency Response for Continuous Mode Operation

Multiple-Output Flyback Converter 1011

Figure 10-12: Frequency Response for Discontinuous Mode Operation

Note that the frequency-domain simulation is invalid above half the switching frequency of the converter. In this case the maximum frequency at which the results are meaningful is 25 kHz.

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Chapter 11 Current-Mode Boost Converter

The Boost converter model is a non-isolated topology that may be used to provide an output voltage greater than the input voltage. This model contains DIABLO functions and provides for variable frequency and fixed frequency operation in both continuous and discontinuous current modes. Figure 11-1 shows the basic boost converter with parasitic elements omitted. The boost converter model allows basic switch characteristics to be set. The switch can be configured to operate with either a constant voltage drop (that is, resembling a bipolar transistor), or a constant resistance (that is, resembling a MOSFET), or a combination of the two.

Figure 11-1: Simple Boost Converter with Current Sense Resistor

Two modes of operation are possible with this circuit, namely continuous and discontinuous current modes. In the former, inductor current flows at all times, and in the latter, the current is zero for a portion of each switching cycle. In neither case is the diode current continuous in a real circuit; however, the diode current of the state-averaged model, being the average diode current over one cycle, is always continuous. The equations for steady state operation of a boost converter, omitting the diode and transistor losses are set out below. In the continuous mode:
Vin Vout = ----------1

Where Vout is the output voltage, Vin is the input voltage, and the period for which the switch is conducting).

is the duty-cycle (the proportion of

Current-Mode Boost Converter 111

Current-Mode Boost Converter In the discontinuous mode, the output voltage is not directly defined. The converter transfers energy from the input to the output at a rate which is a function of the input voltage, operating frequency, dutycycle, and circuit inductance. For given input and output voltages, the output current may be defined. In the steady-state, the output current equation is given by:
Vin lout = -------------------------------------2fl ( Vout Vin )
2 2

where f is the frequency of operation and l is the inductance of the boot inductor. The model of the Boost converter is suitable for both voltage- and current-mode control strategies. Additional terminals are provided which yield information concerning the maximum and minimum inductor currents, as well as the time-rate-of-change of inductor current during the mark time of the boost switch. This information is used by the control IC models to implement in-cycle current limiting and current-mode control. The voltages on the terminals IPK and ITR (peak and trough current sense terminals) may be examined to determine the envelope of the switching inductor current waveform.

Figure 11-2: Graphic Symbol

The input terminal IN will sink the average input current (averaged over one switching cycle). No voltage or current ripple, which would naturally result from converter switching action, appears on this input. The input terminal CNTL must be set to a voltage between 0V and 1V relative to the datum node GND (not the GROUND terminal on the Boost converter model which is not necessarily connected to GND). The applied voltage is numerically equal to the required switching duty cycle. The FREQ terminal operates in a similar manner to the terminal of the same name on the controller IC models. The frequency of operation of this model can be set by applying a voltage of one volt per 10KHz of switching frequency. An output terminal called F_OUT is provided on some of the SMPS control IC models which should be connected to the FREQ terminal on the Boost converter. This enables a single control voltage to determine the operating frequency of both the controller model and the boost converter model. The resistor RSENSE is connected between the notional switch and the GROUND terminal. There are three broken lines emanating from the connection between the resistor and the switch, each of which is necessary if the model is to be used with a current-mode controller. The terminal labelled ISL provides information to the controller IC model about the rate-of-change of current during the spacetime is provided. The signal has a magnitude of 1V for each amp per microsecond change in inductor current. The terminals marked IPK and ITR give an output voltage equal to RSENSE times the peak

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and trough inductor currents respectively. These signals may be examined to determine the operating mode of the circuit (continuous- or discontinuous-current mode) and are also required by the currentmode controller IC models. Together they show the envelope of the switching inductor-current waveform. The OUT terminal is an output signal that sources the average output current over one cycle of operation. No switching noise, naturally resulting from converter switching action, is present on this output. The voltage across the diode is modeled as a constant which may be set using the VeriBest Analog Model Library Manager. The additional terminals are provided on this model to facilitate current-mode control. The IPK and ITR terminals are outputs and have zero output impedance. The voltages on these terminals are respectively the voltage that would be developed across RSENSE at the instant before the switch opens and the instant after the switch closes. The voltages are referenced to the datum node GND (node 0 in the netlist). A further terminal, ISL, supplies a voltage proportional to the slope of the inductor current waveform during the switch mark-time. The output voltage is one volt per amp/microsecond of rate of change of inductor current. This is used in conjunction with the input and output voltages to determine the slope of the inductor down-slope for current mode slope-compensation.

Setting Parameters
Before starting a simulation, the parameters of the Boost model must be set. You achieve this by modifying the parset file using the VeriBest Analog Model Library Manager. LIN RIN VDIODE RDIODE RSENSE RSWITCH VSWITCH Inductance Inductor resistance Diode voltage drop Diode resistance Sense resistor resistance Switch resistance Switch voltage drop

Note: Operating frequency must be set using a voltage source.

Operation of the Current-Mode Boost Topology Block


The boost topology-block is a state-averaged model of the boost converter in Figure 11-1. The parasitic resistances and switch saturation voltage listed in the previous table are included in the model to make simulations more accurate. It is important that the total switch voltage (that is, the fixed constant voltage VSWITCH plus the voltage developed across the switch resistance (RSWITCH x mean input current) is much less than the input voltage if the simulation results are to be accurate. This limitation should not cause problems during normal operation. Simulations using the current-mode Boost topology block can be performed in both frequency-and time-domains. These are detailed separately in the following paragraphs. In the time-domain, information regarding input and output current and voltage can be obtained. Determination of operating mode can be made by examining the trough inductor current monitoring terminal ITR (if ITR is zero, then the converter is operating in discontinuous mode). The peak- and trough-current sense terminals can be used to view the envelope of switching current. This facility is useful as it

Current-Mode Boost Converter 113

Current-Mode Boost Converter enables confirmation, or otherwise, of correct operation of the circuit under development. Note that the voltage on these terminals corresponds with the peak and trough currents multiplied by the value of the sense resistor RSENSE. This resistor is set using the Library Manager. The output impedance of the IPK and ITR terminals is zero. Figure 11-3 shows a simple test circuit comprising a boost converter open-loop. The input resistance to the converter was set to 100 mohm and the input voltage to 50 V. The value of the inductor was set first to 100 milli-ohm and then 50 H. A sweep of duty-cycle from 0 to 1 was performed, while keeping the operating frequency constant at 20kHz (there was a 2v source connected to the FREQ terminal). Figure 11-4 shows the output voltage of the circuit for both values of inductance. Note the change in operating mode from continuous to discontinuous and back to continuous when the inductor is set to 50 H. Figure 11-5 shows the same test, but with the input resistance changes to 10 mohm. The peak output voltage is now considerable larger than before.

Figure 11-3: Simple Test Circuit

Figure 11-4: Output Voltage vs Duty-Cycle

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Figure 11-5: Output Voltage vs Duty-Cycle (Larger Scale)

Time-Domain Simulation
The example circuit was designed to give a 30V DC output at up to 1.5 amperes from an input voltage of 12V DC. The circuit, which is controlled using a Unitrode UC3840 controller, is fundamentally a voltage-mode circuit but features peak in-cycle current-limiting. The circuit is connected to a load (SM_LOAD described in Chapter 17) which acts as a variable resistance. The value of this load resistance is changed to show the circuit operating in discontinuous-mode as well as continuous mode. Operation under current-limit conditions is also demonstrated. The schematic for the circuit is shown in Figure 11-7. Before starting the simulation, the Boost topology block and load should be set up as follows. The parameters of the Current-mode Boost block BOOST_CM are as follows: Inductor Value Inductor resistance Diode voltage Diode resistance Switch resistance LIN RIN VDIODE RDIODE RSWITCH 63 160m 0.7 10m 100m 80m 0 H ohm V ohm ohm ohm V

Sense resistor resistance RSENSE Switch saturation voltage VSWITCH

Current-Mode Boost Converter 115

Current-Mode Boost Converter The parameters of the load SM_LOAD block was as follows: Supply voltage Current 1 (low current) Current 2 (high current) V I1 I2 30 0.5 1.5 V A A

Figure 11-6 shows the output voltage for a transient load change from 0.5 A to 1.5A. This test is saved as tran1.vas

Figure 11-6: Output Voltage for Transient Load Change

Examination of the voltages on the IPK and ITR terminals of the boost converter model shows the envelope of the switching current waveform. The two voltage traces represent the peak and trough inductor currents multiplied by the value of the sense resistor. Figure 11-8 shows the meaning of the voltages at these terminals.

Figure 11-7: Boost Circuit

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Figure 11-8: Explanation of IPK and ITR Voltages

Figure 11-9: Inductor Current Envelope (shown as voltage developed across RSENSE)

The results shown in Figure 11-9 are as expected. Observe that the trough current is greater than zero indicating that the supply was operating in continuous-mode. During this simulation, the duty-cycle was 0.646 when the output current was 1.5A and 0.620 when the output current was 0.5A. You can see this by examining the voltage on the CNTL terminal on the controller or boost converter block (not shown in the figure). If the load resistance is reduced further, the operating mode changes. The defining equations for discontinuous-mode are fundamentally different from those defining the continuous-mode. A slow-down in the speed of transient simulation may be experienced during mode change. The waveforms shown in Figures 11-10 and 11-11 show the effect of switching the load resistance from 20 ohm to 300 ohm corresponding to load currents of 1.5A and 0.1 amps respectively. The setup file for this test is called tran2.vas. Figure 11-10 shows the envelope of the peak and trough currents of the inductor-current waveform. It can be seen that the trough current falls to zero when the load current is 100mA and is non-zero otherwise. This shows that the operation of the supply changes between continuous- and discontinuous-current modes.

Current-Mode Boost Converter 117

Current-Mode Boost Converter

Figure 11-10: Inductor Current Envelope During Operating Mode Change

Figure 11-11: Output Voltage During Load Switching form 0.1A to 1.5A

The UC3840 controller is designed to use cycle-by-cycle peak current limiting as a protection mechanism. This feature is included in the model, but in a manner suitable for state-averaged current-mode control.

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The circuit shown in the Boost Circuit figure is designed to limit the peak inductor current to 7.5A. This was arranged by setting the sense resistor in the boost converter to 100 mohm and connecting the sense terminal IPK on the converter model to the CS (current sense) terminal on the UC3840. When the peak inductor current reaches 7.5 amps, the voltage on the CS terminal is 0.75 volts. A voltage divider (RCLIM1 and RCLIM2) divides the reference voltage and presents a voltage of 0.75V to the CLT (current limit) terminal on the UC3840 controller model. The state-averaged converter is designed, like the practical device, to reduce the duty-cycle if the voltage on the sense terminal CS reaches the voltage on CLT. Unlike the practical device, the model is not implemented with a comparator to perform the task. Instead, a high gain feedback loop is used to reduce the duty-cycle so that the voltage on CS never exceeds that on CLT. A side-effect of this method is that the voltage on CS never reaches that on CLT, but remains just lower. The difference in operation is of no consequence unless the value of the sense resistor in the controller model is made very small (less than a few milli-ohm). Figure 11-12 shows the effect on the output voltage of switching the load resistance from 30 ohm to 10 ohm. The circuit operates in continuous current mode throughout this test. When the load is 30 ohm, the output voltage is approximately 30V as expected. When the load resistance is reduced, the supply enters the current-limit mode and the duty-cycle is limited to prevent the peak current from exceeding the prescribed limit. Figure 11-13 shows the envelope of the switching voltage developed across the sense resistor RSENSE during the simulation. The voltage on the CLT terminal is also shown. Note that the voltage on the CS terminal rises to approach the voltage on CLT.

Figure 11-12: Output Voltage Change When Switching from Load Resistance (30 ohm to 10 ohm)

Current-Mode Boost Converter 119

Current-Mode Boost Converter

Figure 11-13: Current-Sense Waveforms Showing Current Limiting

Frequency-Domain Simulation
The example circuit may also be operated in frequency-domain. The Bode-plot showing the open-loop transfer function is given in Figure 11-14. The waveforms show that the phase-margin is 86 degrees. The frequency-sweep is valid up to half the switching frequency of the supply. This supply operates at 65kHz and therefore the whole of the Bode-plot shown below is valid. In the frequency-domain, simulations providing information about loop stability are possible. Chapter 12 describes a method, common to all power-supply topologies, which allows open-loop Bode plots to be derived. The simplified low frequency (dc) open-loop transfer-function in continuous-mode, from the duty-cycle terminal CNTL to the output is:
dVout Vin -------------- = -----------------2 d (1 ) Vin - DC Transfer function (dB) = 20log ------------------ 2 (1 ) The simplified transfer function from the input terminal IN to the output while operating in the continuous mode is: Vout 1 ----------- = ----------1 Vin

or, as given by the simulator during frequency analysis:

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Figure 11-14: Bode Plot of Circuit Operating with 60 ohm Load Resistance

Current-Mode Boost Converter 1111

Current-Mode Boost Converter

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Chapter 12 Frequency-Domain Analysis

One of the major advantages of using state-averaging techniques over conventional simulation is that frequency-domain analysis is possible. VBA will simulate a state-averaged power supply in the frequency domain, and allow the results to be viewed as a Bode plot. Before describing methods for performing frequency-domain analysis on power supply circuits, it is worth explaining how the simulator works in the frequency domain. A thorough understanding of the frequency-domain analysis process is necessary if the results the are to be interpreted correctly.

Simulation Method for Frequency Analysis


Frequency analysis using VBASE yields the small signal frequency response. When performing a simulation the program first locates the DC convergence point. It then linearizes non-linear circuit elements about the point of convergence and then performs an idealized small-signal frequency-analysis on the now-linearized circuit. In normal operation the user will allow the simulator to find the initial starting conditions for both timeand frequency-domain simulations. In this case the simulator uses certain rules to find the starting point for all the node voltages and the selected currents. Capacitors are all open-circuited, inductors are all short-circuited and resistors are left alone. A modified nodal approach (MNA) system matrix, Jacobian matrix, stimulus vector and initial guess vector are all created and an iterative technique, similar to the Newton Raphson algorithm, is used to find the DC convergence point. At this stage any diodes or transistors can be represented by admittances and controlled sources. The capacitor and inductor values for all the non-linear circuit elements (diodes, transistors etc.) can now be calculated using the node voltages and selected branch currents. A linear circuit with fixed capacitors, inductors, resistors and sources is obtained and it is this circuit that is used for small-signal frequency analysis. Frequency-analysis simulation is performed by using mathematical manipulation of the capacitor, inductor and resistor values. Gain, due to controlled sources (linearized transistors reduce to resistors, capacitors and controlled sources) is taken into account as well. Note that frequency-analysis is not performed by applying time-domain signals to the circuit and analyzing the signal amplitudes and phases at each node. No account is taken of the amplitude of the signal because in a linearized circuit, input signal amplitude is irrelevant to the frequency response or gain characteristics. The simulator will allow the gain and phase of the stimulus signal or signals to be varied. The default amplitude of the stimulus is one unit (note - not one volt). If the stimulus is increased to two units the effect is to add 6.02dB to the gain graph. No change to the shape of the characteristic will occur except for the shift in the gain, likewise a change in the phase of the stimulus simply shifts the phase of the results.

Frequency-Domain Analysis 121

Performing Frequency Analysis


Breaking the Feedback Loop
To determine the stability of a power supply it is necessary to break the feedback-loop, inject a signal at a point just passed the break, and trace the signal back to before the break. Figure 12-1 outlines a typical switching power supply.

Figure 12-1: Control Diagram for Voltage Mode SMPS

The point Y before the break corresponds with the CNTL output of the state-averaged IC models. The point X after the break corresponds to the CNTL input of the state-averaged power supply topology block in use. In order to facilitate an easy method to break the feedback loop, a resistor can be added to the simulation schematic at the position where the break is to be made. The convention in this manual is to call the resistor RBKLOOP (for Resistor BreaK LOOP). The resistor should always be added to the circuit in a position where it will not have any effect during normal time-domain operation when the loop is closed. If resistor RBKLOOP is placed between the points X and Y as shown in the example of Figure 12-2, the above condition is satisfied because in normal operation the output impedance of the control IC at point Y (pin CNTL) is 0ohm and the input impedance of the power supply block at input CNTL (point X) is 1Gohm. Since virtually no current will flow through the resistor, a 1ohm resistor has no effect on circuit operation.

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Figure 12-2: Flyback Circuit

Determination of Frequency-Source Bias Voltage


Having designed the circuit and set up the parameters of the load and SMPS topology-block, the next stage is to run the power supply in frequency domain with the feedback loop broken. To do this the power supply must be running in linear mode, in other words, the operational amplifier in the control IC should be in the active region and not saturated to either the high or low limit. If the system has a high DC gain, which is the case with most high performance power supply designs, a very small change in the power supply output voltage will have a large effect on the operational amplifier output voltage. Just a few tens of microvolts of change in the output voltage of the supply may cause the opamp output to swing from rail to rail. To perform frequency analysis it is necessary to determine the duty cycle when the supply is operating in steady-state. Using the SOURCES dialog, a 0V voltage source should be added to point X (the right hand side of RBKLOOP). The voltage on this supply will be swept using the DCsweep feature of the simulator and its value will be set later, therefore the voltage attributed to it in the Sources dialog is irrelevant. The voltage at point X will be swept from a voltage numerically less-than, to a voltage numerically greater-than, the steady-state duty-cycle. To do this, first click on the DC Analysis icon in VBA and select the source connected to point X. The next step is to fill in the sweep range. It is important that the sweep range is selected to encompass the point of steady-state operation. The intention is to home-in on the steady-state operating point. The expected steady-state duty-cycle should be calculated and a voltage numerically equal to this should form the center of the sweep range. The first sweep should typically extend from 0.1V less than the calculated value to 0.1V above it. The step size in the DC dialog should be set so that there are approximately 200 steps over the sweep range.The simulation should now be run and on completion the voltages on points X and Y in Figure 12-2 should be brought up in an AWD window.

Frequency-Domain Analysis 123

The setup file for this test is stored in the FB directory of the design aid and is called DCsweep1.vas. The voltage where the X and Y voltages cross represents the steady-state operating duty-cycle, in this case in the range between 481mV and 482mV. This is not accurate enough for our needs and so a further simulation over the sweep range 481mV to 482mV will be performed (setup file DCsweep2.vas). Figure 12-3 shows the results at the cross-over voltage.

Figure 12-3: DCsweep Showing Crossover at 0.48127

This shows that the steady-state duty-cycle is between 0.48126 and 0.48127. Either of those values should be recorded for entry later in the frequency-domain set-up dialog. Do not rely on the Marker function available as an option in the AWD. The marker will not give the required level of accuracy. Always set the increment in the DC analysis small enough so that you obtain at least one simulation point located in the active region. The V(x) value for this point guarantees that the whole system will operate in active mode. Another, much simpler, way to determine the steady-state voltage V(x) is to perform DC operating point analysis for a closed loop circuit. The setup for this analysis is stored in the DC.vas file. The start value of the Vcntl source should be set properly to perform the operating point analysis for load conditions at which you want the frequency analysis to be performed. In the test case, it is 5A at 5V on output (Vcntl = 0). The result may be found using Reports dialog for Operating Point. The V(x) in our case is reported as 481.265mV, which is consistent with the DCsweep2 analysis. Even simpler is to look for V(x) in starting point node voltages in tran.apo, if transient analysis was performed previously. In the test case, V(x) is reported as 0.4813V, because for default settings, only four significant digits are reported. To get better accuracy, change the Significant Digits in the Settings dialog. Note that the starting point was calculated for starting point load conditions, and the same load conditions must be used in the frequency analysis. A number of positions in the loop are possible candidates for incorporating a break. The position between the control IC and the SMPS topology-block was chosen because the voltage at this is always in the region 0 to 1V. The stimulus source used to inject a signal into the circuit to perform frequency-analysis requires a DC voltage offset to make the supply run at the correct output voltage.

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Frequency-Domain Simulation
Having accurately determined the duty-cycle at steady-state, the voltage source applied to point X using the Sources dialog in VBA must be set to the voltage V(x) obtained earlier. The setup file freq.vas in any of the power supply demonstration directories in the design aid will show this process. The load resistance should be set by using the SM_LOAD macromodel (see Chapter 17) and the control voltage Vcntl set to values at which the steady-state V(x) was calculated. It is important to note that the useful frequency range of the simulation only extends up to half the switching frequency. At higher frequencies the Bode plot results will not accurately reflect circuit operation. It is, however, important that the circuit does not go unstable at high frequency otherwise the state-averaged time-domain simulation will not converge. This condition does not usually present a problem, but must be considered when adding compensation.

Simulate VBA
Figure 12-4 shows the Open Loop Bode plot for the flyback demonstration circuit.

Figure 12-4: Open-Loop Bode Plot

The phase- and possibly the gain-margin can be read off the Bode plot if the simulation has progressed properly. Figure 12-4 only shows the phase margin. An indication of correct simulation is that the gain of the system varies from typically 50 to 100dB, tailing off at higher frequency to a much lower gain, normally less than 0dB. If the whole gain curve is at a very low level, typically -50dB or lower, it is likely that the bias point was not entered accurately enough in the frequency dialog, and the op-amp in the control IC is saturated to one or other of the rails. If this happens, a more accurate value for the duty-cycle should be obtained by performing the actions in the "Determination of Frequency-Source Bias Voltage" section again, but this time taking care to obtain the results more accurately. Compensation components can be varied using the Property Override dialog in VBA and simulations can then be re-run to determine the effect of the changes. When satisfactory gain and phase margins have been obtained, you can progress to time domain simulation to assess the transient response of the circuit. Often it will not be possible to obtain the gain margin because the phase will not get to 180

Frequency-Domain Analysis 125

degrees before half the switching frequency, above which the results are not meaningful, however, the phase margin can always be obtained. It is not always measured exactly at the point where the gain is 0dB. As well as the compensation components, the series resistance and inductance (ESL and ESR) of the output reservoir capacitors are responsible for the zeros introduced at high frequency. In fact a change in the values of these components usually has a large effect on the frequency-domain characteristics of the circuit. A lot of the work of designing a compensation network will be involved with dealing with the zeros introduced by the capacitor parasitics. It is, therefore, important that the parasitic elements are included as accurately as possible.

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Chapter 13 IC Model Description

This chapter describes the process used to produce state-averaged models of the controller integrated circuits available in the switched-mode power supply design tool.

Pulse Width Modulator Control Integrated Circuits


The schematic diagram of a typical regulating pulse width modulator control integrated circuit (in this case the SG3524) is shown in Figure 13-1. It can be seen that the control circuit contains a linear stage comprising the error amplifier and associated circuitry, and a switching stage which controls the output transistors. The state-averaging process involves the removal of the switching circuitry and simplification of the linear stage while retaining the overall transfer characteristic of the device. Refer to Chapter 1 for a full description of the state-averaging process.

Figure 13-1: Schematic Diagram of SG3524 Courtesy of Silicon General

IC Model Description 131

IC Model Description The state-averaged model of the control circuit has all switching components and the current limit amplifier removed. The block diagram of the state-averaged SG3524 is shown in Figure 13-2.

Figure 13-2: Block Diagram of State-Averaged SG3524

The error amplifier is simplified and only models the parameters of importance to circuit operation. The amplifier is pre-configured to give the correct output impedance, gain and gain-bandwidth product, ensuring that the compensation terminal has the correct characteristics. The shutdown circuitry is modeled and will function as on the real device. A block labeled Duty Cycle Calculator is fed with the output signal from the error amplifier and is used to calculate the duty cycle for any given set of input conditions. The output of the state-averaged model is a signal named CNTL representing the duty cycle. For convenience this signal was chosen to give 1V for 100% duty cycle and 0V for 0% duty cycle, and was linearly interpolated for other duty cycles. Each control circuit model has an input pin labelled DUT_LIM, and external voltage in the range 0 to 1V (referenced to GND) may be applied to this pin to limit the maximum duty cycle available. The maximum duty cycle of the circuit should be determined by reference to the manufacturers datasheet for the control circuit being used. The state-averaged control integrated circuits available in the VeriBest design tool all follow the format described for the SG3524. The configurable parameters and functional differences will be described in the following chapters

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Chapter 14 SG3524 Model

The state-averaged model of the SG3524 regulating pulse width modulator is based on data obtained from the Silicon General Product Catalog 1990 and measurements made on real devices. The model is suitable for simulating power supplies with voltage feedback loops. It is unsuitable for current mode control.

Figure 14-1: Graphic Symbol

The output terminal CNTL produces a voltage between 0V and 1V relative to the datum mode GND (not the GROUND terminal on the SG3524 block which may or may not be connected to GND). The voltage represents a value numerically equal to the required switching duty cycle. The CNTL terminal is compatible with the CNTL input provided on the various power supply topology models described in Chapters 2 through 7. The input terminal DUT_LIM is used to limit the maximum duty cycle output from the control circuit. For example, in power supply designs where only one output from the control circuit is used, the maximum duty cycle must be set to less than 50%. This is achieved by applying a 0.5V supply (relative to GND) to the DUT_LIM terminal. The terminal EOUT represents the compensation terminal on the real device. The amplifier has the correct output impedance and frequency characteristics and may be compensated as shown in the manufacturers datasheet. The Bode plot of the amplifier is shown in Figure 14-2.

SG3524 Model 141

SG3524 Model

Figure 14-2: Error Amplifier Bode Plot Phase Gain

The GROUND terminal may be floated. The terminals INV and NINV are the inputs to the error amplifier. They have the correct input impedance, but bias- and offset-currents and input offset voltage are not modeled. Input common-mode range exceeds that of the real device. Care should be taken to ensure that the input common mode range does not exceed the device manufacturers specification. The terminal SHDWN is the shutdown terminal and operates as on the real device. The VREF terminal provides a voltage reference output which may be adjusted using the parset file. Note that this voltage has zero output impedance and is provided only for convenience in circuit connection. No attempt has been made to model characteristics of the reference supply apart from the reference voltage.

Setting Parameters
The parameters of the SG3524S model can be modified using the VeriBest Analog Model Library Manager. The following table shows a list of the parameters and their meanings. DEADBAND GAIN GBW ROUT VREF Maximum duty cycle=(1-DEADBAND)x100% Open-loop gain of the error amplifier Gain-bandwidth product of the error amplifier Output resistance of the error amplifier Reference voltage at the VREF terminal

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Chapter 15 SG3525 and SG3527 Models

The state-averaged models of the SG3525 and SG3527 regulating pulse width modulators are based on data obtained from the Silicon General Product Catalog 1990 and measurements made on real devices. From the users point of view, operation of the two models is identical. The instructions below refer to the SG3525 but the SG3527 may be substituted at any stage. The model is suitable for simulating power supplies with voltage feedback loops. It is unsuitable for current mode control.

Figure 15-1: Graphic Symbol

The output terminal CNTL produces a voltage between 0V and 1V relative to the datum mode GND (not the GROUND terminal on the SG3525 block which may or may not be connected to GND). The voltage represents a value numerically equal to the required switching duty cycle. The CNTL terminal is compatible with the CNTL input provided on the various power supply topology models described in Chapters 2-7. The input terminal DUT_LIM is used to limit the maximum duty cycle output from the control circuit. For example, in power supply designs where only one output from the control circuit is used, the maximum duty cycle must be set to less than 50%. This is achieved by applying a 0.5V supply (relative to GND) to the DUT_LIM terminal. The terminal EOUT represents the compensation terminal on the real device. The amplifier has the correct output impedance and frequency characteristics and may be compensated as shown in the manufacturers datasheet. The Bode plot of the amplifier is shown in Figure 15-2.

SG3525 and SG3527 Models 151

Figure 15-2: Error Amplifier Bode Plot

The GROUND terminal may be floated. The terminals INV and NINV are the inputs to the error amplifier. They have the correct input impedance, but bias- and offset-currents and input offset voltage are not modeled. Input common-mode range exceeds that of the real device. Care should be taken to ensure that the input common mode range does not exceed the device manufacturers specification. The terminals SHDWN and START are the shutdown and soft-start terminals respectively and operate as on the real device. The VREF terminal provides a voltage reference output which may be adjusted using the parset file SG3525S. Note that this voltage has zero output impedance and is provided only for convenience in circuit connection. No attempt has been made to model characteristics of the reference supply apart from the reference voltage.

Setting Parameters
The parameters of the SG3525S model can be modified using the VeriBest Analog Model Library Manager. Model Parameters Meanings DEADBAND GAIN GBW ROUT VREF Maximum duty cyle=(1-DEADBAND)X100% Open-loop gain of the error amplifier Gain-bandwidth product of the error amplifier Output resistance of the error amplifier Reference voltage at the VREF terminal

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For details on the use of this model for frequency- and time-domain simulation, refer to the appropriate chapter for the power supply topology being used.

SG3525 and SG3527 Models 153

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Chapter 16 TL494 Model

The state-averaged model of the TL494 regulating pulse width modulator is based on data obtained from the Texas Linear Circuits Data Book Volume 3, 1989 and measurements made on real devices. The model is suitable for simulating power supplies with voltage feedback loops. It is unsuitable for current mode control. Features of the model are as follows.

Figure 16-1: Graphic Symbol

The output terminal CNTL produces a voltage between 0V and 1V relative to the datum mode GND (not the GROUND terminal on the TL494 block which may or may not be connected to GND). The voltage represents a value numerically equal to the required switching duty cycle. The CNTL terminal is compatible with the CNTL input provided on the various power supply topology models described in Chapters 2-7. The input terminal DUT_LIM is used to limit the maximum duty cycle that is output from the control circuit. For example, in power supply designs where only one output from the control circuit is used, the maximum duty cycle must be set to less than 50%.This is achieved by applying a 0.5V supply (relative to GND) to the DUT_LIM terminal. The terminal EOUT represents the compensation terminal on the real device. The amplifier has the correct output impedance and frequency characteristics. The Bode plot of the amplifier is shown in Figure 16-2.

TL494 Model 161

Figure 16-2: Error Amplifier Bode Plot

The GROUND terminal may be floated. The terminals INV1, NINV1, INV2 and NINV2 are the inputs to the error amplifiers. They have the correct input impedance, but bias- and offset-currents are not modeled. Input common-mode range exceeds that of the real device. Care should be taken to ensure that the input common mode range does not exceed the device manufacturers specification. Note that the TL494 works in the opposite sense to the other control integrated circuits included with the design tool. An increase in the output of the error amplifier (the EOUT terminal) causes a decrease in duty cycle at the CNTL output. The VREF terminal provides a voltage reference output which may be adjusted using the parset file TL4945. Note that this voltage has zero output impedance and is provided only for convenience in circuit connection. No attempt has been made to model characteristics of the reference supply apart from the reference voltage.

Setting Parameters
The parameters of the TL494S model can be modified using the VeriBest Analog Model Library Manager.. Model Parameters Meanings DEADBAND SLEW GAIN GBW VREF Maximum duty cyle=(1-DEADBAND)X100% Slew-rate of the error amplifier Open-loop gain of the error amplifier Gain-bandwidth product of the error amplifier Reference voltage at the VREF terminal

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Chapter 17 Ancillary Devices

This chapter describes the ancillary components, resistive load model, power supply failure model, opto-coupler, op-amp, and isolation buffer models, provided with the switched-mode power supply design tool.

Load Model
The device SM_LOAD is provided to allow the effect of resistive load change to be investigated. The input terminal CNTL is used to vary the load resistance between the two values set by the voltage and currents specified in the parset file. The voltage on this terminal should be set to 0V representing the high load resistance or 1V representing the low load resistance. As the voltage on the CNTL terminal changes, the load resistance changes in proportion. At all times the load presented to the power supply is purely resistive.

Figure 17-1: Graphic Symbol

Before starting a simulation, the parameters of the SM_LOAD model must be set. This is achieved by modifying the parset SM_LOAD using VeriBest Analog Model Library Manager. Model Parameters Meanings V I1 I2 Notes: 1. The load resistances set are calculated by V/I1 and V/I2. If the output voltage of the supply varies from V then the currents will be proportionally different from I1 or I2. 2. I1 must be less than I2. Failure to observe this condition will cause non-convergence. Output voltage of power supply Load current when CNTL pin is at 0V Load current when CNTL pin is at 1V

Ancillary Devices 171

Power Supply Failure Model


The device V_FAIL is provided to allow the effect of input voltage failure to be investigated.

Figure 17-2: Graphic Symbol

The terminal VOUT produces the supply voltage until the time specified in the parset file at which point the supply becomes open circuit. The terminal GROUND should be connected to the appropriate ground or supply return in the circuit being simulated.

Setting Parameters
Before starting a simulation, the parameters of the V_FAIL model must be set. This is achieved by modifying the parset V_FAIL using the VeriBest Analog Model Library Manager. The following is a list of the parameters and their meanings. Model Parameters Meanings V_OUT T_FAIL Output voltage of supply block Simulation time at which supply fails

Generic Opto-Coupler Models


The generic opto-coupler models supplied with the SMPS design aid allow two different types of optocoupler to be simulated. The first model has a single diode on the input side which is typical of devices such as the Harris CNY17_3. The second model has two diodes back to back on the input stage which is typical of devices such as the Harris H11AA2.

Figure 17-3: Opto-Coupler Graphic Symbols

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The input diode characteristics were obtained from measurements on typical opto-coupler devices. All three terminals of the transistor are available.

Setting Parameters
Before starting a simulation, the parameters of the opto-coupler models must be set. You achieve this by modifying the parset file of the model using the VeriBest Analog Model Library Manager. The following table lists the parameter and its meaning. GAIN Gain of device when conducting (see Note)

Note: Gain is defined as the ratio of input current to output current (that is, Iout = Iin x GAIN). SA_OPTO1 gives positive output current for positive input current. SA_OPTO2 gives positive output current for positive or negative input current.

Generic Operational Amplifier Models


The generic operational amplifier models supplied with the SMPS design aid allow two different types of operational amplifier to be simulated. The first model is a standard operational amplifier, the second is a transconductance amplifier.

Figure 17-4: Operational Amplifier Graphic Symbols

Setting Parameters
Before starting a simulation, the parameters of the operational amplifier models must be set. You achieve this by modifying the parset file of the model using the VeriBest Analog Model Library Manager. OPAMP_S Parameter Meaning SR VOUT_L VOUT_H ROUT GBW GAIN Output-voltage slew-rate in V/ s Output-voltage limit - low Output-voltage limit - high Output resistance Gain-bandwidth product Open-loop gain

Ancillary Devices 173

TCOND_S Parameter Meaning VOUT_L VOUT_H ROUT I_MAX GBW GAIN Output-voltage limit - low Output-voltage limit - high Output resistance Output-current limit Gain-bandwidth product Open-loop gain

Generic Isolation Buffer Model


The generic isolation buffer model supplied with the SMPS design aid allows a signal to be buffered.

Figure 17-5: Isolation Buffer Graphic Symbol

Setting Parameters
Before starting a simulation, the parameters of the isolation buffer model must be set. You achieve this by modifying the parset file of the model using the VeriBest Analog Model Library Manager. R_IN GAIN Input resistance Voltage gain of buffer

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Chapter 18 UC3840 Model

The state-averaged model of the UC3840 regulating pulse-width modulator is based on data obtained from the Unitrode Linear Integrated Circuits Data and Applications Handbook (April 1990). The model is suitable for simulating power-supplies with voltage feedback loops. It is also suitable for implementing circuits which require in-cycle current limiting as a form of current-mode control. Figure 18-1 shows the graphic symbol for the state-averaged UC3840 in the Design Aid library.

Figure 18-1: UC3840 Graphic Symbol

The model of the UC3840 (in Figure 18-1) differs in many ways from the practical device. Figure 18-2 shows the schematic diagram of the UC3840 (courtesy of Unitrode). The parts of the diagram enclosed within the dotted boxes are ancillary to normal operation of the device and have not been modeled. All other circuitry has been state-averaged or modeled.

UC3840 Model 181

UC3840 Model

Figure 18-2: Schematic Diagram of Unitrode UC3840

The CNTL terminal replaces the PWM output terminal on the practical device. CNTL is implemented as a controlled voltage source with an output voltage numerically equal to the duty-cycle from the UC3840. This terminal is compatible with the CNTL input terminals on the SMPS topology blocks and has zero output impedance. The frequency of operation of the state-averaged UC3840 must be set by connecting a voltage source to the F_IN terminal. This voltage, which must be connected between F_IN and system ground (node 0 in the netlist) should be 1V for every 10 kHz of switching frequency, that is, to operate at 50 kHz, the voltage on F_IN should be 5V with respect to GND (node 0 of the netlist). The ramp setting components RR and CR are modeled as part of UC3840 model (see Figure 18-1). These components determine the slope of the ramp that would be generated in a practical circuit. The components CR and RR are set using the VeriBest Analog Model Library Manager to edit the UC3840S parset. The CS (Current Sense) terminal operates in a similar fashion to that on the practical device. Each of the current-mode SMPS topology blocks has an output terminal IPK giving the peak cycle-by-cycle input-inductor current. This terminal must be connected to the CS terminal. The CLT (Current Limit Threshold) terminal operates in a similar way to its namesake on the practical device. Should the voltage on CS exceed that on the CLT terminal, then the duty-cycle output CNTL will be limited. In the case of this state-averaged model, the comparator is replaced by a high-gain

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amplifier and the control mechanism is such that the duty-cycle will be progressively reduced as the voltage on CS approaches the voltage on CLT. This reduction only occurs when the voltages are very close. In effect, a negative feedback circuit is formed and the voltage measured at CS (proportional to the peak current) will tend to track the voltage on the CLT terminal. In this mode of operation, the circuit is operating in current mode control. See the demonstration circuit for the current-mode boost converter for more explanation of the operation of the CS and CLT terminals. The VREF terminal is a fixed and constant 5V reference with respect to the GROUND terminal. The COMP terminal models the compensation terminal on the real device. The amplifier has the correct output impedance and frequency characteristics and may be compensated as shown in the manufacturers datasheet. The Bode plot of the modeled amplifier is shown in Figure 18-3.

Figure 18-3: Error Amplifier Bode Plot

The INV and NINV terminals correspond to the error-amplifier inverting and non-inverting inputs respectively. Both have the correct input impedance but the bias and input-offset currents and input offset voltage are not modeled. Input common-mode range exceeds that of the real device and care should be taken to ensure that, in the simulated circuit, these terminals are operated within the device manufacturers specified limits to ensure accurate results. The graphic symbol for the UC3840 includes a capacitor (CR) connected between the RAMP and GROUND terminals. The voltage on the RAMP terminal represents the ramp signal voltage at the moment that the switching-pulse is terminated. No conventional saw-tooth ramp signal is available from this state-averaged model. The signal from the RAMP terminal can be used to provide slope compensation if the device is operated as a current-mode controller. The ground terminal on the UC3840 state-averaged model may be floated, but it is advisable to connect it to the simulation ground (node 0) if possible as this allows the op-amp to operate with optimal accuracy.

UC3840 Model 183

UC3840 Model The F_OUT terminal is an output that is designed to be connected to the state-averaged currentmode Boost converter. The terminal is internally connected to the F_IN terminal and facilitates easy connection between the controller model and certain topology blocks. The VSENSE terminal is connected to resistor RR which is part of the model. The value of RR, just as with CR, may be set using the VeriBest Analog Model Library Manager dialog. The terminal at the top of RR must be connected to a positive supply rail. This voltage determines the slope of the internal oscillator ramp on the practical device. The characteristics of the ramp are calculated for use internally by the state-averaged UC3840; this is the reason the values of RR and CR are entered as parameters in the parset UC3840S of the model and not added externally. Note that no appreciable current flows through resistor RR because the input characteristics of this terminal are not modeled.

Slope Compensation
The UC3840 controller is designed to be used as a voltage-mode controller with over-current protection. It can be used as a current-mode controller, in which case slope-compensation is often necessary. Slope compensation can be implemented by connecting a resistor between the RAMP terminal and the CS terminal. A further resistor must then be connected between the CS terminal and the IPK terminal of the SMPS topology block. The ratio of these two resistors, the slope of the ramp defined by RR, CR, and VSENSE, and the value of the sense resistor in the SMPS topology block, define the amount of slope compensation applied. Ramp compensation is used to change the control strategy from one of controlling the peak current, to one of controlling the average output current. This is performed by adding a slope component to the sensed inductor current signal. Mathematically, the slope of the compensating ramp must be greater than one-half of the downslope of the input current waveform. The only time during the switching cycle that slope-compensation has an effect is at the instant of termination of a switching pulse. The voltage of the internally generated ramp signal inside the UC3840 at this instant is the voltage present on the RAMP terminal of the UC3840 state-averaged model. Note that the minimum output voltage from the RAMP terminal is 0.5V which is the ramp trough value. The component values used to implement ramp compensation should be the same as those used in a practical circuit. A good reference on ramp compensation techniques is the UNITRODE Linear Integrated Circuits handbook and the UNITRODE Power Supply Design Seminar book. The RAMP output terminal provides a voltage Vramp that is defined as follows:
V ramp = 0.5 + ( V pr 0.5 )

V sense V pr = ----------------HR CR F

where VPR is the peak ramp voltage, F is the operating frequency, is the duty-cycle, and Vsense is the sense voltage (at the upper connection on RR).

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Chapter 19 UC3842 and UC3844 Models

The state-averaged models of the UC3842 and UC3844 regulating pulse-width modulators are based on data obtained from the Unitrode Linear Integrated Circuits Data and Applications Handbook (April 1990) and on practical device measurements. The output terminal CNTL on the UC3842 produces a voltage between 0V and 1V, the CNTRL terminal on the UC3844 produces a voltage between 0V and 0.5V, both relative to the datum mode GND (not the GROUND terminal on the model block which is not necessarily connected to GND). The voltage is numerically equal to the switching duty cycle. The CNTL terminal is compatible with the CNTL input provided on the power supply topology models described in Chapters 10 and 11.

Figure 19-1: Graphic Symbols

The terminal COMP represents the compensation terminal on the real device. The amplifier has the correct impedance and frequency characteristics and may be compensated as shown in the manufacturers data sheet. The Bode plot of the amplifier is shown in Figure 19-2.

UC3842 and UC3844 Models 191

UC3842 and UC3844 Models

Figure 19-2: Error Amplifier Bode Plot

The terminals IPK, ITR, and ISL are used to transfer information from the various power supply topology modes to the control IC block. For any duty cycle, IPK and ITR represent the voltage developed across RSENSE when the inductor is conducting peak and trough switching currents respectively. ISL represents the rate of change of inductor current when the switch is conducting (1V per amp/second). The terminal FREQ_OUT is used to transfer information about the operating frequency from the control IC model to the topology block. The frequency is represented by a voltage of 1V/10kHz. The control IC has a frequency parameter in the parset file. The GROUND terminal may be allowed to float. The terminal VFB is one of the inputs to the error amplifier. It has the correct input impedance, but bias- and offset-currents and input offset voltage are not modeled. Input common-mode range exceeds that of the real device. The VREF terminal provides a voltage-reference output which may be adjusted using the parset file UC3842_S or UC3844_S. Note that this voltage has zero output impedance. No characteristics of the reference supply apart from the voltage have been modeled.

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Chapter 20 UC3846 Model

The state-averaged models of the UC3846 regulating pulse-width modulator is based on data obtained from the Unitrode Linear Integrated Circuits Data and Applications Handbooks (April 1990) and on practical device measurements.

Figure 20-1: Graphic Symbols

The current limit amplifier input pins are not present on the model. The voltages present on the IPK, ITR, and ISL pins allow the effect of the current sense amplifier to be calculated internally. The GROUND terminal on the topology block in use must be connected to the GND terminal so that the effect of the current sense resistor can be calculated. The output terminal CNTL produces a voltage between 0V and 1V relative to the datum note GND (not the GROUND terminal on the UC3846 block which is not necessarily connected to GND). The voltage is numerically equal to the switching duty cycle. The CNTL terminal is compatible with the CNTL input provided on the power supply topology models described in Chapters 10 and 11. The terminal COMP represents the compensation terminal on the real device. The amplifier has the correct output impedance and frequency characteristics and may be compensated as shown in the manufacturers data sheet. The Bode plot of the amplifier is shown in Figure 20-2.

UC3846 Model 201

UC3846 Model

Figure 20-2: Error Amplifier Bode Plot

The terminals IPK, ITR, and ISL are used to transfer information from the various power supply topology models to the control IC block. For any duty cycle, IPK and ITR represent the voltage developed across RSENSE when the inductor is conducting peak and trough switching currents respectively. ISL represents the rate of change of inductor current when the switch is conducting (1V per amp/microsecond). The terminal FREQ_OUT is used to transfer information about the operating frequency from the control IC model to the topology block. The frequency is represented by a voltage of 1V/10kHz. The control IC has a frequency parameter in the parset file (UC3846_S). The GROUND terminal may be allowed to float. The terminal VFB is one of the inputs to the error amplifier. It has the correct input impedance, but bias- and offset-currents and input offset voltage are not modeled. Input common-mode range exceeds that of the real device. The VREF terminal provides a voltage-reference output which may be adjusted using the parset file. Note that this voltage has zero output impedance. No characteristics of the reference supply apart from the voltage have been modeled.

Setting Parameters
Before starting a simulation, the parameters of the UC3846 model must be set. You achieve this by modifying the UC3846_S parset file of the model. F VREF Operating frequency of the control IC Reference voltage at the VREF terminal

DUT_LIM Maximum duty-cycle required SLCOMP Slope compensation value (see Note)

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Note: Slope compensation is calculated as a proportion of the amplitude of the voltage ramp resulting from applying the current ramp signal across the current sense resistor (that is, Slope compensation voltage = SLCOMP x (CP - CT) x RSENSE, where CP and CT are the applied voltages to the Peak and Trough current input pins).

UC3846 Model 203

UC3846 Model

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Chapter 21 AC Supply Failure Model

The device V_FAIL3 provides a simple method for the investigation of input supply failure on the simulated SMPS circuit. Simulation of brown-outs or the complete failure of the input supply may be performed. The device has built-in series inductance and resistance which can be used to simulate the effect of the mains source impedance. The block produces a sinusoidal output which is designed to be connected to the SMPS input rectifier stage.

Figure 21-1: Voltage Failure Block Graphic Symbol

Features of the model are as follows: The output from the block appears across the GROUND and VOUT pins. Note that the GROUND pin may be floated and is not connected to the simulation node GND. The MONITOR pin is used to view the voltage being supplied to the circuit. The voltage on this pin is referenced to the simulation node GND providing a convenient way of displaying the input voltage.

Setting Parameters
Before starting a simulation, the parameters of the voltage failure module must be set. You achieve this by modifying the V_FAIL parset file using the VeriBest Analog Model Library Manager. The following table shows a list of the parameters and their meanings. Note that peak voltages are used to specify the output during normal and failed operation. The parameter V_LOW may be set to zero to simulate total supply failure. A series impedance is included in each output connection of the generator and the parameters R and L apply to each impedance. V_OUT F T_FAIL D_FAIL Output voltage of sine wave (peak) Frequency Time at which supply will fail Duration of supply failure

AC Supply Failure Model 211

AC Supply Failure Model V_LOW R L Output voltage of sine wave during failure (peak) Series resistance of supply block Series inductance of supply block

Operation of the Power Supply Failure Block


A simple example circuit using the power supply failure block is shown in Figure 21-2. The block is shown connected to a bridge rectifier, capacitor, and resistive load. The example illustrates the effect of a temporary reduction in supply voltage.

Figure 21-2: Example Supply Fail Circuit

Time-domain simulation was performed with the parameters of the supply fail block set to their default values as shown in the following table. V_OUT F T_FAIL D_FAIL V_LOW R L 339V 50Hz 40ms 20ms 200V 60mohm 50uH

The results from the simulation are shown in Figure 21-3. The two waveforms shown are the voltage at the monitor pin and the voltage across the capacitor.

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Figure 21-3: Simulation Results

AC Supply Failure Model 213

AC Supply Failure Model

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Index

Index
A AC Supply Failure Model 21-1 Features 21-1 Operation of the Power Supply Failure Block 21-2 Output Terminal 21-2 Setting Parameters 21-1 Voltage Failure Block Graphic Symbol 21-1 Ancillary Devices 17-1 Generic Opto-Coupler Models 17-2 Load Model 17-1 Power Supply Failure Model 17-2 B Boost Circuit 2-4 Boost Converter 2-1 Frequency-Domain Simulation 2-7 Input Terminal 2-2 Operation of the Boost Topology-Block 2-3 Output Terminal 2-2 Setting Parameters 2-2 Terminal GROUND 2-2 Time-Domain Simulation 2-3 BOOST_CM 11-5 Buck (un-isolated step-down) converter. 1-3 Buck Converter 4-1, 6-1 Effect on Frequency Response of Variations in Duty-Cycle 4-7 Input Terminal 4-2 Measured Transient Response 4-5 Open-Loop Test Circuit 4-7 Output Terminal 4-2 Setting Parameters 4-2 Time-Domain Simulation 4-3 Buck-Boost Converter 3-1, 5-2 Frequency-Domain Simulation 3-7 Input Terminal 3-2 Measured Transient Response 3-6 Open-Loop Test Circuit 3-8 Output Terminal 3-2 Peak In-Cycle Current 3-1 Setting Parameters 3-2 Simulated Transient Response 3-7 Switch Resistance 3-2 Time-Domain Simulation 3-3 Buck-Boost Topology-Block 3-3 Parameters 3-4 C C ukConverter 7-1 Continuous Current Mode 3-1 continuous current mode 2-1

Control Diagram for Voltage Mode SMPS 12-2 Convergence Problems 2-3, 3-3 convergence problems 4-2, 5-4 Converter Topologies 1-6 Cuk Converter Description 7-1 Frequency-Domain Simulation 7-7 Input Terminal 7-3 Open-Loop Test Circuit 7-7 Output Terminal 7-3 Parameters 7-3 Restricted Operation 7-2 Time-Domain Simulation 7-4 Current_Mode Control Terminals 8-2 Current-Mode Boost Converter 11-1 Additional Terminals 11-3 Frequency-Domain Simulation 11-10 Graphic 11-1 Input Terminal 11-2 Load Resistance 11-7 Ouput Terminal 11-3 Output Voltage for Transient Load Change 11-6 Output Voltage vs Duty-Cycle 11-4 Setting Parameters 11-3 Simple Test Circuit 11-4 Simulations 11-3 Time-Domain Simulation 11-5 Voltage Divider 11-9 Current-Mode Control 8-1 Cycle-By-Cycle 8-1 Ramp-Compensation Factor 8-4 Simplified Boost Circuit 8-1 Slope Compensation 8-3 Voltage-Mode Control with In-Cycle Current Limit 8-2 D DC Sweep Showing Crossover at 0.48127 12-4 Dcsweep1.vas 12-4 DCsweep2.vas 12-4 demonstration circuits 1-2 DIABLO 1-1, 7-1 Discontinuous Current Mode 3-1 discontinuous current mode 2-1 Document Organization 1-1 Duty-Cycle Calculator 13-2 E effective series resistance (ESR) 1-5 F f3op 10-1 FB30P Parset 10-3 Features and Limitations of the Models 1-5

VeriBest Switched-Mode Power Supply Design Manual Index1

Index Flyback Circuit 5-5, 12-3 Flyback Converter 5-1 Catch winding 5-1 Continuous Current Mode 5-2 Coupling Coefficients 5-1 DC Convergence 5-4 Discontinuous Current Mode 5-2 Frequency-Domain Simulation 5-8 Input Terminal 5-3 Input Windings 5-1 Output Terminals 5-3 Output Windings 5-1 Setting Parameters 5-4 Simulated Transient Response 5-7 Time-Domain Simulation 5-5 Fly-Back Converters Examples 5-2 Forward Converter 6-1 Effect on Frequency Response of Variations in Duty-Cycle.1.0 0.1 6-6 Fast Load Switching Transitions 6-2 Frequency-Domain Simulation 6-5 Input Terminals 6-2 Output Terminals 6-2 Setting Parameters 6-2 Time-Domain Simulation 6-3 freewheel diode 1-3 freq.vas 9-7 Frequecy-Domain Analysis Open-Loop Bode Plot 12-5 Frequency Analysis Performing 12-2 Breaking the Feedback Loop 12-2 Frequency-Doamin Analysis Compensation Components 12-5 Frequency-Domain Analysis 12-1 DC Convergence Point 12-1 ESL 12-6 ESR 12-6 Gain Margin 12-5 Performing Frequency Analysis 12-2 Phase Margin 12-5 Simulate VBA 12-5 Simulation Method for Frequency Analysis 12-1 Frequency-Domain Simulation 2-7, 3-7, 9-6, 12-5 Frequency-Domain Simulation for MultipleOutput Forward Converter 10-11 Frequency-Source Bias Voltage Determination 12-3 G GEAR Integration 3-3, 5-4 GEAR Integration Method 2-5 Generic Isolation Buffer Model 17-4 Setting Parameters 17-4 Generic Operational Amplifier Models 17-3 Setting Parameters 17-3 Generic Opto-Coupler Models 17-2 Setting Parameters 17-3 GMIN Value 5-4 H Hints and Tips 1-2 I IC Model Description 13-1 Error Amplifier 13-2 Shutdown Circuitry 13-2 ilicon General SG3524 3-3 Introduction and the State Averaging Process 11 Document Organization 1-1 SMPS Design 1-1 Isolation Buffer Graphic Symbol 17-4 L LeCroy Digitizing Oscilloscope 2-4, 3-4 Loop Stability 4-6 M m_fwrd 9-1 Directory 9-4 MARKER Function 12-4 mean output voltage 1-4 Measured Transient Response 2-6 Multiple-Output Flyback Converter 10-1 Additional Terminals 10-3 Continuous Current Modes 10-1 Demonstration Power-Supply 10-4 Discontinuous Current Modes 10-1 Frequency-Domain Simulation 10-11 Graphic Symbol 10-2 Input Terminal 10-2 Output Terminals 10-3 Output Windings 10-1 Parameters 10-5 Schematic 10-5 Setting Parameters 10-3 Slope Compensation 10-6 Time-Domain Simulation 10-4 Multiple-Output Forwaed Converter Time-Domain Simulation 9-4 Multiple-Output Forward Convereter Frequency-Domain Simulation 9-6 Multiple-Output Forward Converter 9-1

Index2 VeriBest Switched-Mode Power Supply Design Manual

Index

Circuit Example 9-4 Input Terminals 9-1 Output Terminals 9-2 Parset File 9-1 Setting Parameters 9-2 Simulation Transient Response 9-6 N Newton Raphson Algorithm 12-1 Non-Convergence 2-3, 3-3 O Open loop Bode Plot of Buck-Boost Circuit 3-9 Open_Loop Test Circuit 2-8 Open-Loop Bode Plot for Example Power Supply Gain 6-6 Open-loop Bode Plot of Boost Circuit 2-9 Open-Loop Bode Plot of Buck Circuit Gain 4-8 Open-Loop Bode-Plots 2-7, 5-8 Open-Loop Test Circuit 6-5 Operation of the Boost Topology-Block 2-3 Operation of the Buck Topology-Block 4-2 Operation of the Buck-Boost Topology-Block 3-3 Operation of the Current-Mode Boost Topology Block 11-3 Operation of the Flyback Topology-Block 5-4 Operation of the Forward Topology-Block 6-2 Operation of the Multiple-Output Flyback Model 10-4 Operation of the Multiple-Output Forward Topology-Block 9-4 Operation of the Power Supply Failure Block 21-2 Operation of theC ukTopology-Block 7-3 Operational Amplifier Graphic Symbols 17-3 Opto-Coupler Graphic Symbols 17-2 P parasitic elements 1-2 Parasitic Resistors 3-6 Power Supply Fail 17-2 Power Supply Failure Model 17-2 Pulse Width Modulator Control Integrated Circuits 13-1 R Ramp-Compensation Factor 8-4 RBKLOOP 4-7, 5-9, 12-2 S SA_BUCK Parameters 4-4 SA_BUCK Parset 4-2 SA_CUK Parset 7-5 SA_CVK Parset 7-3 SA_FB Parset 5-4 SA_FWRD3 Parameter 9-5

Schematic Diagram of SG3524 Courtesy of Silicon General 13-1 see DIABLO 1-1 Setting Parameters 3-2 SG3524 Mode 14-1 SG3524 Model Input terminal 14-1 Output terminal 14-1 Setting Parameters 14-2 SG3525 Model 15-1 Error Amplifier Bode Plot 15-2 Input Terminal 15-1 Output Terminal 15-1 Setting Parameters 15-2 Suitability 15-1 SG3527 Mode 15-1 Silicon General Product Catalog 1990 14-1 Silicon General SG3524 2-4 Simple Boost Converter 2-1 Simple Buck Converter 4-1 Simple Forward Converter 6-1 Simulate VBA 12-5 Simulated Results from State-Averaged Buck Circuit 4-6 Slope Compensation 8-3 SM_LOAD Load-Bank 3-5 SM_LOAD load-bank. 5-7 SM_LOAD Macromodel 12-5 SM_LOAD Parameter 6-4, 9-5 SM_LOAD Parset 17-1 SMPS Design 1-1 State Averaging 1-3 State-Averaged Buck Circuit Example 4-4 State-Averaged Forward Circuit Example 6-3 State-Averaged Power Supply 2-5 State-Averaging Converter Topologies 1-6 Features and Limitations of the Models 1-5 state-Averaging Buck (un-isolated step-down) converter. 1-3 state-averaging 1-1 T Time-Domain Simulation 2-3, 3-3, 9-4 Tips 1-2 TL494 16-1 Error Amplifier Bode Plot 16-2 Input Terminal 16-1 Output Terminal 16-1 Setting Parameters 16-2 U UC3840 Model 18-1 Current Limit Threshold Terminal 18-2 Current Sense Terminal 18-2

VeriBest Switched-Mode Power Supply Design Manual Index3

Index Graphic Symbol 18-1 Ramp Settings 18-2 Schematic Diagram 18-2 Slope Compensation 18-4 UC3840 ModelF_OUT Terminal 18-4 UC3842 Model 19-1 Error Amplifier Bode Plot 19-2 Output Terminal 19-1 UC3844 Mode 19-1 UC3844 Model Error Amplifier Bode Plot 19-2 UC3846 Model 20-1 Input Terminal 20-1 Output Terminal 20-1 Setting Parameters 20-2 Slope Compensation 20-3 UC3846_S Parset File 20-2 ure Model Setting Parameters 17-2 V V_FAIL Model Parameters 17-2 V_FAIL Parset File 9-2, 11-3, 21-1 VeriBest DIABLO Behavioral Language Option 1-1 Voltage-Mode Control with In-Cycle Current Limit 8-2

Index4 VeriBest Switched-Mode Power Supply Design Manual

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