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String Technologies
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Avionics
Embedded System
Household Appliances
Microcontroller
A microprocessor plus additional peripheral support devices integrated into a single package Peripheral support devices may include:
Serial ports ( COM ), Parallel ( Ports ), Ethernet ports, A/D & D/A Interval timers, watchdog timers, event counter/timers, real time clock Other local processors ( DSP, numeric coprocessor, peripheral controller )
History of ARM
ARM- Advanced RISC Machine. The first processor in ARM family was developed at Acorn Computers Ltd between October 1983 and April 1985. Now, ARM company is considered to be market dominant in the field of mobile phone chips, due to its power saving features
ARM Families
ARM7TDMI ARM and Thumb modes ARM7M strongARM Multiple instructions Load and store instructions
ARM6 & ARM7DI ARM3 ARM2 ARM1 26 Bit Addressing 32 Bit multiplier 32 Bit coprocessor On chip cache 32 Bit addressing
Features of ARM
ARM is popular with developers due to
Thumb mode of operation. A load store architecture. Fixed length 32-bit instructions. 3-Address instruction format. Large 16 word 32 bit register file. Orthogonal instruction set. Single cycle execution and many more
Block Diagram
LPC2184
Processor Modes
ARM has seven operating modes
User FIQ IRQ Supervisor System Abort Undefined unprivileged mode under which most applications run entered, when a high priority (fast) interrupt is raised general purpose interrupt handling protected mode for the operating system
entered on reset or software interrupt instruction
privileged mode using same registers as user mode used to handle memory access violations used to handle undefined instructions
bit 0
20 16 12 8 4 0
word16
half-word14
11 7 3 10 6
half-word12
word8
byte6
2
half-word4
byte address
10
4E 9D 89
25 39 96 2B
6B< 19 6E 3C
Registers
37 registers
31 general 32 bit registers, including PC 6 status registers 15 general registers (R0 to R14), and one status registers and program counter are visible at any time when you write user-level programs
The visible registers depend on the processor mode The other registers (the banked registers) are switched in to support IRQ, FIQ, Supervisor, Abort and Undefined mode processing
Register Bank
Indicates that the normal register used by User or System mode has been replaced by an alternative register specific to the exception mode
Cond
R0 to R15 are directly accessible R0 to R14 are general purpose R13: Stack point (sp) (in common)
Individual stack for each processor mode
R14: Linked register (lr) R15 holds the Program Counter (PC) CPSR - Current Program Status Register contains condition code flags and the current mode bits 5 SPSRs (Saved Program Status Registers) which are loaded with CPSR when an exceptions occurs
R14 is used as the subroutine link register (LR) and stores the return address when Branch with Link (BL) operations are performed, calculated from the PC. Thus to return from a linked branch
MOV r15,r14 MOV pc,lr
The I and F bits are the interrupt disable bits The M0, M1, M2, M3 and M4 bits are the mode bits
Instruction Format
[Label:]
Sample Assembly Language Program add r1, r2, r3, lsl #4 sub r1, r2, r3, lsl #4 adds r1, r2, r3, lsl #4 subs r1, r2, r3, lsl #4 .end
PROGRAMMING IN C
Why C? Easier and less time consuming C is easier to modify Portability How can processor understand C language? What is Compiler & Cross Compiler?
C for Microcontrollers
Of higher level languages, C is the closest to assembly languages
bit manipulation instructions pointers (indirect addressing)
Most microcontrollers have available C compilers Writing in C simplifies code development for large projects.
Initialization
When a C program is compiled, some code is created that runs BEFORE the main program. This code clears RAM to zero and initializes your variables. Here is a segment LJMP 0003h of this code:
0003: back: ... MOV R0, #7FH CLR A MOV @R0, A DJNZ R0, back
Thank You