SATA Overview:
Serial ATA is an evolution of the parallel ATA interface that was developed for use as an interconnect for desktop PCs, servers, and enterprise systems to connect a host system to peripheral devices such as hard disk drives, optical storage drives, etc. The transition from a parallel bus interconnect to a serial interconnect was largely driven by the need for increased data transfer rates. With a 16 bit parallel data bus, issues such as signal crosstalk and skew became significant as data transfer rates. These issues are resolved by using a serial architecture with differential signals instead of a parallel bus architecture. In addition, the cabling used with a serial interconnect is less complex and is physically smaller than what is used with a 16 bit parallel bus. A 40 pin cable is required for parallel ATA connections compared to a 7 pin cable for serial ATA connections. This means that cabling used for serial connections are physically much smaller than cables for parallel connections, which allow more flexibility in system design and allow for more storage devices to reside in the same location without the concern of large bulky cabling. SATA was designed such that is software compatible with legacy parallel interconnect protocol to minimize the impact on existing operating systems when SATA is employed. SATA defines a 7-pin connector to be used for each interconnect, and SATA cables can be up to 1m in length for interconnect. See Figure 1 below for examples of connectors and cables used for serial vs. parallel ATA connections.
Figure 1: Comparison of cable and connectors for parallel and serial ATA
Note that the physical size for the cables and connectors for Serial ATA are significantly smaller that the cables and connectors for parallel ATA. SATA connectors use only 25% of the PCB space required by Parallel ATA connectors, providing additional benefits in systems with multiple drives installed. The physical data rates for SATA are 1.5 Gbps and 3.0 Gbps, with a roadmap for 6.0 Gbps operation in the future. Figures 2 and 3 below show some typical applications where SATA is used for the system interconnect.
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In a desktop application as illustrated in figure 2, the host is a PCI card installed in the PC or as part of the PC motherboard. The SATA drive(s) are connected using SATA connectors and cables. SATA drives are also used in enterprise servers and storage arrays, where multiple drives are used in each system to increase overall storage capacity. The Serial ATA protocol is used as the interconnect between the host and the drive in these systems, and communication to and from the drive is dictated by the SATA standard protocol. An application using SATA drives in a storage area network is shown in figure 3 below.
The SATA drives are located inside each storage array and connected to the host controller using standard SATA cables and connectors. As systems are expanded to larger sizes, there is a need for longer lengths of interconnect between SATA hosts and drives. In larger server systems where the signal must travel through long backplanes, some signal conditioning could become necessary in order to maintain acceptable signal integrity throughout the system.
Server
Server
Switch
Storage Array
Storage Array
Storage Array
Storage Array
Host Controller
SATA Drive
SATA Drive
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Table 1 below shows the electrical specifications for SATA signals at the various interface points as defined above.
Table 1: SATA Electrical Specications
Parameter Data Rate AC Coupling Capacitance Common Mode Transient Settling Time Tx Differential Output Voltage Tx Rise/Fall Time Tx Differential Skew Tx AC Common Mode Voltage Tj at Connector Dj at Connector Units Gbps nF ns mVp-p ps ps mVp-p UI UI Gen 1i min 1.5 400 100 Gen 1i max 1.5 12 10 600 273 20 0.355 0.175 Gen1m min 1.5 400 100 Gen1m max 1.5 12 10 600 273 20 0.355 0.175 Gen1x min 1.5 400 67 Gen1x max 1.5 12 10 1600 273 20 Gen2i min 3 400 67 Gen2i max 3 12 10 700 136 20 50 0.3 0.17 Gen2m min 3 400 67 Gen2m max 3 12 10 700 136 20 50 0.3 0.17 Gen2x min 3 400 67 Gen2x max 3 12 10 1600 136 15 -
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For SAS, compliance points are defined as follows: IT: IR: CT: CR: XT: XR: Internal connector, Tx port Internal connector, Rx port External connector, Tx port External connector, Rx port Expander or SAS initiator PHY, Tx port Expander or SAS initiator PHY, Rx port
Table 2 below shows the electrical specifications for SAS signals at the various interface points as defined above.
Table 2: SAS Electrical Specications
Parameter Data Rate AC Coupling Capacitance Tx Differential Output Voltage Tx Rise/Fall Time Tx Differential Skew Tj at IR,CR,XR Dj at IR,CR,XR Units Gbps nF mVp-p ps ps UI UI 1.5 Gbps min 1.5 240 67 1.5 Gbps max 1.5 12 1600 273 20 0.55 0.35 3.0 Gbps min 3 240 67 3.0 Gbps max 3 12 1600 137 15 0.55 0.35
Note that the electrical specifications for SAS and SATA are similar to each other, which suggests that components that are used in the physical transport of signals can be used in SAS and SATA systems.
Figure 4: OOB Signal Example
Burst
Idle
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SATA defines two different OOB signals, COMRESET/COMINIT and COMWAKE. SAS identifies the same two OOB signals that SATA does, plus one additional OOB signal called COMSAS. The length of time for the burst and idle periods for each OOB signal is shown in table 3 below:
Table 3: Timing specications for OOB signals
Note: OOBI is a xed value equal to one UI of the nominal data rate
A complete OOB sequence contains six burst/idle periods followed by the negation time, where the transmitted signal is an idle. The length of the idle time is used to identify the type and speed of the OOB signal that is being transmitted. An example of a complete COMRESET OOB signal is shown in figure 5 below:
Figure 5: COMRESET OOB Signal
106 .7 ns
320 ns
After a PHY reset is issued, the SATA/SAS host controller sends a COMRESET OOB signal to the device, and waits to receive a COMRESET OOB signal to be returned from the device. If a COMRESET signal is sent and received between the host and device, the host then sends a COMWAKE signal to the device and waits to receive a COMWAKE signal to be returned from the device. If the host is a SATA host, then the SATA speed negotiation procedure begins after the host receives the COMWAKE from the device. If the host is a SAS/SATA host, then the host will send a COMSAS OOB signal to the device and look for the device to return the COMSAS to the host to confirm that the host is communicating with a SAS device. If the device returns the COMSAS to the host, then the host is configured fro SAS operation and the SAS speed negotiation process begins. If the device does not return COMSAS to the host, then the host is configured for SATA operation and begins the SATA speed negotiation procedure. Speed negotiation takes place between the host and device in order to determine the maximum data rate that the drive can support. For SATA systems, the speed negotiation procedure starts at the slowest data rate supported by the host and then the data rate is increased until the maximum data rate is identified. For SAS systems, the speed negotiation procedure begins with the maximum data rate supported and is decreased until successful communication is established.
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Test Setup:
The M21250 was evaluated with three different setups to verify operability with SAS/SATA systems. The first test was a functional test with a 1.5 Gbps SATA disk drive installed in a desktop PC. The high speed data path between the host and drive was broken and the M21250 was inserted in the middle of the data path as shown in figure 6 below:
Figure 6: Test setup with a desktop PC and SATA disk drive
Host Controller
M21250
SATA Drive
With the M21250 powered up and configured for operation t 1.5 Gbps, it was verified that read and write operations to the SATA drive were successful using the desktop PC. Another functional test was performed using a 3 Gbps SAS/SATA protocol analyzer and hard drive to verify functional compliance to SAS and SATA protocol when the M21250 was inserted into the data path of the signals. The setup used for this evaluation is shown in the figure 7 below.
Figure 7: Test setup with SATA/AS protocol analyzer and SAS disk drive
M21250 EVM
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The protocol analyzer was used to verify communication between the external SAS drive and the analyzer, and including verification of OOB signaling, speed negotiation, and protocol compliance of the external drive. With the M21250 EVM inserted into the high-speed data path and configured for operation at 3.0 Gbps, the functional tests were all passed. A summary of the functional testing performed with the M21250 EVM for SAS/SATA systems is shown in table 4 below.
Table 4: Functional SATA/SAS test results summary
Test Description Functional test with desktop PC and 1.5 Gbps SATA drive Protocol Generator/Analyzer test with 3.0 Gbps SAS Protocol Generator/Analyzer test with 3.0 Gbps SATA *Note that the M21250 does not lock to OOB signals, however OOB patterns do pass through the M21250 to allow for proper communication between initiator and host devices
Output parameter testing was performed on the outputs of the M21250 using a high speed pattern generator and high bandwidth, real oscilloscope to take eye parameter measurements on the device outputs. The setup used for this testing is shown in figure 8 below.
Figure 8: Test setup with high-speed pattern generator and real time oscilloscope
M21250 EVM
Results for the testing using the above setup are presented in the following pages.
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Eye diagram from M21250 output showing compliance to Eye Mask Testing
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1.5G SATA Gen 1x Test Results Vdiff TX, Minimum TX differential output voltage Vdiff TX, Maximum TX differential output voltage TX Rise Time TX Fall Time TJ after connector, clock to data, fBAUD/1667 DJ after connector, clock to data, fBAUD/1667 TJ at connector, clock to data, fBAUD/500 DJ at connector, clock to data, fBAUD/500
Specication Limits >=400 mV <= 50 mV 67 ps to 273 ps 67 ps to 27 3ps <= 550 mUI <= 350 mUI <= 470 mUI <= 220 mUI
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3.0G SATA Gen 2x Test Results Vdiff TX, Minimum TX differential output voltage Vdiff TX, Maximum TX differential output voltage TX Rise Time TX Fall Time TJ after connector, clock to data, fBAUD/1667 DJ after connector, clock to data, fBAUD/1667
Specication Limits >=400 mV <= 50 mV 67 ps to 136 ps 67 ps to 136ps <= 550 mUI <= 350 mUI
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In general the M21250 was compliant to output specifications for SAS and SATS 1.5 Gbps and 3.0 Gbps systems. The failures to the specifications occurred because the M21250 rise/fall times are on the fast edges of the specifications. It should be noted that the measurements recorded above were obtained using a high performance evaluation board, using high quality SMA connectors on the EVM to launch the signal from the EVM to the real time Oscilloscope. In an actual system environment, the signal at the output from the M21250 will likely travel through some backplane trace and potentially a lossy connector, this will tend to slow down the rise/fall time from the M21250 to meet SAS/SATA specifications.
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A measurement of the idle time for a COMRESET signal that has been sent through the M21250 is shown below. The idle time measured is 317 ns, compared to a shall detect range of 304 to 336 ns. Due to the long idle times found in OOB signals, the M21250 will lose phase lock and will lock to the reference frequency connected to the device when OOB signals are connected to the input of the M21250. The M21250 does not achieve phase lock to the OOB signal, but the OOB burst and idle signals are passed through the M21250 with minimal distortion, and allow for compliance to SAS/SATA OOB specifications at the system level.
Summary:
The M21250 can be used in 1.5 Gbps and 3.0 Gbps SAS and SATA systems as a signal conditioner as needed. The output signals from the M21250 are compatible with SAS/SATA requirements and with the appropriate selection of AC coupling capacitor values, the M21250 can also support OOB signaling for SAS/ SATA systems. For additional information on the M21250, please contact your local Mindspeed representative.
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