New Paradigms in the Silicon Industry

Chang-Gyu Hwang, President and CEO Semiconductor Business Div., Samsung Electronics Co., Ltd San #24, Nongseo-Ri, Giheung-Eup, Yongin-City, Gyunggi-Do 449-900 Korea Introduction
Over the past three decades, the semiconductor industry has grown at an unprecedented pace. This growth has been fueled by an exploding customer demand for products utilizing semiconductor chips. Whereas in prior years, the main semiconductor growth engine was the PC market, since the late 1990s the mobile era has emerged with a vast assortment of now familiar products, such as mobile phones, digital cameras and MP3 music players. It is widely agreed that the semiconductor industry will continue to expand rapidly due to continued steady growth of the mobile, digital consumer and entertainment markets. In addition to these, many more growth engines will appear, encompassing the automotive, information-technology, biotechnology, health, robotic and aerospace industries. The author of this paper submits that because of this astounding expansion in the number of markets, the semiconductor market is phasing out of the ebb and flow fluctuations of the past into a new era of steadily accelerating and more predictable growth. (Fig. 1) The advances in silicon technology that have been the backbone of tremendous previous growth, was foreseen in 1965 when Gordon Moore published his famous prediction about the constant growth rate of chip complexity.[1] And, in fact, it has repeatedly been shown that the number of transistors integrated into silicon chips has indeed doubled every 18 months. Increases in packing density, according to Moores law, are driven by two factors: reductions in production costs and increases in chip performance. Another prominent example of the unstoppable pace of technology advancement*, where new sources of momentum are able to maintain or accelerate a growth trend, was predicted by the author of this paper: the time required for the market to witness a doubling of the density of NAND flash memory has been maintained within the period of one year over each of the past seven years.[2] (Fig. 2) Despite these bright prospects, there is growing concern about whether semiconductor technology can continue to keep pace with demand when silicon technology enters the deep nano-scale Moores law was predicted to stagnate to the end of the 20th century, but SoC (System-on-a-chip) integration has the potential to continue IC (integrated-circuit) cost reduction and to perpetrate growth of personal Internet products.(in the presentation material of the reference) [2]) Also, see Fig. 10 in the article Nanotechnology Enables a New Memory Growth Model, authored by C-G Hwang, in Proceedings of the IEEE, 91 (2003) pp. 1765-1771: The highest memory-bit density growth will be much bigger than the prediction from the famous Moores law, and the rates are as follows: While Moores law (in memory) is twofold increase per 1.5 year, highest memory density growth is twofold increase per 1 year
*

dimension. This is because there are ultimate limits to transistor scaling, and narrowing margins in manufacturing due to everincreasing fabrication costs tied to technical complexities.[3, 4] Though most experts believe that silicon technology will maintain its leadership down to 20 nm, beyond this node a number of fundamental and application-specific obstacles will prevent further shrinkage.[5] (Fig. 3) A common example is the inevitable occurrence of variations due to rough line edges and surfaces when pattern sizes approach atomic scales. It is therefore the primary aim of this paper to present various possible paths to overcome these obstacles and ultimately, to maintain the technology-scaling trend beyond the 20 nm node. As will be shown, these solutions include not only 3-D (threedimensional) technologies but also non-silicon technologies on a molecular scale. In addition, new applications, and new growth engines for the semiconductor industry will be provided from a fusing of separate technologies such as silicon-based IT (information technology) with new materials or even new concepts.[6, 7] The paper is structured as follows: in the first part a brief review of the evolution of key silicon technologies is given. The second part states technological limits to scaling and offers possible solutions to these problems. The third part will present prospects for the future silicon industry covering the aforementioned fusion technologies.

Genesis and evolution of silicon technologies

Since the first 1,024-bit DRAM (dynamic random access memory) was demonstrated by Intel in the early 1970s, the highest available density of DRAM has doubled every 18 months. Now DRAM technology has reached 60 nm in process technology and 2 Gb in density, which will appear soon in the marketplace. Further, DRAM at a 50 nm node is being developed at R&D centers around the world. DRAM technology has evolved toward meeting a need for ever-increasing data retention and ever-demanding performance improvements. Increases in data retention impose great challenges on DRAM technology by requiring both a sufficient amount of capacitance in a memory cell and an extremely low level of leakage current from the storage junction. First, in order to meet the requirement of the cell capacitance, the cell capacitor has evolved from 2-D (two-dimensional) structures (e.g. planar capacitors) to 3-D structures, such as stacked capacitors or trench capacitors.[8] (Fig. 4) A cell transistor in DRAM has been designed to reduce sub-threshold leakage currents. As a result, memory cell transistors in DRAM tend to have high voltage thresholds. Not only does this cause leakage current in the storage junction, but it also decreases current drivability of the cell transistor as a result of high doping concentration in the channel. Therefore, the typical DRAM cell

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requires optimization between the sub-threshold leakage current (through a cell transistor) and the storage-junction leakage current. NAND flash memory has the smallest cell size among silicon-memory devices commercially available due to its simple one-transistor structure and a serial connection of multiple cells in a string. Because of this, NAND flash has carved out a huge market for itself, as was expected ever since it first appeared in the mid1980s. The need for NAND flash memory will continue to skyrocket. With the rise of the mobile era, NAND flash has pushed toward everhigher density, along with improving programming throughput. As a consequence, the memory has evolved toward an ever-smaller cell size in two ways: by increasing string size and by developing two bits per cell, while at the same time, increasing page depth.[9] (Fig. 5) Now, current NAND flash memory reaches 40 nm in process technology and 32 Gb in density, mass production of which will blossom beginning around 2008. In addition, NAND technology beyond 40 nm is now under development at R&D centers across the world. Along with the recent development of two-bit-per-cell technology, the introduction to multi-bit cells should greatly accelerate this trend. Meanwhile, the evolution of CPU technology has increased. The number of transistors has doubled every two years to where now there are more than 100 million per chip. This rate of advancement has accelerated recently at an even more remarkable pace due to the introduction of multi-core technology intended to resolve the CPU power crisis while improving performance.[10] The reason why we have been so successful in increasing the packing density of memory devices and CPUs is mainly due to so-called shrink technology,[11] where basic CPU transistors and/or memory cells can be scaled down successfully without dramatic changes in each structure. Such shrink technology has thrived thanks to the timely evolution of optical lithography and transistor-scaling engineering. In fact, it is widely accepted that we now can continue to use the optical tools down to a 35 nm node. If one uses optical lithography techniques down to the deep-nano-scale dimension, we can take full advantage of experience accumulated over the last 30 years to define ever-finer patterns through lithography infrastructures. Thus, we believe that shrink technology can be extended to develop and fabricate silicon chips down to a 35 nm node. Beyond 35 nm, it is uncertain whether we can push optical lithography to a new limit, along with various supportive techniques. It is also unclear whether we will have to introduce entirely different infrastructures such as EUV (extreme ultra-violet) and nano-imprint. But we will have to devise a more appropriate lithography process beyond 35 nm. Transistor-scaling theory[12] basically tells us that when a transistor is scaled down by 1/K, its power-delay product will be improved to 1/ K3. As a result, transistor scaling results in high performance and high density.

Stepping forward to 3-D technologies

3

K is a scaling factor; greater than 1, and 1/ K is a measure of transistor performance.

The advantages of scaling transistors cannot be entirely relied upon when device dimensions shrink down to the nano-scale. This is because of non-scalable physical parameters such as mobility and sub-threshold swing. In addition, several other important factors make it difficult to scale transistors to a nano-dimension: dealing with a tiny amount of electrons; interference between adjacent cells; and pronounced CD (critical dimension) variationsall of which are critical in a nano-scaled 2-D transistor. When working with silicon devices, a transistors key parameters must take into account: oncurrent; off-leakage current and the number of electrons contained in each transistor, or the number of transistors that have been integrated.[11] All of these factors are very important, but not equally important in the case of silicon devices. For instance, in logic devices, on-current is emphasized most because logic technology is focused on an ever-increasing on-current of transistors because of speed concerns. On the other hand, in memory devices, off-leakage current is regarded as a more important factor and as a result memory technologies have been developed with a greater emphasis on reducing leakage current related to power savings and performance improvements. For logic technology, transistor delay is the single most important parameter, not just to indicate chip performance but to measure the level of excellence in device technology as well. This transistor delay, which relates closely to transistors on-current state, will continue to be reduced to a 30 nm channel length. However, at less than the 30 nm, the transistor begins to deviate in spite of a much relaxed off-current requirement. (Fig. 6) This is mainly due to the aforementioned non-scalable parameters (mobility and subthreshold swing) and to parasitic resistance. To tackle these critical issues, two approaches need to be examined. One attempt is to enhance carrier mobility using mobility-enhancement techniques such as strained Si[13], SiGe/Ge channel[14], or an ultra thin body of Si[15], where carrier scattering is suppressed effectively. Another approach is to reduce the channel resistance by widening the transistor width. In this case, it appears very promising to use different channel structures such as trigate[16] or multi channel[17]. As silicon technology scales down further, two approaches eventually will be merged into one single solution, i.e. a gate-all-around (GAA) structure[18] with an optimum level of gate control. With this type of structure, one will arrive at nearly ideal transistor performance such as performance that is virtually free from SCE (short channel effect), sufficient on-current and suppressed off-current. It is believed that developing a transistor with a GAA structure is quite feasible if one can extend 2-D silicon technology to 3-D. This is because the channel length is no longer restricted by lateral dimension. (Fig. 6) DRAM has often struggled to increase data-retention times, which play a key parameter in power consumption and performance. To meet the ever-present demand for increased retention time, it is essential to minimize leakage current. Thus, the most critical scaling factor in DRAM stems from finding the best way to design a cell array transistor. In general, data retention in DRAM is inversely proportional to the junction-leakage current, which results from electric-field strength spread across the junction of a cell transistor. Unfortunately, dimension scaling of the planar-

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based cell transistor in DRAM is inevitably accompanied by a severe increase in doping concentration underneath the channel region. Typically, any degradation of the retention time becomes significant below 100 nm due to a rapid increase in the junction electric-field. This issue can be overcome by introducing 3-D cell transistors, whose junction electric-field can be greatly suppressed due to a lightly doped channel region. In an attempt to improve the retention period in DRAM, we have shown cell array transistors that have a great immunity against the SCE. One example of these is a RCAT (Recess Channel Array Transistor)[19], whose gate detours around some part of the Si substrate so that an elongate channel can be formed. To some extent, one can extend this technology down to a 50 nm node with only minor modifications of the RCAT. Beyond 50 nm, we may need another breakthrough for array transistors in DRAM. Some studies show that a body-tied FinFET (Fin field effect transistor)[20] for memory in a cell array transistor lends some clues as to how best to extend the technology node further to take advantage of its superb transistor features: excellent immunity against the SCE; high transconductance; and extremely suppressed sub-threshold leakage. It is believed that the body-tied FinFET reinforces conventional silicon technology to extend down to 30 nm. (Fig. 7) It is also believed that a vertical transistor with a surrounding gate will be an appropriate candidate for solving pertinent problems because the vertical transistor no longer needs to rely on a lateral dimension. When the vertical surrounding gates are applied as a DRAM cellarray transistor,[21] the current momentum toward smaller cell size from 8F2 to 6F2 will be sufficient enough to reach 4F2 in cell size and even below. (Fig. 8) As NAND flash memory enters a 50 nm technology node, flash memories based on a floating-gate (FG) structure will face serious scaling issues. These problems are often posed not only by the physical aspects of the cell structures but also by some aspects of its electrical performance. There are physical constraints to building an extremely tiny FG-NAND flash cell and they can be divided into three areas. First, both tunnel oxide and an inter-poly dielectric (ONO) have reached their lower thickness limit. The second problem is cell-to-cell interference, i.e. when a dimension scales down, the distance between the floating gates becomes so close as to cause a large amount of interference. Lastly, the most fundamental issue in FG-NAND flash is the reduction in the number of electrons as a design rule shrinks. It is expected in FG-NAND flash that we will see a serious electron-storage problem surface at the 40 nm node because of a lack of electrons (less than 100) being stored in the memory bit.[4, 8, 9] A high-k dielectric as an inter-poly layer could provide a solution against those scaling limitations in FG-NAND flash that were previously mentioned. However, we believe that this sort of modification will serve only as an interim solution. As such, we have to find another pathway that can lead us not only to a 40 nm node but even to the 20 nm node and beyond. A critical question here is whether there are any solutions for replacing the FG structure for NAND flash memory. Many structures using a charge-trap (CT) layer[22], nano-dot[23], and nano-crystal[24] are considered candidates for the next generations of NAND flash memory. Among

these, CT-NAND flash appears most promising at this time. This is for a few reasons: a nitride layer is able to store many electrons; the CT layer is free from cell-to-cell interference; and the nitride layer is not only relatively well-known but CMOS-friendly from the point of fabrication. However, two big quandaries remain that the CT-NAND flash must tackle: one is short retention periods and the other is how fast erase operations can be carried out. Recently, we successfully developed 32 Gb TANOS (TaN-aluminum oxide-nitride-oxide-silicon) NAND flash at a 45 nm technology.[25] Not just to provide a fast erase speed but also to obtain a wide Vth (threshold voltage), we have pioneered a novel structure with a high-k dielectric of Al2O3 as the top oxide and TaN as a top electrode. With this approach, we can attain several essential properties for non-volatile flash memory: good programming/erasing characteristics and an adequate Vth window for a multi-bit operation, as well as a robust level of reliability. It is noteworthy that the TANOS structure has much better mechanical stability than that of an FG-type cell because of the far lower stack. Interference among TANOS cells hardly occurs at all due to the nature of the charge trap mechanismSiN (silicon nitride) traps act as point charges. This is the biggest advantage in the CT-NAND flash memory. To scale NAND flash further down, we may need another cell technology. A FinFET could be a very promising candidate because it can increase storage electrons effectively. In pursuit of which, we also have successfully developed a FinFET TANOS structure[26], where we can obtain fast program/erase speeds and durable retention as well as endurance. If there are much higher k dielectrics than Al2O3, then we can further scale down the FinFET CT-NAND flash memory. Beyond the 20 nm node, we believe that the most plausible way to increase density is to stack the cells vertically.[27] (Fig. 9) This is due to the many limitations encountered with lateral integration, including scaling limitations of FinFET TANOS structures, difficulties in manufacturing, and the unavailability of lithography. Among these, the lithography concern is not discussed here, but it might be the first stumbling block to further evolution of NAND flash unless the industry is properly prepared In practice, as a device enters the realm of nano-scaling, we know that CD variations and parametric fluctuations become much pronounced. Under the current assumption of a major performance parameter change every 12 months, the likelihood of meeting the goal of reducing the complexity (e.g. number of transistors in the CPU; memory density) per unit cost appears to be extremely marginal. To some extent, it is not a bad idea to find another pathway to reach the goal. This most likely would be to devise new structures more friendly from a manufacturing perspective with a much relaxed design rule, while maintaining the same performance growth and continuing to double density. All plausible solutions described earlier tell us that current planar technology will reach an impassable limit, and while silicon technology is moving away from 2-D planar silicon technology, 3-D silicon technology is showing clear signs of serving as the foundation for a rebirth of the silicon industry.

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The advantages of 3-D integration are numerous. They include: 1) elimination of uncertainty in the electrical characteristics of deep nano-scale transistors; 2) extendable use of silicon infrastructures, especially optical lithography tools; 3) forming a baseline for multi-functional electronics and facilitating implementation of a hierarchical architecture, where each layer is dedicated to a specific functional purpose. For instance, there would be one layer for data processing, a second layer for data storage, a third layer for data sensing and so on.

3-D design meets new materials and new concepts

The early version of 3-D integration has been commercialized already in a multi-chip package (MCP), where each functional chip (not device) is stacked over one another and each chip is connected by wire bonding or through the through-via hole bonding method within a single package. (Fig. 10) The advantages of the MCP are a small footprint and better performance compared to a discrete chip solution. It is expected that the MCP approach will continue to evolve. However, the fundamental limitation of MCP will be its relative lack of cost-effectiveness due to a number of redundancy/repair issues. In this respect, 3-D silicon-integration technology is able to overcome MCP limitations through an easy implementation of redundancies and repairs. Recently, new silicon technology based on 3-D integration has drawn much attention because it seems to be regarded as the only practical solution. Though the concept of 3-D integration was first proposed in the early 1980s,[28, 29] it has never been thoroughly investigated or verified until now, as silicon devices had not approached their limits, and high-quality silicon crystal was not ready for fabrication. Recent advances in selective epitaxial silicon growth at low temperature[30] and in high quality layer transferring technology with high-precision processing[31] can bring major new momentum to the silicon industry via 3-D integration technology. The simplicity of memory architecture consisting of memory array, control logic and periphery logic, makes it relatively easy to stack one memory cell array over another. This will ultimately lead to multiple stack designs of many different memories. Recently, some memory manufacturers have started implementing 3-D integration technology with SRAM (static random access memory) to reduce the large cell size in planar silicon technology.[32] For transistors stacked onto a given area with no need for well-to-well isolation, a SRAM cell size of 84 F2 is being reduced to the extremely small cell size of 25 F2. (Fig. 11) Encouraged by this successful approach in SRAM, stacked flash memory has also been pursued. (Fig. 12) A preliminary result[27] indicates great potential for large-scale use with 3-D flash-cell technology, which will spur further growth in high-density applications. The stacking of memory cells via 3-D technology looms on the horizon, in particular, for NAND flash memory. It is believed that logic technology will shift to 3-D integration after a successful jumpstart in the silicon business. The nature of a logic device, where transistors and interconnections are integrated as key elements, is not much different than that of stacked

memory cells. It may be very advantageous to soon introduce 3-D integration technology to a logic area. For example, a dual-core CPU can be realized with only a half of the chip size, which will result in significantly greater cost-effectiveness. It is noteworthy that implementation of interconnection processes seems to be more efficient in a vertical as opposed to a lateral approach, the latter of which has posed headaches with current logic technology. Another promising use would be to improve logic performance by cutting down on the length of metallization. Decrease in the interconnection length means a huge amount of reduction in parasitic RC components, i.e. a high speed and power saving. In addition, 3-D technology will make it easy to combine a memory device and a logic device onto one single chip through hierarchical stacking. Because most silicon in future SoCs (system-on-chips) will be allocated to memory parts, this combining trend will be accelerated. Therefore, rapid adoption of 3-D integration technology seems to be essential and, thankfully, unavoidable. The next step after a sophisticated vertical combining of logic and memory will be to stack multi-functional electronics such as RF (radio frequency) modules, CISs (CMOS image sensors) and bio-sensors (e.g. lab-ona-chip) over the logic and memory layers. (Fig. 13) Meanwhile, as the use of 3-D silicon technology has great potential to migrate into a wide diversification of multi-functional gadgetry, it should ignite a trend that merges one technology with another, ranging from new materials through new devices to new concepts. In this regard, new materials may cover the following: carbon nano-tube (CNT)[33], nano-wire (NW)[34], conducting polymer,[35] and molecules[36]. New devices could also be comprised of many active elements, such as tunneling transistors,[37] spin transistors,[38] molecular transistors,[39] single electron transistors (SETs)[40] and others. We may be able to extend this to new concepts, varying from nano-scale computing[41] and FET decoding[42] to lithography-free addressing[43]. To a certain extent, some of these will be readily integrated with 3-D silicon technologies. This integration will further enrich 3-D silicon technologies to produce various new multi-functional electronics, which will provide further substantive boosts to the silicon industry.

Prospects on future of silicon industry

Since the silicon integrated circuit was first invented, the silicon industry has been pursuing ever-improving performance, while striving for greater cost-effectiveness. As a result, current key silicon technologies are quite dissimilar and difficult to combine. Nonetheless, there have been attempts to merge existing technologies to optimize performance and cost-effectiveness. SoC is a good example; another is OneNAND, invented to provide distinct cost and performance advantages over NOR flash memory.[44] With OneNAND, the cost-effectiveness is gained by the NAND cells and the higher performance is being achieved with embedded SRAM. New markets driven by this kind of fusion technology will help to The reason for this originates in the fundamentals of MOS transistors where high on-driving current should be accompanied with high off-leakage current and vice versa.

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propel todays silicon industry to previously unattained heights with surprising performance improvements. For the long term, the silicon industry is expected to expand even more and more rapidly than it has in the past. Increases in performance will enable semiconductor products to satisfy increasingly diversified needs in the automotive, robotics, aerospace and other industries. For instance, the future automobile may include digital wheels[45] in which a large amount of silicon chips will be used. Regarding robotics, the physical basis for pseudo-human brains may be laid out by extrapolating the current technology trend of data processing and storage. With DRAM density, for instance, we expect that bit density will reach 0.5 ~ 1.0 Tbit/cm3 by 2020, which is comparable to the data-storing capability of the human brain. Apart from consumer products, an insatiable demand for massive data processing will continue to be seen in many fields of science, where data gathering, processing or simulation is needed on a massive scale. Consider the simulation of natural or man-made disasters as but one example. In addition to support for massive processing, basic science applications in cosmology and other fields requiring sophisticated simulation, also will depend heavily on enhanced data-processing capabilities. Many new opportunities and growing momentum for the semiconductor industry will come from device-converging trends in countless areas, allowing us to make a projection of a nano-silicon era into practical realities today and tomorrow. These realities will be manifested in highly desirable applications of the fusion of information technology (IT), bio-technology (BT), and nanotechnology (NT), to become so-called fusion technologies (FT). If key obstacles are tackled by bridging the gap between previously incompatible platforms in silicon-based CMOS technology and new technological concepts, a vast number of new applications will unfold. One example may be many applications related to health sensor technology, in particular, the early recognition of cancer diseases and the screening of harmful and poisonous elements pervasive in the environment. (Fig. 14) Further, when a nano-scale bio-transistor is available, labon-a-chip (LoC) will become a single solution integrating all of its essential components, such as micro-array, fluidics, sensors, scanners and displayers. Then, by its very nature, a mass of disposable LoCs will be consumed, which will stimulate the future silicon industry. Many dreams will be embraced within a single silicon solution not too far in the future. We will even realize many things that are unimaginable today. The author strongly believes that all these dreams will be linked directly or indirectly, at least in some key aspect, to future silicon technologies. Considering all of these opportunities, the future silicon industry will have tremendous potential to match and even exceed the maximum annualized growth rates of the semiconductor-industry revenue despite recent hesitations in the growth curve.

Conclusion
Many challenges await the silicon industry as technology enters the deep nano-dimension era. However, armed with new technologies such as 3-D scaling and a wealth of promising materials, along with fusion technology, we will not only overcome barriers that today appear formidable, but enjoy the many challenges we will encounter along the way. Over the next decade, we will observe many opportunities and witness great endeavors in numerous areas that will greatly stimulate the semiconductor business. For one, the successful evolution of device structures will continue and even accelerate at a greater pace in the not-too-distant future. In addition, modern and future device designs will converge onto a single mobile platform, covering many different capacities and services from telecommunication through broadcasting and even as yet unforeseen data-processing applications of culture-shifting magnitude. Finally, semiconductor technology will play a critical role in realizing functionally merged solutions such a bio chip, where patients will house diagnostic, prescriptive, and even surgical data. All of these will permit us to gain invaluable clues not just on how to prepare future silicon technology but also on how to positively influence the direction of the entire silicon industry. This will allow us to attain an even more sophisticated fusing of technologies. As has been in the past, silicon technology will continue to provide many new and even as yet unforeseen benefits to society through much more costeffective and versatile solutions. Finally, the author would like to conclude this paper with a simple phrase: The future is not to be predicted, but to be created

Acknowledgements
The author is grateful to many colleagues for numerous discussions of the issues appeared in this paper. The author would like to thank especially Dr. Kinam Kim for fruitful discussions and helpful suggestions preparing the paper. The author would also like to acknowledge Dr. C. H. Kim, Dr. B. Suh, Dr. T. S. Jung, Dr. J. T. Kong, Dr. D-G. Park, Mr. John Kang, and Mr. John Lucas for their valuable suggestions.

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Nanowire Arrays for Integrated Nanosystems, Nano Letters, 3 p. 1255-1259, (2003) [7] Y. Wada, Prospects for Single-Molecule Information-Processing Devices for the Next Paradigm, Ann. New York Acad. Sci. 960, p3961, (2002) [8] K. Kim, Manufacturing technology for sub-50 nm DRAM and NAND Flash memory, (invited) Semiconductor FABTECH, pp. 1319 (2006) [9] K. Kim, et al., The Future Prospect of Non-volatile Memory, (invited), Proceedings of technical papers of 2005 IEEE VLSI-TSA, pp.88-94, (2005) [10]http://www.intel.com/pressroom/kits/events/moores_law_40th [11] K. Kim, Technology evolution of semiconductor devices for nano generation and beyond, (invited), 2nd Samsung Tech. Conference, (2005) [12] R. H. Denard et al., Design of Ion-Implanted MOSFETs with very small physical dimensions, IEE J. Solid-State Circuits SC-9, p. 256, (1974) [13] H. Daembkes et al., The n-channel SiGe/Si Modulation-doped Field-Effect Transistor, IEEE Transactions on Electron Devices, ED-33, p. 633 (1986) [14] T. Ghani et al., A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors, Technical Digest of IEDM, p. 978, (2003) [15] D. Hisamoto et al., A Fully Depleted Lean-channel Transistor (DELTA) A novel vertical ultra thin SOI MOSFET ---, Technical Digest of IEDM, p.833, (1989) [16] R. Chau et al., Advanced Depleted-Substrate Transistors : Single-Gate, Double-Gate and Tri-Gate, SSDM, pp. 68-69, (2002) [17] S-Y Lee et al., A novel multibridge-channel MOSFET (MBCFET): fabrication technologies and characteristics IEEE Transactions on Nanotechnology, 2, Issue4, p.253, (2003) [18] J. P. Colinge and et al., "Silicon-on-insulator gate-all-around device", Technical Digest of IEDM, p. 595, (1990) [19] J. Y. Kim et al., The Breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor (RCAT) for 88nm feature size and beyond, VLSI Technical Digest, pp.11-12, (2003) [20] C. H. Lee et al., Novel body tied FinFET cell array transistor DRAM with negative word line operation for sub 60 nm technology and beyond, VLSI Technical Digest, pp.130-131, (2004) [21] J-M Yoon et al., A Novel Low leakage Current VPT (Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology, 64th DRC Digest, pp.259-260, (2006) [22] D. Frohman-Bentchkowsky, The Metal-Nitride-Oxide-Silicon (MNOS) Transistor characteristics and applications, Proc. IEEE, 58, p.1207, (1970) [23] Z. Liu et al., Process and device characteristics of selfassembled metal nano-crystal EEPROM, Si Nanoelectronics Workshop, VLSI Technical Digest. (2000) [24] S. Tiwari et al., "A Silicon Nano-Crystals Based Memory,'' Appl. Phys. Lett. 68 1377 (1996). [25] Y. Park, et al., Highly manufacturable 32Gb multi-level NAND flash memory with 0.0098 mm2 cell size using TANOS(Si-oxidenitride-Al2O3-TaN) cell technology, to appear in Technical Digest of IEDM, (2006) [26] S. H. Lee et al., Improved post-cycling characteristic of FinFET NAND Flash, to appear in Technical Digest of IEDM, (2006)

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Fig. 1: The past trend and future projection on semiconductor markets

Fig. 5: Technology evolution in NAND-flash-memory. NAND flash has been evolved to 2bit/ cell and it will be expected to eventually evolve to multi-level cell.

Fig. 2: Doubling phenomena of memory density every 12 months, supporting a new memory-growth model proposed by the author Fig. 6: A recent observation of transistor performance as technology shrinks. Performance improvement predicted by the transistor-scaling theory does not work properly around 30 nm. However, the GAA structure shows great gate controllability.

Fig. 3: Prospects on the long-term silicon technology. There seems to be a big gap between technology nodes, in particular, around 20 nm. While the incumbent silicon technology will be extendable up to 20 nm, below 10 nm quantum physics will dominate.

Fig. 7: A prospect on the cell evolution in DRAM

Fig. 4: The evolution trend of DRAM technology. In the early stage of evolution, the DRAM cell capacitors have been evolved to 3-D structures such as stack or trench types.

a) 8F cell

b) 6F cell

c) 4F cell

Fig. 8: DRAM cell architectures being changed to 4 F2 from 8 F2 through 6 F2 in terms of unit cell size.

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Fig. 9: The cell-technology evolution of NAND flash memory

Fig. 12: NAND flash memory fabricated by 3-D integration technology. Multi-stacked TANOS cell in CT-NAND flash memory can be readily implemented by 3-D integration technology.

7/8/9/10 chip 3/4/5/6 chip

1/2 chip

a) MCP

b) WSP
Fig. 13: A schematic illustration showing 3-D fusion technology by vertical stacking of either heterogeneous materials or differently functioning devices: 3-D SoC + SiGe, MEMS, Optics, III-IV compound semiconductors, and others, being able to realize an extremely tiny multi-functional chip in ubiquitous era.

Fig. 10: Illustrations of 3-D chip stack technologies: a) MCP( Multi Chip Package ) by wire bonding b) WSP (Wafer-level Stack Package) with through-via hole

Fig. 11: 3-D integration technology for SRAM, cell size of which can be reduced dramatically to 25 F2 from 84 F2 in planar technology.

Fig. 14: Paradigm in the semiconductor industry will shift to fusion era as future technologies become converging

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