A New Test Data Compression for Low Power Test

Sunghoon Chun Yongjoon Kim Minjoo Lee Sungho Kang

Department of Electrical and Electronic Engineering Yonsei University 134, Shinchon-Dong Seodeamoon-Gu, Seoul, Korea shchun@soc.yonsei.ac.kr Abstract This paper proposes a new test data compression method for low power testing. To improve compression ratio, the proposed scheme uses the modified input reduction and novel techniques, a new scan flip-flop reordering algorithm and a newly proposed one block compression. The proposed method leads to better compression ratio with lower hardware overhead and lower power consumption than previous works. Experimental results validate efficiency of the proposed method. Keywords: Test data compression, Low power test and static compaction of scan vectors for the low power test [6]. Recently, a number of test data compression techniques have been proposed for reducing test data volume [7-10]. However, these techniques did not consider power consumptions during testing. In [11], test data compression for low power scan test is presented and however this still has problems cuased by the cyclic shift register (CSR) architecture and the static compaction test vectors. In this paper, we propose a new test data compression method for low power test in order to overcome a power consumption problem and enormous test data volume problem. The rest of the paper is organized as follows. The next section explains the power consumption model to estimate power dissipation during scan testing and introduces several definitions to easily present the proposed method. The proposed scheme is presented in Section 3. The experimental results for ISCAS 89 benchmark circuits are presented in Section 4 followed by conclusion in Section 5.

Introduction

As the complexity of VLSI circuits increases, it is more important to test VLSI circuits exactly. Especially, todays large and complex VLSI circuits in SoC environments need an enormous amount of test data. When SoCs are tested, such test data are transfered to the circuit under test (CUT) from an automatic test equipment (ATE). Since the channel width and the size of memory for the ATE are limited, the traditional ATE must be modified or more expensive ATE must be required in order to test an SopC with enormous test data. In addition, if the original test data are reduced for the size of the ATE memory by eliminating useful test patterns, then the accuracy of testing can be decreased. Test data compression is necessary to overcome these limitations. The test power could be twice as high as the power consumed during the normal mode [1]. Excessive power consumption during test can cause several problems. Firstly, this leads to an increased maximum current flow in the CUT increased peak current and the electromigration wihch are thus affecting the reliability of the system. In addition, power consumption during test is more important since excessive heat dissipation can damage the CUT directly. Therefore, we focus on the test data compression method for low power test in order to overcome these problems. In fact, the low power scan testing and the reduced test data volume are conflicting goals. To alleviate these conflicting goals, the approaches of resolving test problems has been researched over last several years. These include lower power built-in self test (BIST) [2-5]

Preliminary
2.1 Power Consumption Model

The source of power dissipation in CMOS devices is summarized by the following expression[12] :

1 2 P = C VDD f N + QSC VDD f N + I leak VDD 2

(1)

where P denotes the total power, VDD is the supply voltage, and f is the frequency of operation. The expression fN is the average number of times per second that the nodes switch. It has been shown [13] that during normal operation of well designed CMOS circuits the switching activity power accounts for over 90% of total power dissipation. Thus power optimization techniques at employed different levels of abstraction target minimal switching activity power. The model for power dissipation for a gate i in a logic circuit is simplified as :
P= 1 Ci VDD 2 f Ni 2

(2)

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The capacitive load Ci that the gate is driving can be extracted from the circuit. The switch activity Ni depends on the input to the system which during test mode involves test vectors and therefore, for low power scan based test, reducing switching activities during scan shifting is one of the most significant factors. We use the extended version of the weighted transitions metric (WTM) introduced in [6] to estimate the power consumption due to scan vectors. In the original WTM, the scan in power for a given vector is estimated using the number of transitions in it with their relative positions. However, since we should consider the power of scan output responses for a given vector during scan based test, the original WTM is modified slightly. Consider a scan chain of length k, a scan vector P = {p1, p2, , pi} and a scan response R = {r1, r2, , ri}. The extended WTM to estimate the power consumption during scan based test is as follows:
WTM =

Definition 3. Scan Input/Output Vector (SV) : For a given test input set TD, scan input/output vector of input i, SVi, is defined as the union set of the test input sequence SVik(input) and the output response for each test input sequence k, SVik(output). Definition 4. Scan Distance (SD) : For a given test input set TD, the scan distance SD is defined as the distance between scan input/output vector SVi and SVj. Therefore, the scan distance SD is calculated using the following equation.
SDij =

SV
k =0

L 1

ik

SV jk

where i < j

(5)

Definition 3. Compression Block : The compression block (CB) is defined as the 4-bit block which occurs most frequently in the test data. Definition 4. Uncompression Block : The test data which exclude the compression block is divided into 2-bit blocks. The uncompression blocks are defined as theses divided 2-bit blocks. The uncompression block is denoted by UB.

(p
j =1

p j + i )( k j ) +

(r
j =1

r j + i )(k j ) (3)

If the total test vector set Ptotal contains n vectors P1, P2, , Pn and n response R1, R2, , Rn, then the total power consumption WTMtotal is as follows:
WTM total =

The Proposed Method

3.1 The Modified Input Reduction

WTM
i =1

(4)

2.2

Definitions

To simplify the presentation of the proposed test data compression scheme for low power test, the following definitions are used. When a test set TD whose input size is N and length is L is given, let v(i , k) be a value of input i (0 i N-1) at sequence k (0 k L-1). Definition 1. Input Compatibility : For a given test input set TD, two inputs i and j are compatible, if and only if v(i, k) = v(j, k). If v(i, k) = X (dont care) or v(j, k) = X, it should not conflict the value of any other compatible or inverse compatible inputs. Let v(i, k ) be an inverse value of v(i, k). The inverse compatibility is defined as follows. Definition 2. Input Inverse Compatibility : For a given test input set TD, two inputs i and j are compatible, if and only if v(i, k) = v ( j, k ) . If v(i, k) = X (dont care) or v(j, k) = X, it should not conflict the value of any other compatible or inverse compatible inputs.

In order to reduce test data sets for a BIST, the input reduction was proposed in [13]. A new input reduction scheme is used in this paper, which is the modified version of the input reduction scheme in [13], in order to achieve high compression ratio. The input reduction scheme is to identify circuit inputs that can be combined into other test inputs without the loss of fault coverage. Unlike the input reduction scheme in [13], we consider a case where test sets are given because we do not consider ATPG for BIST. Therefore, we propose a new input reduction algorithm in this case. The proposed algorithm is shown in Fig. 1. Initially, in this algorithm, the initial set of input check set C is prepared and Ci (0 i N-1) has UNIQUE value, which means that input i is not input compatible or input inverse compatible. For entire test sequence k (0 k L-1) for given test set TD, is_compatible function is the function to check the compatibility between target input value v(i, k) and comparison input value v(j, k) by the concept of Definition 1 and Definition 2. In this function, as defined as Definition 1 and 2, if v(i, k) or v(j, k) is unspecified, then it should check whether it conflicts the value of any other compatible or inverse compatible inputs in conflict_check function which is included in is_compatible function.

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Since the architecture to apply the modified input reduction adds fanout points and inverters only to original scan chains and modifies the connection of scan chains, it is reconfigurable with small effort.

Figure 2. The scan flip-flop reordering algorithm To reduce test power consumption using the scan FF reordering algorithm, first, the scan input/output vector SVi (0 i N-1) defined in Section 2 is set. In this case, assuming that, for given original test data TD, the reduced test data TIR using the modified input reduction has M inputs, SVk(input) of (N-M) compatible or inverse compatible inputs should set X (dont care) in entire test sequences since SVk(input) of them do not affect scan shifting in test mode. Therefore, SVi of the compatible input or the inverse compatible input can be obtained to combine the SVk(input) which set X in entire test sequence and SVk(output). Next, the scan distance SDij is calculated using the scan input/output vector SVi. Based on this scan distance SDij, the order of scan flip-flops is determined and X values of SVi are justified to minimize the power consumption during scan shifting. Note that the result of XOR operation for the X value is 0 when calculating the scan distance SD. 3.3 The Proposed Compression Code

Figure 1. The modified input reduction algorithm By using this modified input reduction, test data volume is reduced in proportion to the number of the reduced inputs and the number of switching activities during scan shifting in scan chain is also reduced. Therefore, the power consumption during scan based testing is diminished, especially putting test sequences into scan chains. 3.2 Scan Flip-Flop Reordering Algorithm

The advantage of the reduced test data TIR is reducing transitions in test input sequences. However, since the modified input reduction considers only input sequences, there is no benefit during scan shifting for scan output responses. To consider the scan output responses as well as the scan input sequences for low power test, we propose a new scan flip-flop reordering algorithm in this paper. The key idea of the scan flip-flop reordering algorithm is to find the order which has the minimum scan distance between scan flip-flops. Thus, the switching activities during the entire sequences are significantly reduced using the proposed scan flip-flop reordering algorithm. Fig. 2 presents the scan flip-flop algorithm.

In this paper, a new compression code is proposed in order to efficiently compress test data for low power test. The main key idea is that the compression ratio is enhanced by increasing the occurrence frequency of one block. It can be achieved by appropriately filling specific values to numerous unspecified values (X values) in test sets. Compressing one block leads to lower hardware overhead for the decoder while, in the methods like the Huffman code, as the number of the compressed blocks is increased, the hardware overhead for the decompression architecture is increased enormously. The idea of the proposed code is to make the 4-bit block, CB, which occurs most frequently have a one-bit code, and the rest of test sets have 3-bit codes which consist of a 2bit original block and a prefix bit to identify uncompressed 2-bit blocks. To increase the occurrence frequency of the specific 4-bit block is implemented easily and it is an efficient method to improve the compression ratio for test data. Furthermore, test data except the compression block are divided into 2-bit blocks, the uncompression blocks, in order to make the most frequent 4-bit block in test sets occurs more frequently. This is because dividing the rest of

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test data which exclude the CB into smaller size has much more chances to increase the occurrence frequency of the CB in the original test data. For this reason, the compression block occurs more frequently as the length of the UB is 2 bits. The goal of the proposed compression code is to improve the compression ratio by increasing the occurrence frequency of the most frequent 4-bit block in TIR whose scan vector is reordered. The algorithm used to implement the proposed scheme has two procedures : (1) reordering the test set and (2) compressing the test set using the proposed code. The detail of each procedure is as follows: (1) Reordering the test set TIR : The sequence of the reduced test set TIR which is mapped to specific values is reordered so that the compression block occurs more frequently. Initially, in this procedure, first test sequence TIR1 is prepared as the initial test sequence and then TIR1 is divided into 4-bit blocks and 2bit blocks according to whether the divided 4-bit block is the CB or not. If there is the remaining block rb1 in TIR1 (rb1 3bits) and a filling block fb2, which the compression block is generated by adding rb1 to, is found in the other sequences, this sequence which includes the filling block fb2 become the second test sequence TIR2. Otherwise, original second test sequence TIR2 is prepared for the reordering procedure. For entire sequence k (1 k L-1), repeating the same steps mentioned above, the occurrence frequency of the compression block in TIR can be much higher. (2) Compressing the test set using the proposed compression code : The reduced and reordered test set TIR is compressed by the proposed compression code proposed in Section 3.1. This procedure is to make the compression block {CB} which occurs most frequently have a one-bit code, and the uncompression block {UB1, UB2, UB3, UB4} have 3-bit codes which consist of a 2bit original block and a prefix bit to identify uncompressed 2-bit blocks. Let N = {nCB, nUB1, nUB2, nUB3, nUB4} be the number of occurrence of the test set TIR. Total number of the compressed test data is

control the buffering and the loading of data into the controller when the data has been decodes and the synchronization of the ATE. An example of the state diagram for the FSM decoder of the proposed code is shown in Fig. 3.

Figure 3. The state diagram of FSM decoder The controller to transfer the decoded test data into scan chains in the CUT and to control the signals between the ATE and the FSM decoder is illustrated in Fig. 4. Note that the clock signal Clk in Fig. 4 is the same as the test clock. The controller for the proposed compression method consists of the serializer to shift the decoded data into scan chains, which is synchronous with the test clock, the scan clock, and the part to match the clock for the FSM decoder to the test clock.

Figure 4. The proposed decompression architecture

Experimental Results

nCB +

i =1

3 nUBi .

3.4

The Decompression Architecture

Once the proposed code has been chosen, then a FSM decoder for the proposed compression code is synthesized. There are two inputs to the decoder, one is the ATE clock and another is the input for transferring the compressed test data from the ATE channel. Outputs for the FSM decoder consists of a data output to transfer original test sets to scan chains in a CUT and three control outputs. The three control signals are Parallel, Serial, and Wait. These signals

To demonstrate the efficiency of the proposed method, the performance of it is analyzed on the larger ISCAS 89 benchmark circuits. The proposed scheme is implemented in C and experiments are performed on a Pentium 3 667MHz system with the Linux. The test set for each circuits is generated by MinTest[14] in order to compare previous schemes. In addition, although the experimental results of previous works, SC[15], Golomb[8], FDR[7], VIHC[10] and SHC(Selective Huffman Coding)[16], show different compression ratios according to the group size, we use the group size for which [10] reports the best results. In addition, the block size for the SHC in [16] is 12 and the block size of the proposed compression code is fixed to 4. We use the original test data set TD, while the

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difference test sequence set Tdiff is used in the methods using Golomb[8], FDR[7] and VIHC [10] in order to make the best compression ratio. Note that the compression ratio is computed as follows.

Table 2. The power consumption reduction ratio (%)

Circuits s5378 s9234 s13207 s15850 s38417 s38584 Group size 4 4 16 4 4 4 The reduction ratio of the average power 89.18 88.28 89.89 94.88 86.60 78.78

compression ratio =

TIR Tcomp TIR

100

(6)

where Tcomp is the size of the compressed test set The results of the compression are presented in Table 1. As shown in Table 1, test data for ISCAS 89 benchmark circuits are more highly compressed in the proposed method. Since test data are compressed by reducing redundant testing inputs using the input reduction scheme, in the proposed compression method, the compression ratio is better than that of other previous approaches in most circuits. However, the results of two circuits, s9234 and s13207, do not show the best compression ratio due to the scan flip-flop reordering for low power test. As mentioned before, since the problems between the test data compression and the low power test are irreconcilable, the tradeoff between two problems is required. Table 1. The compression ratios for ISCAS '89 benchmark circuits
Circuits s5378 s9234 s13207 s15850 s38417 s38584 Group size 4 4 16 4 4 4 SC [15] 56.95 51.82 63.81 62.90 71.19 67.78 Golomb [8] 60.53 66.56 66.29 65.63 69.82 63.70 FDR [7] 69.04 66.59 67.06 77.14 72.50 68.50 VIHC [10] 60.64 57.15 76.36 65.69 74.90 63.60 SHC [16] 65.1 64.2 87.0 76.0 69.0 74.1 Proposed 76.64 76.14 86.20 85.44 82.28 83.53

Table 2 shows that the average power is significantly reduced if the proposed method is used for test data compression and decompression. In addition, using Golomb[8], FDR[7] and VIHC[10] methods, more power consumption during testing is required actually, because the CSR architecture is used. Therefore, our experimental results demonstrate that the significant reduction in power consumption during scan testing, as well as the substantial reduction in test data volume, is accomplished by using the proposed method. Table 3. The comparison of the area overhead for the decoder
Circuits

Area of the circuit with a single scan chain 2704 3361 7965 7672 22841 23236

SC [15] 11.43 9.4 10.15 4.35 1.5 1.47

Golomb [8] 4.41 3.58 3.71 1.6 0.54 0.53

FDR [7] 10.58 8.69 3.86 4 1.38 1.35

VIHC [10] 4.78 3.88 3.58 1.74 0.59 0.58

SHC [16] 21.55 18.10 8.53 8.82 3.15 3.09

Proposed 3.87 3.14 1.35 1.40 0.47 0.46

s5378 s9234 s13207 s15850 s38417 s38584

We present results on the reduction ratio of the average power consumption during the scan in and the scan out operation. These results show that the proposed test data compression scheme can also lead to significant savings in power consumption. As described in Section 2, we estimate the average power using the weighted transition metric. Let PTD be the average power with compacted test sets obtained using MinTest [17]. Similarly, let Pproposed be the average power when the proposed coding is used by reordering scan flip-flops and mapping the X values in TD for low power test. Note that the Tdiff in previous works is the same test vectors as TD when the Tdiff test vector is decompressed in test mode. Therefore, we consider the TD for the comparison of the power reduction. Table 2 shows the reduction of the average power consumption for MinTest sets with TD when the proposed compression coding is used. The percentage reduction in power is computed as follows:
power reduction ratio = ( PTD Pproposed ) PTD 100

Next, the area overhead of the decoders for the different compression methods is compared in Table 3. The ISCAS 89 benchmark circuits are synthesized with a single scan chain and a single scan chain in the benchmark circuit is inserted by the DFTadvisor of the Mentor Graphics with the class library. The area overhead of the decoder is computed as follows.
decoder area overhead = the area of decoder 100 (the area of benchmark circuit + the area of decoder )

(8)

The area is computed by the Synopsys Design compiler with the class library. Note that the decoder for each compression scheme is configured by the parameter, the group size, shown in Table 1. The column 2 in Table 3 is the area of benchmark circuits without the decoder. As shown in Table 3, the decoder of the proposed code has the lowest area overhead. Furthermore, for Golomb[8], FDR[7] and VIHC[10], the area overheads in Table 3 exclude the area overhead for the CSR architecture. As mentioned before, it is inevitable that the high area overhead for the CSR architecture is required. Therefore, the

(7)

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proposed method is an effective solution of the test data compression/decompression for SoCs.

Conclusions

In this paper, we propose a new test data compression method for low power testing using the input reduction. Unlike previous works using the different test sequence Tdiff, using the original test data TD, a simple decompression architecture with low hardware overhead is achieved in our approach. Instead of Tdiff, the input reduction scheme is used in order to identify redundant inputs for testing and by the input reduction we obtain effectively compressed test data without any loss of test data information and the reduction of the power consumption during scan testing. In addition, reordering scan flip-flops is proposed to reduce the power consumption during the scan out operation as well as the scan in operation. Then the compressed test data TIR is compressed again by the proposed compression code. The decompression architecture for the proposed code is simple and small since it has a simple decoding process. Therefore, the area overhead for our approach is much lower than that of previous approaches. Therefore, as shown in experimental results, the proposed approach is an attractive and effective solution of test data compression/decompression for low power test.

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