COVENTRY UNIVERSITY Faculty Of Engineering & Computing CDE Interfacing with Analogue to Digital Converters (ADCs)

Introduction
Our world is analogue. All the physical variables around us such as temperature, pressure, displacement, light intensity etc are analogue. The usual method of reading analogue inputs into a microprocessor is to use an Analogue-to-Digital Converter (ADC). This device accepts a voltage or current and converts it to a digital value that can be read by the computer/microprocessor.

Fig 1
An ADC can be a single stand alone single IC device or part of a multifunctional data acquisition board that can be interfaced to a microprocessor or a computer. However many modern microcontrollers including the PIC18F4520 include an on-chip multi-channel ADC.

Types of ADCs

ADCs come in various speeds, use different interfaces and provide differing degrees of accuracy. The most common types of ADCs are flash, successive approximation, and sigma-delta.

Some Basic Definitions of ADC Data Terms

Number of bits:
Is the number of the digital output bits (4, 8, 12, 14, 16)

Resolution (Size Step):

Is the smallest analogue increment corresponding to 1 Least Significant Bit (LSB) converter code change. Resolution is expressed in bits. The number of digital codes is equal to 2n where n is the number to bits. For example an 8-bit converter maps the analogue signal to 28=256 digital codes. The table below shows a comparison chart of resolution compared to the number of bits of the ADC when the ADC uses a reference voltage Vref of 5volt. Number of Bits 8 10 12 16 Number of steps (NOS) 256 1,024 4,096 65,536 Step size (resolution in mvolts) Vref/NOS 5/256 = 19.5 mV 5/1024 = 4.8 5/4096 = 1.2 5/65536 = 0.076

Table 1 shows the resolution of 8-16 Bit ADCs when the Reference voltage is 5Volt Full Scale Input Range:
Is the input range of voltages over which the ADC will convert the analogue input.

Conversion time:
Is the time required complete the conversion of an analogue input to a digital output. The conversion time is determined by the clock source to the ADC as well as the fabrication process involved in making the device.

Quantization Error:
This is an inherent error in all AD conversions. Since even the ideal ADC has finite resolution, any analogue voltage that falls between two adjacent output codes will result in an output that is inaccurate up to LSB.

V ref (Voltage Reference):

The Vref is an input voltage reference that provides an accurate and stable point for the ADC conversions. For an 8-bit ADC the step size is Vref/256 as seen in Table 1. If the analogue input needs to be in the range of 3 volt, the Vref to the ADC should be 3v. This will give a step size for an 8-bit ADC of 3/256 = 11.7 mV. If now we wanted a step size of 10mV for our 8-bit ADC Vref should be 2.56/256 = 10 mV.

Other important parameters of the ADC that have to be mentioned in here are the analogue input channels and the Start and End-Of-Conversion signals.

Analogue I/P channels.

Quite often there are applications whereby we need more than one ADC. There is a variety of ADC ICs that offer a multichannel device with 2, 4, 8, 16 input channels on a single IC. A large number of microcontrollers also offer a multichannel arrangement. Our PIC18F184520 used is used in this exercise has a 13-channel on-chip ADC. Start Conversion and End-of-Conversion signals When the Start Conversion signal is issued to the ADC the conversion process is initiated and the ADC starts converting the analogue input signal to an n-bit digital number. The time taken for conversion is depends on the ADC clock and the fabrication process involved in making the device as already mentioned. When the conversion is complete the End-of-Conversion signal notifies the CPU or other controlling device that the data is now ready to read. A stand-alone ADC IC will have the Start conversion (SC) and End-Of-Conversion pins that could be controlled by externally connected devices. In our PIC18 and other microcontroller environments where the ADC is a part of the microcontroller the Start Conversion is controlled by writing specific information to the appropriate register while the End-Of-Conversion is signalled as flags set in associated registers or interrupt conditions(see later)

The PIC18 ADC system Introduction

The PIC18 ADC system is a complex and powerful. It can be used to convert up to 13 different 10-bit analogue channels (PIC18F4520 & PIC18F4420). A simplified block diagram of the ADC PIC18 module is shown in Fig 2.

Table 2 Some of the PIC18 devices and their peripherals (ADC channels highlighted)
A simplified block diagram of an ADC data acquisition system is as shown in Fig. 2. It shows a four channel transducer arrangement connecting to the various essential system components.

The signal conditioning blocks: To make best use of the ADC the input voltage should be of
the appropriate level. As the transducer outputs produce very small outputs there is a need to condition these signals to levels acceptable by the ADC. Sometimes level shifting may be also required, for example if the signal is of a bipolar nature and the ADC input is of a unipolar nature. If the input signal is periodic we must observe the Nyquist sampling criteria (conversion rate must be at least twice the highest signal frequency and therefore anti-aliasing filtering may be required).

The Analogue Multiplexer : If there is a number of analogue inputs an analogue multiplexer is

used to connect one channel at a time to the ADC. The alternative to this is to use multiple ADCs.

The multiplexer channel selection is done by using a set of semiconductor switches controlled by a micro or other external device. Sample & Hold: A very fast changing analogue input can present conversion problems to the ADC. For this reason a Sample & Hold circuit is used to take a snapshot of the input voltage and hold it steady for the duration of the conversion. A simple circuit of sample & hold is a semiconductor switch with a capacitor. The output of the sample & hold is the input to converter which generates the result via successive approximation.

Fig.2 A simplified block diagram of a data acquisition system A simplified PIC18 ADC system

Fig 3 PIC18F simplified ADC system 4

Features of the PIC18F4520 ADC module

The micro contains a 13 channel ADC (PIC18F45200 10 channels for 28-pin devices) of a 10-bit resolution. It allows for a software selectable analogue reference to the devices positive and negative supply voltage, VDD and Vss or an external voltage reference on PIN4 and PIN5 of the PIC18F4520. For a simple design the VREF- is Vss and VREF+ is VDD

The PIC18 ADC Module

The ADC module of the PIC18 has five registers which control the operation of the ADC. These are as follows: A/D A/D A/D A/D A/D Result High Register Result Low Register Control Register 0 Control Register 1 Control Register 2 (ADRESH) (ADRESL) (ADCON0) (ADCON1) (ADCON2)

The A/D Control Register 0 ADCON0 The ADCON0 register is used to set the conversion time of the analogue input channel as well as the enabling and the start conversion process of the ADC. In order to minimise the power consumption of the PIC18 the ADC feature is disabled when the micro is initially powered up. In order to enable the ADC module the ADON (Bit 0) of the ADC control register 0 ADCON0 needs to be set (See Fig. 4). The ADC conversion process is started by setting the GO/Done bit 1 of the ADCON0. We can monitor the completion of the conversion process by examining the same bit. If the conversion has been completed this bit is cleared ( logic 0 ). Please note that some other members of the PIC18 family have slightly different configuration settings. Bits 2 -5 of ADCON0 select the appropriate ADC channel by simply setting and clearing the corresponding channel selection bits. See Fig.4 .

Fig .4
Bit 7 -6 Bit 5-2 Not used Read as 0 Are the channel selection bits CHS3 CHS0 and are as follows: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 = = = = = = = = = = Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel 0 1 2 3 4 5 6 7 8 9 (AN0) (AN1) (AN2) (AN3) (AN4) (AN5) (AN6) (AN7) (AN8) (AN9)

1010 1011 1100 1101 1110 1111

= = = = = =

Channel 10 (AN10) Channel 11 (AN11) Channel 12 (AN12) Not available Not available Not available

Bit 1 GO/DONE: is the Status bit of the ADC as well as the Start conversion signal. When = 1 A/D conversion is in progress. (This is used as start conversion. It will go Low to indicate the end of conversion). When = 0 A/D is Idle, conversion is complete and digital data is available in the ADRESH and ADRESL registers. Bit 0 ADON: Enables/Disables ADC module When = 1 A/D is enabled When = 0 A/D is disabled The default setting of ADON is Low and should be left Low if the ADC is not used.

The ADCON 1 Register

The ADCON1 register is used to select the reference voltage to the ADC (VREF) amongst other things. It is shown in Fig.5. The ADC takes the ratio of an input voltage to a reference voltage and represents it as a number. This number depends on the resolution of the ADC. Our PIC18 device has a 10-bit resolution which means that 1024 numbers from 0 1023 are available to represent this voltage ratio. The following equation demonstrates this: ADC value = (Vin/ VREF) x 1023 If Vin = 2.5 volts and VREF=5 volts the ADC value will be: ADC value = (2.5/5) x 1023 = 511. This is half of 1023 which shows that our input voltage (Vin =2.5) is half of the reference voltage (VREF =5) If we solve the above equation for Vin we could also convert the ADC value back into a voltage: Vin = (ADC value/1023) x VREF Bits 4 and 5 of the ADCON1 register are used for the selection of the ADC reference voltage. This is shown in Fig.5. The ADC of the PIC18 can be referenced to an internal or an externally connected VREF voltage. Bits 0 4 of this register control the function of the port pins as analogue inputs or Digital I/O pins.

Fig .5
Bit 7 -6 Bit 5 Not used, Read as 0

VCFG1: Voltage Reference Configuration Bit (VREF source)

1 = VREF- (AN2) External ve reference provided by AN2 0 = Vss Internal ve reference set to Vss

Bit 4

VCFG0 : Voltage Reference Configuration Bit (VREF+ source)

1 = VREF+ (AN3) Externally supplied reference provided by AN3 0 = VDD Internal +ve ref VDD (The analogue reference voltage is software selectable to either the devices positive and negative supply voltage or the voltage level on the RA3/AN3/ VREF+ and RA2/AN2/ VREF-/CVREF pins). Bit 3-0 PCFG3 PCFG0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

PCFG3 PCFG0: A/D Port configuration Control bits.

AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0

A A A D D D D D D D D D D D D D

A A A A D D D D D D D D D D D D

A A A A A D D D D D D D D D D D

A A A A A A D D D D D D D D D D

A A A A A A A D D D D D D D D D

A A A A A A A A D D D D D D D D

A A A A A A A A A D D D D D D D

A A A A A A A A A A D D D D D D

A A A A A A A A A A A D D D D D

A A A A A A A A A A A A D D D D

A A A A A A A A A A A A A D D D

A A A A A A A A A A A A A A D D

A A A A A A A A A A A A A A A D

A = Analogue Input

D = Digital I/O

The ADCON2 Register

The ADCON2 register is used to set the formatting of the 10-bit ADC result in the two 8-bit registers (ADRESH and ADRESL) , to select the ADC acquisition time and the ADC conversion clock. Bit 7, ADFM, of the ADCON2 is used to Right or Left justify the converted ADC values in the result registers. Remember that we have a 10-bit ADC result stored in the two 8-bit result registers ADRESH and ADRESL (see Fig.7). By setting the ADFM bit to logic 1 we select the Right justified result option. This means that the higher 2 bits value will be placed in the ADRESH register and the lower 8 bit value is in the ADRESL register. When a specific ADC channel is selected the analogue input voltage to this channel is stored in the internal sample and hold capacitor circuit. It will take some time for the capacitor to reach the same level as the analogue voltage applied to this channel. This time is called the Acquisition Time. Once acquisition time is reached the input channel is disconnected from the analogue source and the conversion begins. As a rule of thumb a safe acquisition time should be higher than 2.5uS. (See data sheet for more details). The PIC18 ADC system requires a clock to do the conversion. This is called the ADC clock. The time period of the ADC clock is called TAD. It is also the time required to create a 1-bit conversion. The ADC requires 11 TAD to perform a 10-bit conversion. In order for ADC circuit inside the PIC18 microcontroller to meet its specified accuracy the ADC clock period (ADCS) and the ADC acquisition time (ACQT) should be set accordingly. The bits that control these setting are part of the ADCON2. The PIC18s ADC provides for a programmable acquisition time. Acquisition time may be set with ACQT0 ACQT2 bits which provide a range of 2 to 20 TAD. When the GO/DONE bit is set the A/D module continues to sample the input for the selected acquisition time, and then automatically begins a conversion. As the acquisition time is programmed there is no need to wait for an acquisition time between selecting a channel and setting the start conversion bit GO/DONE. In a manual acquisition mode bits ACQT0 ACQT2 are cleared to 000. When the GO/DONE bit is now set, sampling is stopped and a conversion begins. The user must make sure that the required acquisition time has passed between the selection of the desired input channel and the setting of the GO/DONE bit. When the conversion has been completed the GO/DONE bit is cleared and the A/D begins sampling the currently selected channel again. If the acquisition time is programmed, there is no indication that the acquisition time has ended or if the conversion has begun. The ADC clock is derived from the CPU clock known as Fosc and is further divided by an appropriate division factor. There are seven possible options in deriving the ADC clock as shown below: 1. 2. 3. 4. 5. 6. 7. Fosc / 2 Fosc / 4 Fosc / 8 Fosc / 16 Fosc / 32 Fosc / 64 Internal RC Tosc Tosc Tosc Tosc Tosc Tosc x x x x x x 2 4 8 16 32 64

For a correct ADC operation the appropriate ADC clock has to be configured. From the PIC18 data sheets (table 25-26 for PIC184520) the ADC clock must be as short as possible but greater that the minimum TAD which has a value of 0.7uS. Our PIC18F target runs at 20MHZ, ideally we have to set the ADC clock with a 32 X Tosc prescaler. The calculations are as follows: For a Fosc = 20MHZ TFosc = 1/20 MHZ = 50ns 32 Tosc = 32 x 50ns = 1600ns = 1.6uS

1.6 uS is higher than the minimum requirement of 0.7uS We will also need to select the acquisition time TACQ in terms of TAD. The following settings are available: 20 16 12 8 6 4 2 0 x X X X X X X X TAD TAD TAD TAD TAD TAD TAD TAD

As we saw before a safe TAD is above 2.5uS so selecting an acquisition time 2 x TAD we have: TACQ = 2 x TAD = 2 x 1.6uS = 3.2 uS We can also use the internal RC oscillator for the conversion clock source instead of the Fosc of the external crystal oscillator. In this case the TAD is between 4-6 ms and the conversion time is 11 x 6 us = 66us. The PIC18 microcontrollers ADC peripheral is also capable of generating interrupts when it completes the conversion by setting the ADC interrupt flag ADIF bit to logical 1 in PIR1 register.

Fig.6

Bit 7 ADFM : A/D Result Format Select bit 1 = Right justified 0 = Left justified Bit 6 Not used: Read as 0 Bit 5 - 3 ACQT2 ACQT0 : A/D Acquisition Time Select bits 000 001 010 011 100 = = = = = 0 2 4 6 8 TAD TAD TAD TAD TAD

101 = 12 TAD 110 = 16 TAD 111 = 20 TAD Bit 2 0 ADCS2 ADCS0: A/D Conversion Clock Select bits 000 001 010 011 100 101 110 111 = = = = = = = = FOSC/2 FOSC/8 FOSC/32 FRC (clock derived from A/D RC oscillator) FOSC/4 FOSC/16 FOSC/64 FRC (clock derived from RC oscillator)

Fig. 7 Left and right justification of the ADC result

Basic steps in configuring and using the PIC18 ADC.

The following steps should be followed to perform an A/D conversion. 1. Configure the A/D module: Configure analogue pins, voltage reference and Digital I/O through ADCON1, (VCFG0-1) (PCFG0-3) Select the A/D input channel through ADCON0, (CHS0-3) Select the A/D acquisition time through ADCON2 (ACQT0-2) Select the conversion clock through ADCON2 (ADCS0-2) Turn on the ADC through ADCON0, (ADON) 2. Configure the AD interrupt if required: Clear ADIF (AD interrupt Flag) Set ADIE (AD Interrupt Enable) bit Set GIE (Global Interrupt Enable) bit 3. Wait for required acquisition time if required:

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4. Start the conversion: Set the GO/DONE bit in ADCON0 register 5. Wait for the A/D conversion by either: Polling the GO/DONE bit when clear OR Waiting for an interrupt (if used) 6. Read A/D result registers ADRESH and ADRESL Clear interrupt flag ADIF if interrupts are used 7. For the next conversion go to step 1 or 2 as required. The required conversion time per bit is defined as TAD. The minimum wait of 2 TAD is required before the next acquisition starts. The value in the ADRESH and ADRESL registers is not modified on a Power-on-Reset and will contain unknown data. After the A/D module has been configured as desired the selected channel must be acquired before the conversion is started. The analogue input channels must have their corresponding TRIS bits selected as inputs.

EXPERIMENTATION Apparatus

PC with MPLAB V5.6 or higher and USB port ICD 3 and USB lead 5 volt fixed PSU and connecting leads Digital Voltmeter (DVM) PIC18F4520 Target board ADC Potentiometers board and IDC10 way connecting cable PIC18 Prototyping board and 10way ICD connector, 2-way connecting lead for Port B 10-LED Bargraph display 2 x 270R resistors Connecting wire links

Fig.8 System schematic

The resistor network RN1 is already on your PIC Port I/O board. The bargraph LED and resistors R1 & R2 should be added on your breadboard 11

Fig 9 Potentiometer O/B

Fig.9 shows the potentiometer Outboard that is used to simulate the analogue inputs to the ADC. A connecting wire link is required if the potentiometer is to be used as the analogue input. If the analogue input is from an external sensor the link is not required and the sensor o/p is connected to the appropriate pin at the right hand-side of the row of sockets. An external Vcc source is required for producing the variable Vin voltage from the potentiometers. If an external Vref+ and Vref- reference voltage is to be used these should be connected to the right-hand-side of the 2 pins labelled Extern Refer while the left-hand-side of the pins should be connected to the appropriate AN(x) pin of port A. Please ask for advice if you need to use this option.

In the example that follows we will use a single analogue input channel AN0 as our Analogue input. This will be through a variable resistor connected via the potentiometer outboard as shown in Fig.9. The converted digital output will be displayed on Ports D (Least significant value) and Port B (Most significant 2 bits of the 10-bit result). The reference voltage to the A/D will be internally selected: VREF+ is VDD (+5 volt in our example) and VREF- is Vss ( 0 volt in our example). System connections are as shown in Fig.10.

PB0 & PB1

Fig.10 System connections 12

ADC Example 1 Assembler version

;**************************************************************** ; ; Filename: ADC Example.asm ; Date: 22/10/10 ; File Version: 1.0 ; ; Author: PDA ; Company: Coventry University ; ; Program Function: ADC Example PIC18F4520 ; The program gets an analogue input connected to AN0 (RA0) of the ADC and ; displays the 10 bit digital value on ports D (Least significant) & B (Most) ;******************************************************************* ; * ; Files Required: P18F4520.INC * ; * ;******************************************************************* LIST P=18F4520 #include <P18F4520.INC> ; directive to define processor ; processor specific variable definitions

;********************************************************************** ; CONFIGURATION BITS ; (Microchip has changed the format for defining the configuration bits, please ; see the .inc file for further details on notation). Below are a few examples. ; ; ; ; Oscillator Selection and other fuse settings: CONFIG CONFIG CONFIG CONFIG CONFIG OSC MCLRE DEBUG LVP WDT = = = = = HS ON OFF OFF OFF ;High Speed clock ;MCLR enabled ;Background debugger disabled, RB6 and RB7 ; Low Voltage Programming OFF ; WDT disabled

;************************************************************************ ; RESET VECTOR ; This code will start executing when a reset occurs. ORG GOTO Main CLRF CLRF BSF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BSF BTFSC BRA MOVFF MOVFF BRA END 0x0000 Main TRISD TRISB TRISA,0 B00001110 ADCON1 0x01 ADCON0 B10110010 ADCON2 ADCON0,GO ADCON0,DONE READY ADRESL,PORTD ADRESH,PORTB START ; ORG Directive ;go to start of main code ;Port D O/P (for displaying 8 least significant value) ;Port B O/P (for displaying bits 9 &10) ;Make RA0 an I/P for analogue input ;Vref+ is Vdd Vref- Vss, AN0 is analogue input Channel 0 ; ;Channel Select 0 (AN0), Enable ADC (ADON = 1) ; through ADCN0 register ;Right justified result 16 ATD acquisition time ,clock Fosc/32 ;Start the ADC by setting the GO bit to logic 1 ;Test the DONE bit of ADCON0 , if @ logic 0 (done) skip to next instr. ; if @ logic 1 go back and read the flag again ; Send least significant ADC value to Port D ; The two Most Significant bits display on Port B ; Repeat the conversion process again

START READY

The following figures give a full account of the register settings associated with our example:

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Voltage reference configuration and PORT function selection as Analogue or Digital I/O.

VCFG1 = 0 , VCFG0= 0 selects Vref- to VSS (0 volt) and Vref+ to VDD (+5v) PCFG3, PCFG2, PCFG2 & PCFG 1 = 1 AN12 AN1 is set as Digital I/O pins PCFG0 = 0 selects AN0 as Analogue Input. Channel selection and ADC enable settings (throughADCON0)

All Channel selection bits are cleared selecting Analogue channel AN0 The ADC module is enabled by setting ADON bit to 1. ADC Result format , Acquisition time and ADC Clock selection (through register ADCON2): Our settings are as follows:

ADFM (AD result Format) is set to logic 1 , ADC result is Right Justified , 8 Least Significant bits of result in ADREL and 2 Most Significant bits of the result in ADRESH. ACQT2 , ACQT1 = 1 , ACQT0 = 0 sets A/D Acquisition time to 16 TAD ADCS2 = 0 , ADCS1 = 1 , ADCS0 = 0 selects ADC clock to Fosc/32

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Starting the ADC and testing for conversion complete. Setting the GO/DONE bit of ADCON0 will initiate the conversion. On completion of the conversion process this will be automatically cleared ( logic 0) thus indication that the conversion has been completed.

ADC Example 1 C MCC18 version

The example that follows shows the C version of our previous ADC assembler example. You will need to study and understand the ADC library functions for the ADC module in the MCC18 library documentation ( section2.2) http://web1.eng.coventry.ac.uk/Panos/Info/Micros/PIC/C_Compilers/C18%20Compiler%20Student/M PLAB_C18_Libraries_51297f.pdf
/* ADC Interfacing example for 10-bit ADC*/ /* The following example shows the procedure of setting up and using the PIC ADC */ /* PIC ADC Ch 0 is used as the Analogue i/p. All 10 bits are shown on Ports D (0-8) and Port B (bits 9 and 10) */ #pragma #pragma #pragma #pragma #include #include #include #include config OSC = HS /* set osc mode to HS */ config WDT = OFF /* set watchdog timer off */ config LVP = OFF /* Low Voltage Programming Off */ config DEBUG = OFF /* Compile without extra Debug compile Code */ <p18f4520.h> <adc.h> <stdlib.h> <delays.h> /* Device used is the PICF452 */

void main (void) { /*Set PORT B as Digital Outputs to display only the 8 LSB ADC values*/

TRISB = 0x00; TRISA = 0xFF; TRISD = 0X00;

/* Configure Port B as O/P */ /* Configure Port A as I/Ps for ADC */ /* Configure Port D as all O/P */

/* Configure the ADC */ /* The following configure the ADC module operational mode */ /* OpenADC configures the operation of the ADC with a number of arguments /* /* /* /* /* /* /* ADC_FOSC selects the ADC clock source and has a number of set values ADC_RIGHT_JUST select ADC result justification */ ADC_0_TAD sets the A/D acquisition time select */ ADC_CH0 select Channel 0 */ ADC_INT_OFF Interrupts are disabled */ ADC_VREFPLUS_VDD set ADC + reference voltage configuration to VDD ADC_VREFMINUS_VSS set ADC - reference voltage configuration to VSS

*/ */

*/ */

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/* 0b1011 are the A/D control Register 1 config bits setting the reference and function of port bits

*/

OpenADC(ADC_FOSC_32 & ADC_RIGHT_JUST & ADC_20_TAD,ADC_CH0 & ADC_INT_OFF & ADC_VREFPLUS_VDD & ADC_VREFMINUS_VSS, 0b1011); SetChanADC(ADC_CH0); ConvertADC( ); while(BusyADC( )); /* Get results and store at Ports D & B */ LATD = ADRESL; LATB = ADRESH; CloseADC( ); } /* Selects the pin used as i/p to the */ /* start A/D conversion */ /* wait for completion */

/* Results Register Low displayed, least sign on Port D */ /* Results Register High displayed on Port B */

Exercise 1

Using either the assembler or the MCC18 version of the previous example modify the code so that you are now using Channel 1 as your analogue input. This time, left adjust your ADC result on Port B ( Least Significant value) and D ( Most Significant value). Please note that you will have to make the appropriate changes to your system connections.

Exercise 2

Using either the assembler or the Compiler carry out the following task. Choose your own analogue input channel and your preferred result justification. Continuing from the previous example or exercise connect a voltmeter across your chosen ADC channel. Adjust the potentiometer for a DC voltage of 0 volts. Finely adjust the potentiometer now so that your Least significant output port displays the digital value of 00000001 ($01). Make sure that you adjust the range settings of your DVM so that you can precisely measure small voltage values. Make a note of the voltmeter reading and repeat the process for the next incremental digital steps up to the digital value of 00001000 ($08). Comment on your readings and their significance. Repeat the above process but this time takes measurements for digital values from $000 to $03FF for 20 evenly distributed readings. From these readings draw a graph of Analogue Input versus Digital Output. Comment on your results.

Exercise 3
Four analogue sensors are connected to A/D ports Channels0 - 3. These will be simulated by the use of the 4 potentiometers on the potentiometer board. Preset these potentiometers to different analogue settings. Write, assemble OR compile and execute a program that reads the analogue inputs from these four sensors, displays their digital representation one at a time on Ports D and B with an appropriate time delay between the displayed values.

P Abatis ADC PIC18 V1.1

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APPENDIX

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