A common ASIC digital design flow can be summarized into the following points: 1.

Feasibility study - During this step it's necessary to investigate all critical points and to provide all analysis needed to be able finish the project successfully. 2. Specifications - It's necessary to negotiate with the customer about a final product. The technical part of the agreement must be a specification and it is used as a communication channel with a customer. The specification has to include a description of a functionality, all timings, electrical parameters and chip dimensions. This document must be agreed by both sides of the contract. On the basis of the specification a system level analysis a design specification and verification plan are created. The design specification defines splitting of functionality into blocks, their interfaces, testability requirements and all functionality requirements for a designer. According to the design specification a designer can start with an implementation. 3. Implementation - There are used programming languages for a hardware description like VHDL, Verilog, SystemC etc. or their combination. The level of the hardware description is usually RTL (Register-Transfer-Level). This description level can be easily translated to an equivalent hardware implementation by common synthesis tools. 4. Functional verification - The goal of this task is to cover all requirements which are defined in the verification plan. At the beginning a "testbench" is created. This testbench includes RTL design (DUV - Design Under Verification), surrounding blocks as models, stimuli generator and monitors. The latest challenge is usage of "assertions" for verification. If testbench is created then testcases are prepared and regressions can be started. 5. Synthesis - The goal of the synthesis is to translate RTL design to the target technology library (RTL to gates) and prepare it for Place & Route. In case of sub-micron technologies and large designs it's necessary to do both steps at the same time (physical synthesis). 6. Place & Route - During this step the obtained result (netlist + constrains) from synthesis is used as input. There are defined dimensions of area and pin positions then the netlist with genarated clock-tree is read and cells placed a then connections routed in some incremental steps. As output are generated parasitic (timing) information for following step (Static Timing Analysis). The process is not so simple as I described above but enough for rough approximation. 7. Static Timing Analysis - The goal is to check if all timing constraints are passing postlayout digital netlist. Following parameters are checked: setup time, hold time, recovery violations, input and output delays.

8. Timing Simulations - One of the possibilities how to verify post-layout netlist is to simulate this netlist with SDF file. It's usually possible to run simulation in case of "small" designs, mainly for asynchronnous designs where STA is difficult. 9. Formal Verification - This step is applied by contrast in case of large designs to check if final (post-layout) netlist is equivalent to RTL (VHDL, Verilog) sources. 10. Chip Assembly - During this step are all blocks connected on the top-level of the chip. Analog and digital block's layouts are placed on the chip according to a chip floorplan and connections routed. The last but not least steps are DRC and LVS checks. GDS files goes to the maskshop. 11. Manufacturing - Here is the time when real chip are borning. Our chip can be placed on MPW (Multi-Product-Wafer) with other chips or on "dedicated". MPWs are usually meant for test chips in case of first run. Dedicated is used during real production. 12. Evaluation and qualification - Then samples are measured in specified conditions and all tests must pass. If all evaluation steps passed and It's not necessary to fix something in a design then production can start. 13. Production - During this stage a real production of chips is running.