Douglas Slade ECEN 260 Lab 1 9/17/12

Goal of Lab:
The Goal of this lab was to get the student reacquainted with the BYUI microprocessor which they had created in ECEN 160. This included relearning the processors instruction set, implementing the machine code used by the processor, and finally modifying the instruction set and processors design to implement a 1Kb RAM unit used to store data.

Schematics:
CS

U19 PROM32
O7 O6 O5 O4 O3 O2 O1 O0

U9 4024
CP MR

Ram Test
CS O7 O6 O5 O4 O3 O2 O1 O0

CS

PROM2 PROM32
O7 O6 O5 O4 O3 O2 O1 O0

Q6 Q5 Q4 Q3 Q2 Q1 Q0

A4 A3 A2 A1 A0

A4 A3 A2 A1 A0

A4 A3 A2 A1 A0

DISP1
7 6 5 3*3=9 4 3 2 1 CP

A3 COUT A2 A1 S3 A0 S2 B3 S1 B2 S0 B1 B0 CIN

U2 4008

A3 A2 A1 A0 B3 B2 B1 B0 SA SB

REG3 4019
Q3 Q2 Q1 Q0

A3 A2 A1 A0 B3 B2 B1 B0 SA SB

REG4 4019
Q3 Q2 Q1 Q0 CS

3+4=7
O7 O6 O5 O4 O3 O2 O1 O0

U3C U3D U5A U5B

A4 A3 A2 A1 A0

CP1 Q1 CP2 Q2

U6A
A3 A2 A1 A0 B3 B2 B1 B0 SA SB

A3 A2 A1 A0 B3 B2 B1 B0 SA SB

REG1 4019 U1
Q3 Q2 Q1 Q0 D0 D1 D2 D3 Q0 Q1 Q2 Q3

A3 A2 A1 A0 B3 B2 B1 B0 SA SB

REG2 4019
Q3 Q2 Q1 Q0 CS

3*3=9
O7 O6 O5 O4 O3 O2 O1 O0

REG5 4019
Q3 Q2 Q1 Q0

CP

U7A U7B U7C

A4 A3 A2 A1 A0

CS

Hello
O7 O6 O5 O4 O3 O2 O1 O0

U27F U3A

U3B

U27D

A3 A2 A1 A0 B3 B2 B1 B0 SA SB

REG0 4019 U4
Q3 Q2 Q1 Q0 D0 D1 D2 D3 Q0 Q1 Q2 Q3

U7D U10A U10B U10C

A4 A3 A2 A1 A0

CP

REG6 4019
Q3 Q2 Q1 Q0

A3 A2 A1 A0 B3 B2 B1 B0 SA SB

U12D U27E

A3 A2 A1 A0 B3 B2 B1 B0 SA SB

ACCUM 4019 U11

Q3 Q2 Q1 Q0 D0 D1 D2 D3 Q0 Q1 Q2 Q3

U10D

U12A U12B

CP

U17 4019 U15

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 WE CS

U16
O0 O1 O2 O3 I0 I1 I2 I3

Q3 Q2 Q1 Q0

A3 A2 A1 A0 B3 B2 B1 B0 SA SB

OE

U12C

RAM1K U20A

U12E

Test Plan:
The test plan I used to ensure the proper function of the RAM unit was that I loaded the number 1 into register 0 and then loaded register 0 into address 0 on the RAM. I then loaded address 0 into register 1. I continued this process increasing the value loaded into register 0 and the RAM address by 1 each time. I could then watch for proper function by watching that

register 1 counted up until the program ended. After I tested reading from register 0 and writing to register 1, I reversed the process starting again loading 1 into register 1, loading register 1 into RAM address 0, and reading into register 0. Then continued the incrementing process and watched register 0 count up. Doing this it appeared that my implementation of the RAM unit was working properly. However, upon looking into the RAM unit itself I saw that the values were incorrect. After examining the pins and wires connected to the tri-state buffer which controlled the input/output of the RAM I notice that my input wires were reversed sending the least significant bit to the most significant bit pin and vice versa. After rewiring the buffer I confirmed proper function by performing the same test and ensuring that not only did the registers count up, but that the proper values were being stored in the RAM itself.

Machine Code for Programs:

0001 0011 0010 0100 0110 0000 0010 0011 0011 0000 0010 0010 0001 1011 0011 0000 0010 0011 0001 0100 0011 0000 0001 1101 0011 0000 0100 0000 0011 0000 0010 0000 0001 1101 0011 0000 3+4 Addition Program Load 3 into register 0 Load 4 into register 1 ADD register 0 and register 1 Load 3 into register 1 Display number 3 Load 2 into Register 1 Load 11 into register 0 Display + Load 3 into Register 1 Load 4 into Register 0 Display 4 Load 13 into Register 0 Display = Move Accumulator to Register 0 Display 7 Load 0 into Register 1 Load 13 into Register 0 Display Carriage Return

3*3 Multiplication Program 0001 0011 Load 3 into Register 0 0010 0011 Load 3 into Register 1 0011 0000 Display 3 0010 0010 Load 2 into Register 1 0001 1010 Load 10 into Register 0 0011 0000 Display * 0001 0011 Load 3 into Register 0 0010 0011 Load 3 into Register 1 0011 0000 Display 3 0001 1101 Load 13 into Register 0 0011 0000 Display = 0001 0011 Load 3 into Register 0 0110 0000 Add Register 0 to Register 1 0100 0000 Load Accumulator to Register 0 0110 0000 Add register 0 to Register 1 0100 0000 Load Accumulator to Register 0 0011 0000 Display 9 0001 1101 Load 13 into Register 0 0010 0000 Load 0 into Register 1 0011 0000 Display Carriage Return

0001 0001 1010 0000 1101 0000 0001 0010 1010 0001 1101 0001 0001 0011 1010 0010 1101 0010 0001 0100 1010 0011 1101 0011

Ram Test Program 1 Load 1 into Register 0 Load Register 0 into RAM address 0 Load RAM address 0 into Register 1 Load 2 into Register 0 Load Register 0 into RAM address 1 Load RAM address 1 into Register 1 Load 3 into Register 0 Load Register 0 into RAM address 2 Load RAM address 2 into Register 1 Load 4 into Register 0 Load Register 0 into RAM address 3 Load RAM address 3 into Register 1

0010 0001 1011 0000 1100 0000 0010 0010 1011 0001 1100 0001 0010 0011 1011 0010 1100 0010 0010 0100 1011 0011 1100 0011

Ram Test Program 2 Load 1 into Register 1 Load Register 1 into RAM address 0 Load RAM address 0 into Register 0 Load 2 into Register 1 Load Register 1 into RAM address 1 Load RAM address 1 into Register 0 Load 3 into Register 1 Load Register 1 into RAM address 2 Load RAM address 2 into Register 0 Load 4 into Register 1 Load Register 1 into RAM address 3 Load RAM address 3 into Register 0

Questions:
1. What is the main difference between a Von Neumann based computer system and a Harvard based computer system? The main difference between Harvard and Von Neumann is that the Von Neumann Architecture holds both data and instructions in the memory sending both through the data bus. The Harvard architecture, on the other hand, has separate instruction and data memory, and separate buses for each. 2. List and describe the 3 parts of a Von Neumann based computer system. Memory This holds the data to be used by the CPU and the instructions which the CPU will follow. CPU This is the central processing unit which processes the instructions sent to it from the memory and I/O adapter, and modifies the data sent to it according to the instructions. I/O adapter This is used to interact with the outside world, it is capable of receiving data from external sources and either sending it to memory to be stored or to the CPU as an instruction or data to be modified. It also sends data to the user or other external sources.

3. What is a Program Counter (PC)? A program counter is a register which holds the address pointer to the current instruction. Once the instruction is sent to the CPU it is incremented to the next instruction to be processed. In the labs microprocessor it is a simple up-counter. 4. What are the 3 main categories of instructions listed in article #1? Describe each. What types of instructions does the BYUI processor have? Memory access Used to read and write data from memory. These include LOAD, used to load a register, and STORE used to store data to memory. Calculation Use registers or other operands to perform calculations such as ADD, SUB, AND, OR, etc. These are done completely in the ALU and do not access memory. Branch These instructions alter the flow of a program based on the results of a comparison. These work similar to If, Then statements. The BYUI processor only has Memory access and Calculation instructions since it only performs loads, stores, and calculations. 5. What does the acronym CISC stand for? What does it mean? CISC stands for Complex Instruction Set Computer, which means that there is not a limited instructions size. This allows for more complex and varied instructions since the instruction codes are not limited to a single word size. These complex instructions allow for shorter programs since there is fewer redundancy in the code, however the complexity does increase the execution time for instructions. 6. What does the acronym RISC stand for? What does it mean? RISC stands for Reduced Instruction Set Computer, which means that instruction size is limited to 1 word. This results in fewer instructions in the instruction set. Because of this programs tend to be larger as complex processes take more instructions. However, because of the standardized instruction size execution time per instruction is set at 1 clock cycle.

7. The Intel Core Processor Family has 3 versions (Core i3, Core i5, and Core i7). Briefly describe the main difference between these 3 processors. One difference is that the Core i3 is a dual core chip while the i5 and i7 are quad-cores. The i5 and i7 also have a Turbo Boost feature which focuses unused processing when one or more cores is not being used. Another large difference between the three cores is the cache size which is memory located directly on the processor. The i3 has a 3Mb cache, i5 has 6Mb and the i7 has 8Mb, although these differences seem slight, they make a large difference in the processing power of each. 8. From a computer performance standpoint, what does the acronym MIPs sand for? What does it mean? MIPs stands for millions of instructions per second. This is a general unit of measurement used to compare the performance of a processor. Generally, the more instructions a processor can perform in a second the faster it will run programs given to it. 9. From a computer performance standpoint, what does the acronym FLOPs stand for? What does it mean? FLOPs stands for floating point operations per second. This is another general measure of performance, since floating point operations are more complex and require more processing power to perform calculations with. Generally used in scientific processing, this measurement is most relevant to the comparing the processing power of super computers. 10. How many general purpose registers does the MSP430 have? The MSP430 has 12 general purpose registers R4 R15.

Conclusion:
The purpose of this lab was to reacquaint the student with the BYUI processor created in the ECEN 160 class, which it was able to accomplish. Through this lab I have become reacquainted with the functions of this processor and its instruction set. Although it was difficult at first to figure out how to then use that knowledge to implement a 1k RAM unit, after

some trial and error I was eventually able to create a working memory unit for this processor. The biggest problem I found was rerouting several of the instruction PROM pins into a second PROM which would allow for more functionality. Another problem I had was finding out how to ensure that the read and write commands were not overlapping in the RAM causing unwanted data to be written. This access problem was solved with a simple NOR gate which prevented the RAM from being accessed when it was not needed. Finally, as discussed before, I had the mix-up of reversing the input pins on the tri-state buffer going into the RAM. However, after sorting out these small issues I ended up with a working microprocessor capable of performing all its original operations, plus the added functionality of having a memory unit.