April 1997

NDS351AN N-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description
These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMCIA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package.

Features
1.2A, 30 V. RDS(ON) = 0.25 @ VGS = 4.5 V RDS(ON) = 0.16 @ VGS = 10 V. Industry standard outline SOT-23 surface mount package using proprietary SuperSOTTM-3 design for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. Compact industry standard SOT-23 surface mount

_________________________________________________________________________________

Absolute Maximum Ratings

Symbol VDSS VGSS ID PD TJ,TSTG Parameter Drain-Source Voltage

T A = 25C unless otherwise noted

NDS351AN 30 20
(Note 1a)

Units V V A

Gate-Source Voltage - Continuous Maximum Drain Current - Continuous - Pulsed Maximum Power Dissipation
(Note 1a) (Note 1b)

1.2 10 0.5 0.46 -55 to 150

Operating and Storage Temperature Range

THERMAL CHARACTERISTICS RJA RJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case
(Note 1a) (Note 1)

250 75

C/W C/W

1997 Fairchild Semiconductor Corporation

NDS351AN Rev. C

Electrical Characteristics (TA = 25C unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS IGSSF IGSSR VGS(th) RDS(ON) Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 A VDS = 24 V, VGS = 0 V TJ =125C Gate - Body Leakage, Forward Gate - Body Leakage, Reverse VGS = 20 VDS = 0 V VGS = -20 V, VDS = 0 V VDS = VGS, ID = 250 A TJ =125C Static Drain-Source On-Resistance VGS = 4.5 V, ID = 1.2 A TJ =125C VGS = 10 V, ID = 1.4 A ID(ON) gFS Ciss Coss Crss td(on) tr td(off) tf Qg Q gs Q gd On-State Drain Current Forward Transconductance VGS = 4.5 V, VDS = 5 V VDS = 5 V, ID= 1.2 A, VDS = 10 V, VGS = 0 V, f = 1.0 MHz 3.5 1.8 0.8 0.5 1.7 1.3 0.19 0.28 0.125 30 1 10 100 -100 V A A nA nA

ON CHARACTERISTICS (Note 2) Gate Threshold Voltage 2 1.5 0.25 0.37 0.16 A S V

DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance

(Note 2)

125 100 90

pF pF pF

SWITCHING CHARACTERISTICS Turn - On Delay Time Turn - On Rise Time Turn - Off Delay Time Turn - Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge

VDD = 10 V, ID = 1 A, VGS = 10 V, RGEN = 50

6 15 14 18

15 30 30 40 2.7

ns ns ns ns nC nC nC

VDS = 10 V, ID = 1.2 A, VGS = 4.5 V

1.9 0.5 0.9

NDS351AN Rev. C

Electrical Characteristics (TA = 25C unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS ISM VSD
Notes: 1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of guaranteed by design while RCA is determined by the user's board design. the drain pins. RJC is

Maximum Continuous Drain-Source Diode Forward Current Maximum Pulsed Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.2 A (Note 2) 0.8

0.42 5 1.2

A A V

P D (t ) =

R JA(t )

T J TA

TJ

TA

R JC+RCA(t )

= I 2 (t ) RDS(ON ) D

TJ

Typical RJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper. b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper.

1a

1b

Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.

NDS351AN Rev. C

Typical Electrical Characteristics

5 1.8

V GS =10V
I D , DRAIN-SOURCE CURRENT (A)
4

6.0

R DS(on ) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE

5.0 4.5 4.0

1.6 1.4 1.2 1 0.8 0.6 0.4

VGS = 3.5V

3.5
2

4.0 4.5 5.0 6.0 7.0 10

3.0
1

0 0 V
DS

, DRAIN-SOURCE VOLTAGE (V)

2 I D , DRAIN CURRENT (A)

Figure 1. On-Region Characteristics.

Figure 2. On-Resistance Variation with Drain Current and Gate Voltage.

1.8

1.8 DRAIN-SOURCE ON-RESISTANCE I D = 1.2A 1.6 1.4 1.2 1 0.8 0.6 0.4

DRAIN-SOURCE ON-RESISTANCE

1.6

VGS = 4.5 V

R DS(ON), NORMALIZED

V GS = 4.5V

TJ = 125C

1.4

RDS(on) , NORMALIZED

1.2

25C -55C

0.8

0.6 -50

-25

0 25 50 75 100 T , JUNCTION TEMPERATURE (C) J

125

150

2 I D, DRAIN CURRENT (A)

Figure 3. On-Resistance Variation with Temperature.

Figure 4. On-Resistance Variation with Drain Current and Temperature.

V DS = 5.0V
4

25C

Vth , NORMALIZED GATE-SOURCE THRESHOLD VOLTAGE

T = -55C J

1.2 1.1 1 0.9 0.8 0.7 0.6 -50

I D , DRAIN CURRENT (A)

125C
3

V DS= V GS I D = 250A

0 0.5

1.5 V
GS

2.5

3.5

4.5

-25

, GATE TO SOURCE VOLTAGE (V)

0 25 50 75 100 TJ , JUNCTION TEMPERATURE (C)

125

150

Figure 5. Transfer Characteristics.

Figure 6. Gate Threshold Variation with Temperature.

NDS351AN Rev. C

Typical Electrical Characteristics (continued)

1.12

DRAIN-SOURCE BREAKDOWN VOLTAGE

I , REVERSE DRAIN CURRENT (A)

I D = 250A
1.08

V GS = 0V
1

BV DSS , NORMALIZED

TJ = 125C
0.1

25C -55C

1.04

0.01

0.96

0.001

0.92 -50

-25

0 T
J

25

50

75

100

125

150

0.0001 0 0.2 0.4 0.6 0.8 1 V SD , BODY DIODE FORWARD VOLTAGE (V) 1.2

, JUNCTION TEMPERATURE (C)

Figure 7. Breakdown Voltage Variation with Temperature.

Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature.

400 , GATE-SOURCE VOLTAGE (V) 300 CAPACITANCE (pF)

10

I D = 1.2A
8

VDS = 5V

10V 15V

200 150

C iss
100 80

C oss f = 1 MHz V GS = 0V C rss

50 0.1

V 0.2 V 0.5
DS

GS

10

20

30

, DRAIN TO SOURCE VOLTAGE (V)

2 Q g , GATE CHARGE (nC)

Figure 9. Capacitance Characteristics.

Figure 10. Gate Charge Characteristics.

VDD
t d(on)

t on

t off tr
90%

t d(off)
90%

tf

V IN
D

RL V OUT
VOUT
10%

VGS

R GEN

10%
INVERTED

DUT 90% S

V IN
10%

50%

50%

PULSE WIDTH

Figure 11. Switching Test Circuit.

Figure 12. Switching Waveforms.

NDS351AN Rev. C

Typical Electrical Characteristics (continued)

, TRANSCONDUCTANCE (SIEMENS) 5 20

VDS = 5.0V
I D , DRAIN CURRENT (A) 4

10

1m s
N) S(O RD IT LIM

T J = -55C 25C

5 3 1 0.3 0.1 0.03 0.01 0.1

10m 100 1s ms

125C

V GS = 4.5V SINGLE PULSE R JA =See Note1b T = 25C A

0.2 0.5 V
DS

10s DC

FS

2 3 I , DRAIN CURRENT (A)

D

10

20 30

50

, DRAI N-SOURCE VOLTAGE (V)

Figure 13. Transconductance Variation with Drain Current and Temperature.

Figure 14. Maximum Safe Operating Area.

STEADY-STATE POWER DISSIPATION (W)

1
I , STEADY-STATE DRAIN CURRENT (A)

1.6

0.8

1.4

0.6
1b

1a

1.2

1a

0.4

1b

4.5"x5" FR-4 Board TA = 2 5 C Still Air VG S = 4 . 5 V

o

0.2

4.5"x5" FR-4 Board TA = 25 oC Still Air

0.8 0 0.1 0.2 0.3 2oz COPPER MOUNTING PAD AREA (in 2 ) 0.4

0.1 0.2 0.3 2oz COPPER MOUNTING PAD AREA (in 2 )

0.4

Figue 15. SuperSOTTM _ 3 Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area.

Figure 16. Maximum Steady-State Drain Current versus Copper Mounting Pad Area.

1
r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE

0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.0001

D = 0.5 0.2 0.1 0.05 0.02 0.01 Single Pulse

R JA (t) = r(t) * R JA R JA = See Note 1b

P(pk)

t1

t2

TJ - TA = P * R JA (t) Duty Cycle, D = t1 /t2

0.001

0.01

0.1 t 1 , TIME (sec)

10

100

300

Figure 17. Transient Thermal Response Curve.

Note : Characterization performed using the conditions described in note 1b. Transient thermal response will change depending on the circuit board design.

NDS351AN Rev. C