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VLSI Design Concepts
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Advanced Technology Center Chung-Wei Ku
Content
Introduction s Static CMOS logic s Important components s Modern VLSI design methodology s DSP system design
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Advanced Technology Center
Chung-Wei Ku
References
N. Weste and K. Eshraghian, Principle of CMOS VLSI Design: A System Perspective, Addison-Wesley Published, 1993. s Kai Hwang, Computer Arithmetic: Principles, Architecture, and Design, 1989.
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Introduction
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Very Large Scale Integration (VLSI)

Integrated Circuit (IC) with large density
millions of gate counts for modern VLSI technology
Large system can be integrated into small silicon area

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Complementary Metal-Oxide-Silicon (CMOS) process

low cost, low power, stable.
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Physical Structure
field-oxide p-well n-substrate
thin-oxide
p-well n-substrate
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Physical Structure
poly-oxide
p-well n-substrate
p+
p+
p-well n-substrate
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Physical Structure
p+ p+ n+ n+
p-well n-substrate
p+
p+
n+
n+
p-well n-substrate
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Physical Structure
p+
p+
n+
n+
p-well n-substrate
VLSI design is a 3-D structure s Mask amount is critical to cost s Design rules for specific process
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Scaling Effects
W/ L/ tox/ polysilicon gate
n+ or p+
p- or n- substrate
n+ or p+
Xj/
Na(d)
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Scaling Effects
Parameter Length: L Width: W Gate oxide thickness: tox Junction depth: Xj Substrate doping: Na Supply voltage: Vdd Electric field across gate oxide: d Parasitic capacitance: WL/tox Gate delay: VC/I DC power dissipation: Ps Dynamic power dissipation: Pd Power-delay product Gate area Power density (VI/A) Current density (I/A) Transconductance: gm Scaling 1/ 1/ 1/ 1/ 1/ 1 1/ 1/ 1/ 1/ 2 1/ 2 1/ 3 1/ 2 1 1
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MOS Behavior
a b c PMOS a b c 1 0 1 0 0 1 1 1 z 0 1 z b c NMOS a b c 1 0 z 0 0 z 1 1 1 0 1 0 a
Threshold voltage (Vt): ~0.7 Volt

CMOS Logic
Vdd A X X A B Vdd A B
B (AB)
(A+B) B
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Boolean Logic Arithmetic

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F=AD+AB+BCD
F=(A+D)(A+B)(B+C+D)
F B A D
A D
A C B D B
D
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Important Components
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Adder
carry-propagate; carry-save; carry-select
Multiplier
Booths multiplier
Shift register s Memory s Logic (MUX, DEMUX, logic gates,...)

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Adder Design
A B A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C SUM Carry 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 1
Carry
Full Adder SUM
FA: the smallest building block
SUM=ABC+ABC+ABC+ABC Carry=AB+AC+BC
Carry Propagate Adder

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Cascaded with several FAs (4 bits).

A4 B4 A3 B3 A2 B2 A1 B1
Cout
Full Adder SUM4
Full Adder SUM3
Full Adder SUM2
Full Adder SUM1
Cin
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Parallel Multiplier
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Direct implementation (4 bits)

X3 Y0 Y1 Y2 Y3 P7
X3Y3 X3Y2 X2Y3 X3Y1 X2Y2 X1Y3 X3Y0 X2Y1 X1Y2 X0Y3
X2
X2Y0 X1Y1 X0Y2
X1
X1Y0 X0Y1
X0
X0Y0
P6
P5
P4
P3
P2
P1
P0
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Finite State Machine

AND s OR
General solution:
input Programmable Logic Array z registers X0 X1 X2
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output
Hierarchy of Design Levels

System level s Behavioral level s Register transfer logic (RTL) level s Gate level s Circuit (or Switch) level s Physical level
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Behavior Level Modeling

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Behavior level
describe the behavior of the module
Example: Adder (algorithm based)

module adder(A,B,C); A input[7:0] A,B; output[7:0] C; C ADDER initial B C=A+B; end endmodule No Timing and Structural Issues
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RTL Level Modeling

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RTL level
describe the logic between registers, including the clock timing information
Example: FIR filter (architecture based)
x[n] a1 y[n]
a2
a3
a4 0
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Gate Level Modeling

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Gate level
describe the structure of the whole architecture in terms of logical gates
Example: 2-to-1 multiplexer (gate-count, speed)

a sel output b
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Circuit Level Modeling

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Circuit level:
describe the electronic behavior of all the components, such as capacitance, resistance, conductance, MOS, etc.
Example: Inverter (driving, power)

Vdd
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Layout Level Modeling

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Layout level:
describe the circuit geometric polygon directly. Layout can be used for mask generation directly.
Example: Inverter (DRC, process parameters)

Vdd In Out
Vss
Full-Custom Design Flow

Step 1: system architecture s Step 2: RTL design and simulation s Step 3: building block
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circuit level design and simulation layout simulation

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Step 4: integrate building blocks

integrate (place and route) and simulate DRC and ERC for fabrication
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Cell-based Design Flow

Gate-level cell-library is built by fab vendors. s Step 1: system architecture s Step 2: RTL design and simulation s Step 3: Silicon compiler (with cell library)
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use tools to convert RTL code to gate-level code

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Step 4: Layout tools

use tools to do place and route DRC and ERC for fabrication
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Top-Down Design Flow

System-on-a-chip: because of fast progress submicron technology, it is possible to put a system into a single chip. s Top-down design flow becomes more and more important because more efforts must be paid for system level design (e.g. algorithm and architecture) s EDA tools become more and more mature.
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Top-Down Design Flow

algorithm: C, verilog, SPW building blocks behavior: HDL code System Simulation SPW, C compiler, COSSAP verilog or VHDL simulator
SPW
Behavior Simulation
cell library
architecture: HDL code
VA, Behavior Compiler

RTL-level Simulation verilog or VHDL simulator
Design Compiler
gate-level: HDL code Gate-level Simulation verilog or VHDL and Altera simulator simulator
OPUS, Altera
physical: Layout or FPGA Physical Simulation Cadence, Avant!, Altera....
product
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Analog VLSI Design

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Full-custom design:
Most efforts are put on circuit level design Iterative circuit - layout design flow size matching, impedance matching, noise are issues
Parameter-based design
some standard components are built-in A-verilog are under development EDA tools are still in primary stage
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DSP System Design

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Specifications:
frequency domain time domain
y[n]=a1x[n]+ a2x[n-1] + a3x[n-2]
signal flow graph

x[n] a1 y[n]
a2
a3 0
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DSP System View

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Control unit can be implemented by FSM

Memory Control Unit Data-path
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Building Blocks for DSP

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Memory
RAM, ROM, Buffers, registers, Shift registers
Control
FSM, counters, etc.
Arithmetic unit
Bit-sliced datapath (adder, multiplier, ALU, etc.) Bit-serial datapath
Interconnect
Switches, arbiters, bus, ....
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High Performance Datapath

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About 95% of data stream operations can be covered by the following hardware
Registers Adders Multipliers Comparators Logic operations Multiplexers Buffers
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High Performance Datapath

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Approaches:
Use the fastest logic (carry ripple v.s. lookahead)
Computation graph transformation

Pipelining, unrolling, redundant representation, tree-structure computation, change number system.
Balance resource
Time-share, routing strategy
Automatic synthesis
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Pipelining
clock data s logic logic logic
Does not work for recursive algorithm

IIR, adaptive computation
Registers can be extensive s Registers load clock distribution

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clock skew problems

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Asynchronous approach
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Re-Timing Technique
x[n] a1 y[n] x[n] a1 y[n]
a2
a3
a4 0
a2
a3
a4 0
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Multiplication
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Canonical Signal Digit (CSD) {-1,0,1}

0.1111111 = 20 - 2-7 = 1.0000001
X >>7
Booth algorithm:
1 0 0 1 1 1 0 1 (0) 0 1
1 0
1 0
0 1
1 0 1 0 0 1 0 1
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Other Functions
Division and square-root: iterative operation s Log, sin, cos: table look-up
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interpolation can be used to reduce table size Taylor series expansion: numerical problems
Cordic rotation s Comparators s Shifters

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DSP System Design Flow

tools or C language VHDL verilog silicon compiler system
C language compiler
Application Specific Embedded software Signal Processing (ASSP) for p, CPU, or DSP : ASIC or FPGA
System-on-a-chip
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Virtual component (or intellectual property)

Advanced RISC machine (ARM)
VLSI design extended from cell-based to macroblock-based design s System level knowledge and integration s Verification and testing RAM p s Internal v.s external I/O DSP ASSP s Process compatibility
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VLSI Design Concepts

\S}m Zv<? LUR`^

Advanced Technology Center

Advanced Technology Center

Very Large Scale Integration (VLSI)

Large system can be integrated into small silicon area

Complementary Metal-Oxide-Silicon (CMOS) process

Advanced Technology Center

Advanced Technology Center

Advanced Technology Center

Advanced Technology Center

Advanced Technology Center

Advanced Technology Center

Threshold voltage (Vt): ~0.7 Volt

Advanced Technology Center

Boolean Logic Arithmetic

Advanced Technology Center

Shift register s Memory s Logic (MUX, DEMUX, logic gates,...)

Full Adder SUM

FA: the smallest building block

Carry Propagate Adder

Cascaded with several FAs (4 bits).

Full Adder SUM4

Full Adder SUM3

Full Adder SUM2

Full Adder SUM1

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Direct implementation (4 bits)

Advanced Technology Center

Finite State Machine

Advanced Technology Center

Hierarchy of Design Levels

Advanced Technology Center

Behavior Level Modeling

Example: Adder (algorithm based)

Advanced Technology Center

RTL Level Modeling

Example: FIR filter (architecture based)

Gate Level Modeling

Example: 2-to-1 multiplexer (gate-count, speed)

Advanced Technology Center

Circuit Level Modeling

Example: Inverter (driving, power)

Advanced Technology Center

Layout Level Modeling

Example: Inverter (DRC, process parameters)

Full-Custom Design Flow

circuit level design and simulation layout simulation

Step 4: integrate building blocks

Advanced Technology Center

Cell-based Design Flow

use tools to convert RTL code to gate-level code

Step 4: Layout tools

Advanced Technology Center

Top-Down Design Flow

Top-Down Design Flow

VA, Behavior Compiler

Advanced Technology Center

Analog VLSI Design

Advanced Technology Center

DSP System Design

y[n]=a1x[n]+ a2x[n-1] + a3x[n-2]