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ABES Institute of Technology (ECS-301 DIGITAL LOGIC DESIGN) 2ND YEAR (11CS & 11IT) MODEL TEST PAPER #1
Time: 3.00 hrs. Max. Marks: 100

Note: The question paper contains three Sections. All Sections are compulsory. PART A (2 10= 20) Attempt all questions. Answers are expected to be in 50-75 words. All questions are of same marks. 1. Minimize F = M(1,4,5,6,11,12,13,14) using a K Map and realize using NOR gates. 2. A seven bit hamming code is received as 1111101. Check if it is correct. If not, find the correct code and the data encoded if even parity is used. 3. Show the diagram of Master-Slave JK flip flop. 4. Differentiate between tatic-0, Static-1 and dynamic hazards. 5. Describe twisted ring counter in brief. 6. With the help of block diagrams show difference between Moore and Mealey circuits. 7. Design a full adder using a ROM. 8. Write the excitation table of SR, JK T and D flipflops. 9. Implement the expressions F(A,B,C) = m(1,3,6,7) G(A,B,C) = m(0,3,4,5) using a 3:8 decoder. 10. Describe priority encoder in brief. PART B (6 5 = 30) Attempt ALL questions . All questions are of equal marks. Answer should be in 100 to 200 words. 11. Using four input multiplexers implement the following a. F(A,B,C,) = m(0,2,3,5,7) control variables A and B b. F(A,B,C,) = m(1,3,4,6,7) control variables B and C 12. Design a 8x8 RAM using 4x4 RAMs. Use block diagrams. 13. Design a 3 bit asynchronous counter using ASM blocks. 14. Design a sequence detector for the sequence 101101 using JK Flip flops. 15. Design a 2 bit BCD adder with the help of 4-bit binary adders. 16. Implement a 5x32 decoder using 3x8 and 2x4 decoders. PART C (5 10= 50) Attempt all the five questions. All questions are of equal marks. Answer should be in 300 to 500 words.

17. Draw the state diagram and ASM chart for the synchronous circuit having the following description. The circuit has a control input C and outputs a,b and c. If C=1 every positive edge of the clock the output changes in the sequence 000, 001, 011, 101, 111, 010, 100, 110, 000 If C=0 the circuit holds the present state. OR Design a combinational circuit using a ROM that accepts a 3 bit number and generates an output binary number equal to the square of the input number. 18. Draw and explain the block diagram of asynchronous circuit. Also write down the steps for analysis of asynchronous circuits. OR Minimize the following Boolean function using Tabular method F(A,B,C,D) = m(0,2,4,10,15,19,23,29,31) and implement it using NOR gates. 19. What are shift registers. What are the various types of registers. Design a 4-bit ripple counter . OR Explain the static RAM and dynamic RAM.describe the PLA and its application in detail. 20. Draw an ASM chart for a MOD 6 counter with a reset input and design the counter with T flip flops. OR Draw the logic diagram of the POS expression Y = (X1 + X2)(X2 + X3). Show that there is a static 0 hazard when X1 and X3 are equal to 0 and X2 goes from 0 to 1. Find a way to remove the hazard. 21. Draw a PLA circuit to implement the functions a. F1 = AB + AC + ABC b. F2 = (AB + AC + BC) OR A sequential circuit has four flip flops A, B, C and D and an output X. it is described by following state equations A(t+1) = (CD + CD)X + (CD + CD)X B(t+1) = A C(t+1) = B D(t+1) = C (i) Obtain the sequence of states when x = 1 starting from ABCD = 0001 (ii) Obtain the sequence of states when x = 0 starting from ABCD = 0000