Rochester Institute of Technology Department of Computer Engineering EECC630/730 VLSI Design Dr. Ken Hsu (kwheec@rit.

edu) Project A Ripple Carry 16 or 32 Bit Mirrored Adders A High Speed 16 or 32 Bit Carry-Select Domino Logic Adders The project duration is from October 11, 2006 to November 1, 2006. The project Demo must be done on November8, 2006. The project report is due on Final Exam date. Please fill out the attached Demo Form before the project demo. Please follow the Project Report Specification carefully. You will have 4 weeks to do the important project. One week for the top level assembly with I/O pads, and final project report writing. The project is to be designed, simulated, and physically laid out with TSMC 0.35 m 4T 2P Nwell CMOS technology. The verification is accomplished by DRC and LVS. You have 5 weeks to complete the project. You and your partner need to communicate frequently to work together. Do you know your partners phone number and email address ? In digital signal processing VLSI chip design, the most important building block is the adders and multipliers. In order to obtain real time digital signal processing, VLSI designers search for high speed adder, and high speed multiplier. Furthermore pipelined multipliers will output a valid product at each clock cycle after a certain amount of latency time. You are encouraged to find a recently developed algorithm to design the high speed adder. Find as many as papers as possible that show novel architectures for high speed CMOS dynamic adders with low power consumption. Part I Mirrored 16-bit or 32-bit Adder (Static CMOS Logic) Design one bit full adder, then cascade the full adder together to make 16 or 32 bit adder, area must be small. Determine the time delay for the one bit full adder. Measure rsie time, fall time, propagation delay high to low, and low to high. Make a table for the timing parameters for Sum and Carry. Create symbol for one bit adder, then cascade the one bit full adder to form a 16 or 32 bit transistor level schematics. Do a simulation for timing parameters. Determine the throughput frequency for the 16 or 32 adder by calculation. Draw a stick diagram for the mirrored adder and do the physical layout for one bit full adder, then cascade them to form 16 or 32 bit adder. Do a careful floor plan.

Do DRC and LVS for each cell you design. Part II 16 Bit or 32 Bit High Speed Carry Select Domino Logic Adders You must fine tune the sizing of each transistor for the proper output voltage and minimum gate propagation delay of clock to output. Measure tclock-to-output-HL and tclock-to-outputLH and then use both parameters to determine the maximum operating frequencies. After the successful simulation with desirable speed, then do the physical layout of basic Domino logic cells. Think of top level floor plan before you start the layout. It is desirable to have the final layout fit into a square area. Keep all simulation waveforms and measurement of propagation delays in the print forms. These are partial documentation of your final project report. Each designer is responsible for design, simulation, layout, and verification of the physical layout with the source schematics. Define the basic standard cells and complete the simulation and layout. Do DRC and LVS to verify the design correctness of the layout and the CMOS circuit design. Measure the propagation delay from clock to output from high to low and the delay from low to high. Follow the best high speed algorithm you can find to complete your task. Measure tpHL, clock to sum and tpLH, clock to sum and add two delay times. The reciprocal of the total delay is the operating frequency of your adder core. You will simulate all basic cells with ACCUSIM II. Measure tpHL, clock to Q and tpLH, clock to Q and add two delay times. Part II Chip Assembly: Placement of Multiplier Core and BIST Core Merge the layout of the ADDER cells, add VDD, GND, CLOCK and other input and output signals to the whole layout. For the 16 or 32 bit design. Fit the total physical design into the 112 I/O pads. Use metal layers 2, 3, or 4 for the clean global power bus for VDD and GND. Connect VDD and GND from each cell to the global VDD and GND. Make sure that good connection scheme is used to guarantee good power distribution. The IO pads must be properly connected to VDD or GND for enabling or disabling of the pads. Clock distribution must be designed for overall layout. Estimate the total current each bus will carry. A width of 1 m of metal 1 or metal 2 can carry 1 ma D.C. IO PAD Instructions Directory for the IOPAD /class/eecc630/adk/ic/40pinIOpads

(1) For input IO PAD: DataIn to your input signals, e.g. x0, x1, x2, x3, y0, y1, y2, y3, c1a, c1b, c2a, c2b, mode, clk, etc) EN must be connected to ground (GND). (2) For output IO PAD: DataOut to your output signals, e.g. p0, p1, p2, p3, p4, p5, p6, p7, comparator output, etc) EN must be connected to VDD (3) For unused IO PAD: EN must be connected to VDD DataOut must be connected to GD so that the IO PAD is grounded, and will not generate noise. Part III Project Report Complete documentation of your project is required. The report should include a cover page to indicate the title of the project, class, instructor, your name and the date the project is completed. The complete search path to your project design is required. A table of contents must be included with page number for each section. In the introduction section, explain the algorithm of your adder. Show your design methodology. Explain the advantage of your design. Summary and Conclusion Include the size of your layout, number of transistors for each cell and the final total design, and the operating speed of your design. Tabulate the area, speed, and power dissipations. Suggest future research tasks. Attach all pertinent printouts of simulation waveforms, and a list of testing results. And anything that is related to your chip design -LVS. Reference List the articles that you have found for your project in the following format: Name(s) of author(s), title of articles (in italic), Magazines name or conference, location and date. Final Color Plot

Print the final top assembly in a large color plot. Each student can take one plot with you. Additional plots will cost you a nominal fee (this is the department policy). Write up the report neatly. You are encouraged to submit your report to the Mentor Graphics IC design contest or IEEE Conference.

VLSI Project Extra Credits (Up to 10 points) (1) Design and physical layout of Clock Buffer (10 Pts.) Calculate the total load for the clock, then determine number of stages and scaling factor for the buffer chain for minimal buffer delay.

Project Report Specifications Please use a three-ring binder for your report. Include a large plot for your top physical layer in the inside pocket of your binder (fold it to fit 8 x 10 size).
1. Cover Page (center each line on this page) New16 Bit High Speed Domino Adder with BIST or New 32 Bit High Speed Domino Adder with BIST Team Members names side by side and indicate the course number, either EECC 630 or EECC 730. The undergraduate students will receive bonus points for the implementation 32 bit adder, which is required of graduate students. Show the email Address under each name.

Indicate who performs what: the ADDER Core, extra credit for clock buffer.
Indicate clearly if there is extra credit work included in the project on the cover page. Show the complete directory path for the top level layout Course Number EECC 630 or EECC 730 Instructor: Dr. Ken Hsu Lab Assistant: 2. Table of Contents Show Section and Page Number 3. First Section Indicate the objective of the project, design algorithms; Indicate the full path name of your top level layout (to be sent to plotter) 4. Design Methodology Use CMOS N-Well technology with feature size of 0.35 m 4T 2P. Show the design flow from concept to physical layout to verification with BIST to guarantee that the design is functionally correct.

5. ADDER CORE Simulation of each building block and its documentation

Include the printout of waveforms, and the transistor level source schematics.

6. Include the physical layout of each building block with the dimensions in x vs. y in
Lambdas().

8. Include problems encountered in design and simulations or in layout, and the solutions
found.

9. Include in a binder of all your printed documentation, and one large plot of the final top
physical layout (folded into the 8 by 11 paper size). Show the instructors name, the course number and title, and team members. Give the full directory path name on the cover page of your report. Each will take one plot home with you. It is very useful to show the top level plot to your next industry recruiters. On the plot, insert your names. You also show the instructors name, the TAs name, the course number, and the date of completion. [NOTE: Before you send your layout for plot, you run a plotter script, then the characters are visible.]

10. Summary and Conclusion, Suggestions for higher speed and novel circuit with
reference article. Indicate total number of N and P transistors, the size (dimension from the lower left hand corner to the upper right hand corner.

EECC 630/730 VLSI Design Dr. Ken Hsu Instructions for Plotting the Physical Layout Make sure LVS is done successfully. 1. Click on File Printer Select printer: HAMM ROLL 36 (for three feet wide paper). There are other sizes of paper. 2. Build select Display Color, then OK. 3. Layout options No header, select Legend, select Ruler. Select OK. 4. Close this window, open up Shell Konsole 5. At the prompt, type fix_plotter_text.sh 6. close the shell window. Now the plotter start downloading your physical layout data and ready to plot.

EECC 630/730 VLSI Design Dr. Ken Hsu 11/8/2006 Project Demonstration Project Directory: ___________________________________________ Team Members: Name: ___________________, ___________________ Email Address: _____________________ __________________ Project Credits: ______________________________________________ Extra Credits Clock Buffer: _________________(10 pts.)