PM50CLB060
FLAT-BASE TYPE INSULATED PACKAGE
PM50CLB060
FEATURE
a) Adopting new 5th generation IGBT (CSTBT) chip, which performance is improved by 1m fine rule process. For example, typical Vce(sat)=1.5V @Tj=125C b) I adopt the over-temperature conservation by Tj detection of CSTBT chip, and error output is possible from all each conservation upper and lower arm of IPM. c) New small package Reduce the package size by 32%, thickness by 22% from S-DASH series. 3 50A, 600V Current-sense IGBT type inverter Monolithic gate drive & protection logic Detection, protection & status indication circuits for, shortcircuit, over-temperature & under-voltage (P-Fo available from upper arm devices) Acoustic noise-less 3.7kW class inverter application UL Recognized Yellow Card No.E80276(N) File No.E80271
APPLICATION General purpose inverter, servo drives and other motor controls
PACKAGE OUTLINES
120 7 19.75 3.25 16 3-2 106 0.25 66.5
Dimensions in mm
4 4
25.75
35
55
13
19
4 4
25
4 4
4 4
4 4
42 .
2-2.5
1.5
1
N P
9.5
23 98.25
23
Terminal code 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. VUPC UFO UP VUP1 VVPC VFO VP VVP1 VWPC WFO 11. 12. 13. 14. 15. 16. 17. 18. 19. WP VWP1 VNC VN1 NC UN VN WN Fo
19-s0.5
11.5 27.5
9.5
May 2005
PM50CLB060
FLAT-BASE TYPE INSULATED PACKAGE
NC Fo
1.5k
VNC WN
VN1
VN
UN
VP VVPC
VVP1 VFO
UP VUPC
VUP1 UFO
1.5k
1.5k
1.5k
Gnd In
Fo Vcc
Gnd In
Fo Vcc
Gnd In
Fo Vcc
Gnd In
Fo Vcc
Gnd In
Fo Vcc
Gnd In
Fo Vcc
Gnd
Si Out
OT
Gnd
Si Out
OT
Gnd
Si Out
OT
Gnd
Si Out
OT
Gnd
Si Out
OT
Gnd
Si Out
OT
NC
(Note-1)
CONTROL PART
Symbol VD VCIN VFO IFO Parameter Supply Voltage Input Voltage Fault Output Supply Voltage Fault Output Current Condition Applied between : VUP1-VUPC VVP1-VVPC, VWP1-VWPC, VN1-VNC Applied between : UP-VUPC, VP-VVPC WP-VWPC, UN VN WN-VNC Applied between : UFO-VUPC, VFO-VVPC, WFO-VWPC FO-VNC Sink current at UFO, VFO, WFO, FO terminals Ratings 20 20 20 20 Unit V V V mA
May 2005
PM50CLB060
FLAT-BASE TYPE INSULATED PACKAGE
TOTAL SYSTEM
Parameter Supply Voltage Protected by VCC(PROT) SC VCC(surge) Supply Voltage (Surge) Storage Temperature Tstg Isolation Voltage Viso Symbol Condition VD = 13.5 ~ 16.5V, Inverter Part, Tj = +125C Start Applied between : P-N, Surge value 60Hz, Sinusoidal, Charged part to Base, AC 1 min. Ratings 400 500 40 ~ +125 2500 Unit V V C Vrms
THERMAL RESISTANCES
Symbol Rth(j-c)Q Rth(j-c)F Rth(c-f) Parameter Junction to case Thermal Resistances Contact Thermal Resistance Condition Inverter IGBT (per 1 element) Inverter FWDi (per 1 element) Case to fin, (per 1 module) Thermal grease applied (Note-1) (Note-1) (Note-1) Min. Limits Typ. Max. 0.95* 1.61* 0.038 Unit
C/W
* If you use this value, Rth(f-a) should be measured just under the chips. (Note-1) Tc (under the chip) measurement point is below. arm axis X Y UP IGBT FWDi 29.0 29.5 7.3 1.6 VP IGBT FWDi 64.6 65.1 7.3 2.1 WP IGBT FWDi 85.9 86.4 7.3 2.1 UN IGBT FWDi 38.1 37.6 5.3 4.6 VN IGBT FWDi 54.8 55.3 5.3 4.6 (unit : mm) WN IGBT FWDi 76.1 75.6 5.3 4.6
Bottom view
Switching Time
mA
May 2005
PM50CLB060
FLAT-BASE TYPE INSULATED PACKAGE
CONTROL PART
Symbol ID Vth(ON) Vth(OFF) SC toff(SC) OT OTr UV UVr IFO(H) IFO(L) tFO Parameter Circuit Current Input ON Threshold Voltage Input OFF Threshold Voltage Short Circuit Trip Level Short Circuit Current Delay Time Over Temperature Protection Supply Circuit Under-Voltage Protection Fault Output Current Minimum Fault Output Pulse Width VD = 15V, VCIN = 15V Condition VN1-VNC V*P1-V*PC Min. 1.2 1.7 100 135 11.5 1.0 Limits Typ. 15 5 1.5 2.0 0.2 145 125 12.0 12.5 10 1.8 Max. 25 10 1.8 2.3 12.5 0.01 15 Unit mA V A s C V mA ms
Applied between : UP-VUPC, VP-VVPC, WP-VWPC UN VN WN-VNC (Fig. 3,6) 20 Tj 125C, VD = 15V VD = 15V VD = 15V Detect Tj of IGBT chip 20 Tj 125C VD = 15V, VFO = 15V VD = 15V (Fig. 3,6) Trip level Reset level Trip level Reset level (Note-2) (Note-2)
(Note-2) Fault output is given only when the internal SC, OT & UV protections schemes of either upper or lower arm device operate to protect it.
(Note-3) With ripple satisfying the following conditions: dv/dt swing 5V/s, Variation 2V peak to peak
May 2005
PM50CLB060
FLAT-BASE TYPE INSULATED PACKAGE
PRECAUTIONS FOR TESTING 1. Before appling any control supply voltage (VD), the input terminals should be pulled up by resistores, etc. to their corresponding supply voltage and each input signal should be kept off state. After this, the specified ON and OFF level setting for each input signal should be done. 2. When performing SC tests, the turn-off surge voltage spike at the corresponding protection operation should not be allowed to rise above VCES rating of the device. (These test should not be done by using a curve tracer or its equivalent.)
P, (U,V,W)
IN Fo IN Fo
P, (U,V,W)
VCIN
(0V)
Ic
VCIN
(15V)
Ic
VD (all)
U,V,W, (N)
VD (all)
U,V,W (N)
Fo
U,V,W
trr Irr
CS
VCE Ic 90%
Vcc 90%
VD (all)
P
Ic
10%
10% tc(on)
10% tc(off)
10%
Fo
U,V,W
VCIN
CS
Vcc
td(on)
tr
td(off)
tf
VCIN (15V)
Fo
VD (all)
Ic
P, (U,V,W) A
IN Fo
Constant Current SC
Pulse VCE
VCIN (15V)
Ic
VD (all)
U,V,W, (N)
Fo toff(SC)
0V
IPM input signal VCIN (Lower Arm)
1.5V
2V
1.5V
0V
2V
1.5V
2V
tdead
tdead
tdead
1.5V: Input on threshold voltage Vth(on) typical value, 2V: Input off threshold voltage Vth(off) typical value
May 2005
PM50CLB060
FLAT-BASE TYPE INSULATED PACKAGE
P
20k 10
Vcc Fo In
OT OUT Si U
VD
IF
0.1
VVP1 VFo
1.5k
VD
VD
20k
WP VWPC
IF
10
UN
0.1
In GND GND N OT
20k
IF
10
Vcc VN Fo In
OUT Si
0.1 20k
Vcc Fo In
OT OUT Si NC
VD
IF
WN
0.1
VNC
GND GND
NC 5V
1k
Fo
1.5k
NOTES FOR STABLE AND SAFE OPERATION ; Design the PCB pattern to minimize wiring length between opto-coupler and IPMs input terminal, and also to minimize the stray capacity between the input and output wirings of opto-coupler. Connect low impedance capacitor between the Vcc and GND terminal of each fast switching opto-coupler. Fast switching opto-couplers: tPLH, tPHL 0.8s, Use High CMR type. Slow switching opto-coupler: CTR > 100% Use 4 isolated control power supplies (VD). Also, care should be taken to minimize the instantaneous voltage charge of the power supply. Make inductance of DC bus line as small as possible, and minimize surge voltage using snubber capacitor between P and N terminal. Use line noise filter capacitor (ex. 4.7nF) between each input AC line and ground to reject common-mode noise from AC line and improve noise immunity of the system.
May 2005
PM50CLB060
FLAT-BASE TYPE INSULATED PACKAGE
PERFORMANCE CURVES
OUTPUT CHARACTERISTICS (INVERTER PART TYPICAL) COLLECTOR-EMITTER SATURATION VOLTAGE (VS. Ic) CHARACTERISTICS (INVERTER PART TYPICAL)
60 Tj = 25C
VD = 15V
50 40 30 20 10 0
1.5
0.5
1.5
1.5
100
7 5 4 3 2
101
4 5 7 101
3 4 5 7 102
101
100
7 5 4 3 2 ESW(on)
100
7 5 4 3 2
101
7 ESW(off) 5 4 3 2
101
102
4 5 7 100
May 2005
PM50CLB060
FLAT-BASE TYPE INSULATED PACKAGE
102
VD = 15V
7 5 4 3 2
trr
7 5 4 3
Irr
101
7 5 4 3 2
101
7 5 4 3 2
101 trr VCC = 300V VD = 15V Irr Tj = 25C 2 Tj = 125C Inductive load 100 2 3 4 5 7 102 2 3
7 5 4 3
100
102
3 4 5 7 101
VD = 15V Tj = 25C 40
7 5 3 2
101
7 5 3 2
ID (mA)
30 N-side
20
10 P-side 0 0 5 10 15 20 25
102 Single Pulse 7 5 IGBT Part; Per unit base = Rth(j c)Q = 0.95C/ W 3 FWDi Part; 2 Per unit base = Rth(j c)F = 1.61C/ W 103 5 10 2 3 5 7104 2 3 5 7103 2 3 5 7102 2 3 5 7101 2 3 5 7100 2 3 5 7101 TIME (s)
fc (kHz)
May 2005