San Jose State University Department of Electrical Engineering

ELECTRICAL ENGINEERING SENIOR PROJECT

Microwave Amplifier Design (part 1)

by

Steve Garcia
Jaime Cordoba Inderpreet Obhi
December 15, 2003

Objective The goal of our senior design project was to design and build a prototype single stage Microwave power amplifier operated at 2.4 GHz with a linear region of operation up to our desired output of 1 watt or 30 dBm. This project was chosen because of its apparent complexity and the RF design experience that would be gained by the end of the project. Project Specifications: As a design team, we came to the conclusion that we wanted to design our amplifier to operate in the 2.4 GHz ISM (Industrial, Scientific, and Medical) Band. Typical 2.4 GHz Microwave amplifiers on the market were researched and comparable target specifications were proposed. The overall target specifications of the amplifier design are as follows: Operating frequency @ 2.4GHz Output power of 1 watt (30 dBm) Obtain a gain of +10 ~12db 1dB compression >= 30dbm Cost < $ 100 Application The applications of our proposed device include many products in the field of microwave communications. One of the important applications of a Microwave power amplifier is in the output stage of a transmitter where a signal needs amplification before it is transmitted. A high power amplifier is needed for transmitting a signal through an antenna and a medium. The Microwave power amplifier amplifies the input signal after the signal has been modulated in the transmitter. The High power amplification step is necessary for every application of antenna transmission.

Mixer
RF output Transmitted Data Signal
High Power RF Amp

Local Oscillator

Modulated Signal

Figure 1: General Transmitter Output Stage

Design Methodology A power amplifier is an amplifier that takes a low or intermediate level signal and significantly boosts its power level. At low frequencies this might be a trivial design which would only involve the careful choice of a DC bias circuit designed for maximum power output. But our chosen amplifier design is designed to operate at the microwave frequency of 2.4 GHz. When operating at this frequency, transmission line theory comes into the picture. The high frequency and short wavelength of microwave energy make for difficulties in analysis and design of microwave components and systems. Matching of the input and output of the transistor must be considered and designed around. A typical block diagram of a single-stage RF amplifier is shown below.

Input Matchng Network

Transistor

Output Matchng Network

M1

M2

RF AMP

Biasing Network

Figure 2: General Microwave Amplifier Topology

This was the basic topology that we adhered to through our design procedure. The basic design flow for this topology is as follows: Choose an Microwave Transistor based on design specifications Design a DC Biasing circuit for desired operation: Class A, Class B, Class C, or Class AB Design the Input and Output Matching Circuits based on the desired type of amplifier: Low-Noise Amp, High-Gain Amp, or High-Power Amp Because our design is that of a high-power device, there is a more specific design flow to follow when designing a high-power microwave amplifier that is illustrated in the book, Microwave Circuit Design Using Linear and Nonlinear Techniques by Vendelin, Pavio, and Rohde. This design method is based strictly on using small-signal S-parameters for the design of M1 (the input matching circuit) and M2 (the output matching circuit). It also addresses the proper form of biasing for maximum output power. The design flow is as follows: Obtain transistor static IV curves Using IV curves, design the bias circuit for the transistor in order to achieve Class A operation Obtain the transistor S-parameters for the determined bias values Using IV curves, define the optimum load line for maximum output power and determine the resistance value, RL, corresponding to this load line Design M2 for maximum output power using the value of RL

Determine S11 with M2 at output and design input matching circuit, M1, for zero reflection.

The IV curve of the transistor is the starting point for the design. An example of one is shown below:

ID

Load Line

useable region

useable region

VDS
Operating Point Figure 3: FET Transistor IV Curve

From the IV curve, the usable regions of ID and VDS can be determined. For Class A operation, the DC operating point should be centered in these usable regions. This determined operating point will define the VGS and VDS in the bias circuit design. In order to obtain maximum power from this device, we must define a load line that fully spans these usable regions. The slope of this load line will determine the large-signal load impedance, RL, for maximum transistor output power. In other words, RL is used as the goal impedance to be presented to the devices drain terminal by the output circuit in order to achieve maximum RF power output. This value of RL defines the output matching circuit, M2. The Smith chart is then used to define the lossless output circuit M2 by matching RL to 50 at the design frequency. With M2 designed, the input matching circuit, M1, can then be designed using S11. M1 should be designed for zero input reflection. To do this, the Smith chart is used by matching S11 to 50 at the design frequency. This design method should result in a high power amplifier with little input reflection, IN. It should be observed that the output match will be poor because it is intentionally mismatched in order to achieve maximum RF power generation. In other words, the output match is optimized on RL rather than the device's S22.

It should be noted that this design method for high power works even though small-signal S-parameters are used as a design basis. Ideally, large signal S-parameters should be used because power amplifiers are inherently large signal components. This is because they operate into the power saturation area of the IV curve which is, in most cases, a non-linear region. Ideally, a set of large-signal S-parameters would include these non-linearities and would characterize a transistor for high power applications but unfortunately device manufacturers do not provide them. This is because the measurement of large-signal S-parameters is difficult and is not properly defined. Fortunately, small-signal S-parameters are suitable for use in large-signal amplifier design when they are operating in Class A. Although this design procedure may seem straight forward, the actual design process turned out to be much more involved.

Design Environment: Microwave Office It was obvious from the start that our amplifier would need to be designed in the software environment if we actually wanted to build it. There are several software packages in the industry that are used for the design and simulation of RF circuits. The one that we chose to use was Applied Wave Researchs Microwave Office. The primary reason for this choice was that we could obtain our own trial copy which gave us much more flexibility in the design process. Microwave Office is one of the top three industry standard RF design and simulation packages which also made it very attractive. Learning the use and capabilities of the software through the design process turned out to be very time consuming but the experience gained with the software will no doubt be invaluable in an RF career. We also used Agilent Technologys Advance Design Software for parallel design and comparison in the early stages of design. This was done primarily to gain a little experience with comparable software. Design Phase I: Obtaining a Non-Linear Device Model The first step in the whole design process was to choose a transistor. We chose the Filtronic LP1500 transistor in a P100 package which is a 1 Watt power PHEMT. The LP1500P100 is a packaged Aluminum Gallium Arsenide / Indium Gallium Arsenide (AlGaAs/InGaAs) pseudomorphic High Electron Mobility Transistor (pHEMT). This transistor was chosen because it met all of the requirements for our target specifications. The most unexpected problems that we encountered when we started our design was that there are no perfect non-linear models for microwave transistors. The non-linear model given for the LP1500 does not generate the actual S-parameters of device test data that they also supply. Filtronics supplies, on their website, a Cutice-Cubic Non-Linear Device Model is given along with a set of actual S-parameters of a tested LP1500P100 device at a specific DC bias. But when we compared this test data with the Sparameters that are generated by the non-linear device model in Microwave Office simulation, the values did not match at our design frequency of 2.4 GHz. We found the solution to this problem by consulting a professional in the design field. We were advised to optimize the non-linear device model for our design frequency by adjusting various parameter values in the non-linear model. The Curtice-Cubic non-linear device model that we obtained from Filtronics has a total of 36 parameters. The optimization procedure of the non-linear model involved changing arbitrary values one at a time, running S-parameter simulation,

and comparing the results of simulation with that of the given device test data. This was an especially time consuming procedure because it is a hit-and-miss method. We first had to determine which of the 36 device model parameters made the most significant changes in the S-parameter simulation. Then we had to adjust them while watching all 4 S-parameters. This was quite frustrating because changing one parameter might bring one of the S-parameters values come with in the desired range but would, at the same time, make another S-parameter deviate further from the desired value. We realized how hard it was to bring every device model S-parameter close to that of the actual test data values, so we concentrated on optimizing the input and output matching S-parameters; S11 and S22 respectively, while allowing more error within the through parameters; S21 and S21. This decision was made because obtaining the right matching in the simulation environment would ensure good matching in the realized amplifier circuit. In other words, designing around a device model with S11 and S22 close to the actual device values should guarantee a properly matched circuit when it is actually built. It should be noticed that optimization would not necessarily be needed if the amplifier circuit were only to designed and tested in the software environment. Below is a graphical representation of the actual device Test Data S-parameters (Blue Trace), the nonoptimized model (Green Trace), and our final optimized device model (Pink Trace). Notice the optimization at our design frequency, 2.4 GHz of S11 and S22.

S[1,1] LP 1500 Test Data S[1,1] Optim ized Package Model S[1,1] Factory P ackage M odel
0. 4
6 0.

LP1500 S11
1.0

Swp Max 18GHz

2. 0

0.8

3.

0
4. 0

5.0

10.0

0.2

0.4

0.6

0.8

1.0

2.0

3.0

4.0

5.0

.6

-0

-0.8

0 2.

-1.0

-3 .0

2.4 GHz -0.4 r 0.11 x -0.18

Swp Min 0.5GHz

-5. 0

-0.

-4 .0

2.4 GHz r 0.11 x -0.37

-10.0

0.2

2.4 GHz r 0.13 x -0.23

10.0

LP1500 S11
0

-1

2.4 GHz -1.738 dB 2.4 GHz -1.854 dB

DB(|S[1,1]|) LP1500 Test Data DB(|S[1,1]|) Optimized Package Model DB(|S[1,1]|) Factory Package Model

-2

-3

2.4 GHz -2.164 dB

-4

-5 0.5 5.5 10.5 Frequency (GHz) 15.5 18

2.4 GHz r 0.73 x -0.12

1.0

0.5

0.6

0.7

0.8

0.9

1.2

1.4

1.6

1.8

-0 .1
-0.2
3 -0 .
4 -0 .
.5 -0

2.4 GHz r 0.83 x -0.35

-0

.9

2.4 GHz r 0.79 x -0.35

.6 -0
7 0.

.8 -0

Swp Min 0.5GHz

2.0

0. 6

S[2,2] Factory Package Model

0. 5

0. 8

0. 7

S[2,2] Optimized Package M odel

Swp Max 18GHz

9 0.

S[2,2] LP1500 Test Data

LP1500 S22

0 1.

2 1.

0 .4

0 .3

0.2

0.1

LP1500 S22
-5 -7

2.4 GHz -12.92 dB

-10 -13

-16 -19 -22 0.5

2.4 GHz -13.55 dB 2.4 GHz -15.28 dB

5.5 10.5 Frequency (GHz)

DB(|S[2,2]|) LP1500 Test Data DB(|S[2,2]|) Optimized Package Model DB(|S[2,2]|) Factory Package Model

15.5

18

S[1,2] LP1500 Test Data S[1,2] Optimized Package Model

0.5

0.6

0.7

0.8

0.9

1.0

1.2

1.4

1.6

1.8

2.4 GHz r 1.06 x 0.04

-0 .1
-0.2
3 -0 .
4 -0 .
.5 -0

.6 -0
7 0.

.8 -0

-0

Swp Min 0.5GHz

.9

2.0

0 .3

0.2

2.4 GHz r 1.03 x 0.05

0. 6

S[1,2] Factory Package Model

0. 5

Swp Max 18GHz

2.4 GHz r 1.05 x 0.04
0. 8

9 0.

LP1500 S12
0. 7

0 1.

2 1.

0 .4
0.1

LP1500 S12
-10

-20

2.4 GHz -29.12 dB 2.4 GHz -30.11 dB 2.4 GHz -30.89 dB

DB(|S[1,2]|) LP1500 Test Data DB(|S[1,2]|) Optimized Package Model DB(|S[1,2]|) Factory Package Model

-30

-40 0.5 5.5 10.5 Frequency (GHz) 15.5 18

LP1500 S21
60

Mag Max 20
12 0

2.4 GHz Re 0.84 Im 4.24

Swp Max 18 GHz

45

90

75

105

13 5
15 0

30

165

-180

-165

2.4 GHz Re -0.04 Im 5.07

0 15

2.4 GHz Re 1.36 Im 6.79

15

-15

-3

S[2,1] LP1500 Test Data

35 -1
-6

20

S[2,1] Optimized Package Model

0
-105 -75

-4 5

-1

5 Per Div

S[2,1] Factory Package Model

Swp Min 0.5 GHz

-90

LP1500 S21
30

2.4 GHz 16.81 dB

20

DB(|S[2,1]|) LP1500 Test Data DB(|S[2,1]|) Optimized Package Model DB(|S[2,1]|) Factory Package Model

2.4 GHz 14.09 dB

10

2.4 GHz 12.72 dB

-10 0.5 5.5 10.5 Frequency (GHz) 15.5 18

Design Phase II: IV Curve With an acceptable device model obtained, the actual design process could begin. The curvetracer in Microwave Office was used to generate the LP1500 IV curves from which an operating point and load line could be determined.

IV Curve of LP1500
700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 0 1 2 3 4 5 6 7

IVCurve (mA) CurveTrace

8 9 10 11 12 13 14 15 16 17 18 Voltage (V)

From this IV curve, the operating point was designed. The DC bias values turned out to be VDD=8.5 Volts and VGS= -0.5 Volts. The maximum power load line was determined and has a RL value of 22 ohms. RL was then translated to the Smith Chart and matched to 50 ohms using lumped elements.

6 0.

RL= 22 ohms
0. 4

Smith Chart
0.8

Match to 50 Swp Max ohms

1
2. 0

1.0

3.

0
4. 0

5.0

10.0

0.2

0.4

0.6

0.8

1.0

2.0

3.0

4.0

5.0

-0

.4
.0 -2

-0

.6

-0.8

Swp Min -1

This determined the output match M2. M1 was then designed using S11 on the smith chart as described earlier. The final lumped element circuit is shown below.

-1.0

-5. 0

-0.

2
-4 .0

-10.0

-3 .0

0.2

10.0

DCVS ID= VGS1 V= -0.5 V

DCVS ID= VDD1 V= 8.5 V

PORTFN P= 1 Z=50 Ohm Freq=2.4 GHz Pwr=16 dBm Ang=0 Deg Tone=1

INDQ ID= Lrfchoke1 L= 100 nH Q= 0 FQ=0 GHz CAP ALPH= 1 ID= C1 C= 10.34 pF

SUBCKT ID= S1 NET= "LP1500 Package Model"

I NDQ ID= Lrfchoke2 L=100 nH Q= 0 FQ=0 GHz IND ALPH=1 I D=L2 L= 1.64 nH

1
PORT P=2 Z=50 Ohm

CAPQ ID= Cdcblock1 IND C= 100 pF ID= L1 Q= 0 L= 1.17 nH FQ=0 GHz ALPH=1

CAP ID= C2 C= 1.49 pF

CAPQ ID= Cdcblock2 C= 100 pF Q= 0 FQ=0 GHz ALPH=1

Because the circuit was to be built on a substrate, a mixed lumped element microstrip design had to be generated based on the above design. This is because every connection between all of the elements are in actuality microstrip pieces and therefore had to be considered and modeled in the design. This was a very long and drawn out process but it finally yielded a working circuit. This is the final circuit in Microwave Office along with the S-parameters and 1 dB compression point determination:

VIA ID= V4 D = 50 mil H = 32 mil T= 1.4 mil 1 RHO=

VIA ID= V3 D= 50 mil H= 32 mil T= 1.4 mil RHO= 1

MLIN ID=TL16 W =160 mil L = 500 mil

MLIN ID=TL15 W =160 mil L = 500 mil

CAPQ ID=Cdcblock3 C= 1000 pF Q =0 F Q = 0 GHz ALPH=1

RES ID=RD1 R = 22.5 Ohm

DCVS D = VDD1 I V= 15.78 V

MSUB Er= 3.38 H= 32 mil T= 0.669 mil Rho= 1 Tand=0.0021 ErNom= 3.38 Name= R O 1

DCVS I D = VGS1 V = -0.4775 V

CAPQ ID= Cdcblock4 C= 1000 pF Q=0 F Q = GHz 0 ALPH= 1

MLIN ID=TL10 W = 160 mil L = 500 mil INDQ ID= Lrfchoke2 L = 1000 nH Q=7 F Q = 0.00796 GHz ALPH=1

MLIN I D = TL3 W = 160 mil L = 500 mil

MLIN ID=PAD10 W =50 mil L=100 mil W 1=238.8 L1=480.8

INDQ ID=Lrfchoke1 L = 1000 nH Q =7 F Q = 0.00796 GHz ALPH=1

PORT_PS1 P=1 Z=50 Ohm PStart=0 dBm PStop=30 dBm PStep=0 . 2 d B Ang=0 Deg

MLIN ID=PAD9 W =50 mil L=100 mil

MSTEP$ D = TL22 I 2 MLIN I D = TL8 W = W 1 mil L = L1 mil

3 1

IND ID=L 3 L =M2ind nH

W4=59.79 L4=32.17

MTEE ID= TL12 W 1=W 4 mil W 2=74.5 mil W 3=120 mil 1 2 3

CA P ID=DCblock2 C=1000 pF

MTEE I D = TL5 W 1=W 4in mil W 2=120 mil W 3=120 mil 2 MLIN ID=TL7 W =74.5 mil L = 500 mil 3 MLIN ID= PAD4 W = 120 mil L=60mil 1

W4in=240 L4in=10 3 1 MLIN ID= TL4 W = 4in mil W L = L4in mil MLIN I D = PAD2 W = 120 mil L = 60 mil 2 MSTEP$ I D = T L21 1

MTEE I D = TL9 W1= 120 mil W2= W 1 m i l W3= 160 mil

M2ind=1.8 MLIN I D = PAD5 W = 120 mil L = 60 mil MLIN ID=PAD6 W =120 mil L =60 mil MSTEP$ ID= TL19

MLIN ID=TL11 W=W4mil L = L4 mil

MLIN ID= TL14 W = 74.5 mil L = 500 mil

PORT P= 2 Z= 50 Ohm

CAP ID=DCblock1 C=1000 pF

M1cap=39 CAP ID= C1 C= M1cap pF

MSTEP$ ID=TL18

MTEE ID= TL2 W1= 1 2 0 m i l W2= W1in mil W3= 1 6 0 m i l

W1in=423.2 3 L1in=167.7 SUBCKT ID=S1 NE T = "LP1500 Package Model" CA P ID=M2cap1 C= M2cap pF M2cap=0.5

MLIN ID= PAD7 W = 120 mil L=60mil

MLIN I D = PAD1 W = 120 mil L = 60 mil

MLIN I D = TL1 W = W 1in mil L =L 1 i n m i l

IND ID= L1 L= M1ind nH

M1ind=58

MLIN ID=PAD3 W =120 mil L = 60 mil

MLEF ID=TL23 W = 120 mil L = 60 mil

MLIN D = PAD0806 I W = 120 mil L=60 mil

MSTEP$ ID=TL17

MLEF ID= TL6 W = W6in mil L=L6in mil

L6in=2687 W6in=165.1

15

2.4 GHz 14.56 dB Magnatude of S Parameters

DB(|S[1,1]|) (R) LAYOUT

10

2.4 GHz -2.763 dB

DB(|S[2,1]|) (L) LAYOUT DB(|S[1,2]|) (R) LAYOUT DB(|S[2,2]|) (R) LAYOUT

-10

2.4 GHz -10.3 dB

-20

-30

2.4 GHz -28.12 dB

-5 1 2 3 Frequency (GHz) 4 4.8 -40

S[1,1] LAYOUT S[2,2] LAYOUT

Smith Chart S Parm

1.0
6 0.

Swp Max 2.8GHz

2. 0

0.8

-0 .6

-0.8

-2

.0

-1.0

-3

.4 -0

Swp Min 2GHz

-5.

-4 .

2 -0.
0

-10.0

2.4 GHz r 0.32 x -0.98

10.0

0.2

0.4

0.6

0.8

1.0

2.0

3.0

4.0

5.0

.0

0.

4
0.2

0 3.
0 4.

2.4 GHz r 1.10 x -0.67

5.0

10.0

IVCurve (mA) CurveTrace

IV Curve and Dynamic Load Line at 1dBC

700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 0 1 2 3 4 5 6 7

Dynamic Load Line (mA) Final Layout

8.657 V 308.9 mA

8 9 10 11 12 13 14 15 16 17 18 Voltage (V)

Gain vs Input Power

DB(PGai nSP[PORT_1,PORT_2,1]) POWER_LAYOUT

16 15 14

-10 dBm 14.56 dB

1 dB compression of gain at input power of 13.21 dBm

13 12

13.21 dBm 13.55 dB

11 10 9 8 7 6

-10

-8

-6

-4

-2

4 6 8 Power (dBm)

10

12

14

16

18

20

P1dB Compression
35 30 25 20 15 10 5 -10 -8 -6 -4 -2 0 2 4 6 8 Power (dBm) 10 12 14 16 18 20 Compression Point at 29.24 dBm
AMtoAM[PORT_2,1] (dBm) power

13.5 dBm 29.24 dBm

Which, in physical layout looks like this:

This layout was translated to the appropriate file for the circuit milling machine after which the circuit was built and tested.

VDD

Input VG GND

Outpu