Mixed-Signal-Electronics

PD Dr.-Ing. Stephan Henzler

Stephan Henzler

Mixed-Signal-Electronics 2011/12

Chapter 7
Comparators

Stephan Henzler

Mixed-Signal-Electronics 2011/12

Ideal Comparator
Compare input signal to reference and provide binary output signal

Often same symbol as for opamp (reasonable as open loop opamp behaves like a comparator) Comparator is essentially an amplifier with saturation, ideal comparator means infinite gain in VCVS not realistic
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Static Characteristics of Comparator

Comparator gain

Maximum voltage for negative saturation VDL Minimum voltage for positive saturation VDH Comparator resolution: (min. voltage increment, determines comparator gain)

Offset voltage: Horizontal shift of characteristic Input common mode range

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Dynamic Characteristics of Comparator

Note: Comparators work in large signal mode of operation basic circuit theory to reveal trade-offs and mechanisms simulation to determine actual performance figures Main dynamic performance figure: propagation delay td

Stephan Henzler

Mixed-Signal-Electronics 2011/12

Operational Amplifier as Comparator

Opamp in open-loop configuration is comparator asynchronous relatively slow due to high gain and stability requirement offset error (may be compensated by correlated double sampling,
but this also means synchronous operation)

Consider DC operating point at input for a reference voltage 0 Compensation cap may be disconnected during latching
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OpAmp Comparator Dynamics

Gain-Bandwidth trade-off gain determined by desired resolution bandwidth determined by desired propagation delay Amplifier model Response of Stable 1st Order Linear System
1 0.9 0.8 -0.1 -2.0 -0.5 -1.0 -1.0 -0.5 -2.0 -0.1

Step response

output signal [norm]

0.7 0.6 0.5 0.4 0.3 0.2

Propagation Delay

0.1 0 0 2 4 6 8 10

time [AU]

Stephan Henzler

Mixed-Signal-Electronics 2011/12

Comparator Propagation Delay

Linear mode of operation

Propagation delay for small input signals is determined by linear small signal dynamics of amplifier

Slew rate limited mode of operation

Propagation delay for large input signals is dominated by slew rate of opamp output stage Propagation delay for slew rate limited operation

Stephan Henzler

Mixed-Signal-Electronics 2011/12

Discrete Time Comparators

In some applications comparator function only desired during certain intervals at certain discrete time instances Allows for offset compensation via auto-zeroing and other switched capacitor benefits Allows for amplifiers in positive feedback configuration

full level always reached gain boosting (reuse one amplifier by cyclic amplification
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Track & Latch Circuit I

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Mixed-Signal-Electronics 2011/12

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Track & Latch Circuit II

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Principle of Track-and-Latch Stage

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Linear Dynamic of Latch

Linear small signal analysis (ref. Schaltungstechnik 2) Node voltages

Differential voltage
output signal [norm]

Response of Instable 1st Order Linear System (Latch)

1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 0.01 0.1 0.4

Propagation delay

time [AU]

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Latched Comparators I

Standard architecture for high-speed comparators Latch offset voltage limits resolution of latch-only comparator Two step approach: analog pre-amplifier stage(s) regenerative track and latch stage

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Latched Comparators II

Pre-amplifier: 1-3 amplifier stages low gain, high-speed delay along amplifier chain separation of input from latch to reduce loading and avoid kickback effect
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Latched Comparators III

Track & latch circuit: amplifies signal in track mode restores (regenerates) signal to full rail in regenerative latch mode (positive feedback)

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Current Mode (CML) Latch

Combines amplifier and latch functionality

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Memory and Hysteresis in Comparators

Hysteresis: Switching threshold is different when switching from low to high and from high to low, respectively. Useful to avoid bouncing outputs for small (noisy) signals near comparator threshold

Memory effect: Kind of hysteresis that causes the comparator decision to be dependent on previous decisions. Has to be strongly avoided in Nyquist rate ADCs such as flash converters.
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Elimination of Memory Effect

Precharge and equalize circuit elements eliminate all information from previous cycles and decisions
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Switched Capacitor Comparator

Offset compensated Threshold determined by capacitynce ratio

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