FGMOS: A normal transistor (MOSFET) uses a gate electrode to open or close the connection between two other electrodes,

called the source and drain, allowing the device to function as an on/off switch.

http://info.tuwien.ac.at/theoche... When charge is placed on the gate electrode, the semiconducting purple region becomes conductive, and the source and drain are connected. When charge is removed from the gate electrode, the purple region becomes insulating, and the source and drain are disconnected. Note that when the power to a MOSFET is turned off, charge drains from the gate through the circuit it's connected to, and it reverts to being "off" (non-conducting). http://en.wikipedia.org/wiki/Mosfet A floating gate transistor has an additional electrode between the gate and the semiconductor. Unlike the other electrodes, however, the floating gate is not connected to anything (hence the name 'floating').

http://en.wikipedia.org/wiki/Fil... By running (relatively) high currents through the device, electrons can be made to punch through the insulating layer and get stuck in the floating gate. There they act to turn the device on like in the gate of a normal MOSFET, connecting the source and drain. However, unlike the normal MOSFET, when power is lost, the floating gate retains its charge since it isn't connected to anything. Thus, the device remembers its "on" state even when power is lost. This effect allows the device to be used in portable storage media such as flash memory. Why NMOS is strong 0 and PMOS is strong 1?

NMOS need +Vt for on,when gate voltage is 1(Vdd) and source voltage applied is 0, than Vgs(GATE to SOURCE) become Vg-Vs=Vdd-0=Vdd which is greater than Vt so it allow strong 0 and output is 0.If source voltage applied is 1(Vdd),than Vgs=Vg-Vs=Vdd-Vdd=0 so NMOS not allow 1 so NMOS act as open switch. But if source voltage is Vdd-Vt ,than Vgs=Vg-Vs=Vdd-(Vdd-Vt)=Vt......................which on the NMOS so output is Vdd-Vt which is weak 1. If we apply Vdd=Vs>(Vdd-Vt) input is not pass to output.But the quoted last line seems erroneous, since it violates the boundary condition, from commonsense point of view. (also

he uses Vs to refer to Vi).If input voltage (Vi) exceeds (Vdd-Vt), it says input is not passed to output. In reality output will not be zero volts then, instead it will be= Vdd-Vt.This is also because the output capacitance at the load charges-up from zero onwards, till the output reaches the value = (Vdd-Vt), at which point the channel gets cut-off (due to Vgs < Vt), at that instant.

In electrical engineering, noise margin is the amount by which a signal exceeds the minimum amount for proper operation. It is commonly used in at least two contexts: In communications system engineering, noise margin is the ratio by which the signal exceeds the minimum acceptable amount. It is normally measured in decibels. In a digital circuit, the noise margin is the amount by which the signal exceeds the threshold for a proper '0' or '1'. For example, a digital circuit might be designed to swing between 0.0 and 1.2 volts, with anything below 0.2 volts considered a '0', and anything above 1.0 volts considered a '1'. Then the noise margin for a '0' would be the amount that a signal is below 0.2 volts, and the noise margin for a '1' would be the amount by which a signal exceeds 1.0 volt. In this case noise margins are measured as an absolute voltage, not a ratio. Noise margins for CMOS chips are usually much lesser than TTL because the VOH min is closer to the power supply voltage and VOL max is closer to zero. In simple words, Noise margin (in circuits) is the amount of noise that a circuit can withstand. Noise margins are generally defined so that positive values ensure proper operation, and negative margins result in compromised operation, or perhaps outright failure.

The threshold voltage, commonly abbreviated as Vth, of a MOSFET is usually defined as the gate voltage where an inversion layer forms at the interface between the insulating layer (oxide) and the substrate (body) of the transistor. The formation of the inversion layer allows the flow of electrons through the gate-source junction. The creation of this layer is described next.