GFEC MAX II Starter Kit

User Guide

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Address : 14F , 207-5, Sec 3,Peihsin Rd., Hsintien, Taiwan R.O.C. TEL: 886-2-8913-2200 FAX: 886-2-8913-2277

Galaxy Far East Corp. Contact Details

Taipei Head Office Address : 14F , 207-5, Sec 3,Peihsin Rd., Hsintien 231, Taiwan R.O.C. TEL:886-2-8913-2200 FAX:886-2-8913-2277 Hsinchu Office Address: 3F., No.526, Sec. 1, Guangfu Rd., Hsinchu City 300, Taiwan (R.O.C.) TEL:886-3-578-6766 FAX:886-3-577-4795 :<800>5610F8 TEL:886-7-223-1338 FAX:886-7-222-4051 Technical Support Hotline TEL:0800819595 World Wide Web HTTP://WWW.GFEC.COM.TW

Index
Chapter 1 Introduction...4 Chapter 2 Quartus II quick overview....19 Chapter 3 Download testing program.36 Chapter 4 ALU example48 Chapter 5 7-Segment display example.51 Chapter 6 Clock example.54 Chapter 7 Traffic signal example.63 Chapter 8 Gaming machine example.71 Chapter 9 RS-232 example80 Appendix A QuartusII 4.2 installation procedure..94 Appendix B License application Procedure99 Appendix C Install Byteblaster in Windows XP..104 Appendix D MAX II Starter Kit Schematic..111

Chapter 1 Introduction

Contents
MAX II Emulation Board Download Cable AC Adapter ( Input : AC 115 V 60Hz / Output : DC : 6V 1A) or USB to DC Cable CD-ROM

Attention
If any component from the above list is missing please contact GFEC or its authorized agent immediately. Please note the extension I/O voltage on this emulation board can only receive signals up to 3.3V. If by some mistake you end up burning the EPM1270T144C5ES CPLD, you can buy a new device from us. But you need to re-solder the new CPLD onto the board. Under normal usage conditions, this emulation board has a three-month warranty

Feature
This manual explains the usage and operation of the GFEC MAX II Starter Kit. The GFEC MAX II Starter Kit emulation board is specifically designed for Altera MAX II Device Family. But the board can also be used by designers who are interested in simulating and synthesizing programmable logic circuits in their applications. The emulation board is based on the EPM1270T144C5ES CPLD device, which provides 1270 LEs (logic elements), 116 I/O lines and 8-Kbit user Flash Memory. The CPLDs data and detailed specification can be found in the accompanying CDROM or on Alteras Website (http://www.altera.com). Besides the EPM1270T144C5ES CPLD, the emulation board also provides a few peripherals, which enables you to quickly finish your digital-logic designs.

Onboard Peripherals
4 Digitals seven segment LED Displayer 8 Bits DIP Switch 4 Push Buttons 8 LEDs 1 16Mhz Oscillator 1 UART Connector 4 Extension I/O Connectors 44 Pin Socket (for 3.3V 8051 CPU)

Component-side view of MAX II Emulation Board

The following section provides a detailed explanation on the onboard peripherals

4 Digitals seven segment LED Displayer (DS1)

The LED display comprises four groups of seven-segment display, which are inter-connected. Additionally, there is a common pin connected with one group of the seven-segment Display. When one of the common pin is at a high-level signal and one LED of the seven-segment display is at a low-level signal, that LED will be turned on. Although the LEDs of the four groups of seven-segment display are connected together, you can use the common pins to decide which LED should be activated. In general, four different digits are displayed by scanning the common pins. Please refer to Table 1 & Fig 1 for the mapping between the seven-segment display pins and the MAX II Device I/O.

Table 1 Segment pin MAX II I/O 4 Digitals seven segment LED Displayer a b c d e f g DP 37 38 39 40 41 42 43 44

Common pin MAX II I/O Note :

4 Digitals seven segment LED Displayer Digital 1 Digital 2 Digital 3 Digital 4 29 30 31 32

When the common Pin is High, one group of the seven-segment LED displays will be enabled; When the segment Pin is Low, that segment LED will be on.

Fig 1

8 Bits DIP Switch (SW6)

The emulation board provides an 8-bit DIP switch, and when the switch is On, the MAX II device I/O will be Low. You can refer to Table 2 for the mapping between the 8-bit DIP switch signal pins and the MAX II device I/O pins.

Table 2 Switch MAX II I/O DIP1 22 DIP2 21 8 Bits DIP Switch DIP3 DIP 4 DIP 5 DIP 6 16 15 14 13 DIP 7 12 DIP 8 11

NoteON is LowOFF is High

4 Push Button (SW1 SW4)

The emulation board provides four push buttons, which will offer Low signals to MAX II device when pressed, and will stay High when not pressed. Table 3 details the mapping between the push-button switches and the MAX II Device I/O pins.
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Table 3 Push Button MAX II I/O 4 Push Button SW1 SW2 SW3 SW 4 23 24 27 28

NotePress is low

8 LEDs (D1 D8)

When MAX II I/O lines send a Low signal to the LED bank, that LED will be on. Please refer to Table 4 for the mapping between eight LED signal pins and the MAX II Device I/O lines

Table 4 LED MAX II I/O D1 1 D2 2 D3 3 8 LEDs D4 D5 4 5 D6 6 D7 7 D8 8

16M Hz Oscillator
A 16-MHz oscillator of full-length type is provided on this emulation board. The oscillator sends the clock signal to the MAX II Device through JP1 Jumper. Please refer to Table 5 to understand the jumper connections between the signal pins of the 16-MHz oscillator and the MAX II Device I/O lines.

Table 5 JP1
JP1

MAX II

18 / GCLK0P

JP1

20 / GCLK1P

JP1

89 / GCLK2P

JP1

91 / GCLK3P
JP1

44 Pin PLCC Socket (8051 MPU) Pin21

Note: JP1 can be inserted with multiple Jumpers at the same time, to provide multiple sets of clock inputs.

UART Connector (J8)

This emulation board offers a UART connector. Users can configure a UART controller into the MAX II Device, for communicating with other devices using a UART interface. The UART circuit comprises three parts: the first part transforms UART signals from IntersilsICL3232CA device between the 3.3-V voltage level of MAX II I/O and that of RS-232 at +/- 12V levels; the second part contains two LEDs (D9, D10). By observing the D9 (transmit) and the D10 (receive) LEDs you can determine whether the UARTs is transmitting or
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receiving data; the third part is a RS-232 (DB9/F) connector, which can be connects to the PC through a standard RS-232 cable. See Table 6 to understand the relation between the UART Connector and the MAX II Device I/O pins. Table 6 UART Connector (J8) MAX II I/O UART Connector TXD CTS RXD RTS 2 8 3 7 45 48 49 50

4 Extension I/O Connectors (J1 / J2 / J3/ J4)

The EPM1270T144C5ES CPLD provides 116 I/O pins, and some of the extension I/O lines of this emulation board is connected with J1, J2, J3, J4 (through a 2 X 17 connector), respectively. Through this scheme, it is easy for you to connect this connector to other circuit boards. Jumpers J1 to J4 also have Power Pin and GND Pin. The Power Pin provides 3.3V volts without the circuitry for over-current protection. If the extension circuit board needs to draw a large current (300mA and above) from the emulation board, we recommend that this power circuit be provided for on the extension circuit board itself. Also we suggest that in this case you need to connect ground signals of both boards together. Except Power and GND Pins, other pins on J1 to J4 connectors are directly connected to MAX II Device I/O lines. So make sure you do not connect any signals above 3.3V to this connector. Apart from these pins, some pins in the connector are linked with the MAX II CPLD or to some other peripherals on the emulation board (for example, the LED, push-button switches, and so on). Therefore, you must pay attention to whether these peripherals will influence the extension I/O pins. Please refer to Figure 2 and Tables 7, 8 for the relationship between extension I/O connectors and the MAX II Device I/O lines.
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Fig 2

Tables 7
MAX II PIN No. J1 Pin1 J1 Pin2 J1 Pin3 J1 Pin4 1 2 3 4 5 6 7 8 11 12 13 14 15 16 21 22 23 J1 Pin5 J1 Pin6 J1 Pin7 J1 Pin8 J1 Pin9 J1 Pin10 J1 Pin11 J1 Pin12 J1 Pin13 J1 Pin14 J1 Pin15 J1 Pin16 J1 Pin17 J1 Pin18 J1 Pin19 J1 Pin20 J1 Pin21 VCC / 3.3V VCC / 3.3V VCC / 3.3V VCC / 3.3V LED D1 LED D2 LED D3 LED D4 LED D5 LED D6 LED D7 LED D8 DIP8 DIP7 DIP6 DIP5 DIP4 DIP3 DIP2 DIP1 SW1 37 38 39 40 41 42 43 44 45 48 49 50 51 52 53 55 57 58 59 Connector Features MAX II PIN No. J2 Pin1 J2 Pin2 J2 Pin3 J2 Pin4 J2 Pin5 J2 Pin6 J2 Pin7 J2 Pin8 J2 Pin9 J2 Pin10 J2 Pin11 J2 Pin12 J2 Pin13 J2 Pin14 J2 Pin15 J2 Pin16 J2 Pin17 J2 Pin18 J2 Pin19 J2 Pin20 J2 Pin21 VCC / 3.3V VCC / 3.3V Segment a Segment b Segment c Segment d Segment e Segment f Segment g Segment DP RS232 TXD RS232 DTS RS232 RXD RS232 RTS U4 PIN2 / P1.0 U4 PIN3 / P1.1 U4 PIN4 / P1.2 U4 PIN5 / P1.3 U4 PIN6 / P1.4 U4 PIN7 / P1.5 U4 PIN8 / P1.6 Connector Features

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24 27 28 29 30 31 32

J1 Pin22 J1 Pin23 J1 Pin24 J1 Pin25 J1 Pin26 J1 Pin27 J1 Pin28 J1 Pin29 J1 Pin30 J1 Pin31 J1 Pin32 J1 Pin33 J1 Pin34

SW2 SW3 SW4 Digital 1 Digital 2 Digital 3 Digital 4 GND GND GND GND GND GND

60 61 62 63 66 67 68 69 70 71 72

J2 Pin22 J2 Pin23 J2 Pin24 J2 Pin25 J2 Pin26 J2 Pin27 J2 Pin28 J2 Pin29 J2 Pin30 J2 Pin31 J2 Pin32 J2 Pin33 J2 Pin34

U4 PIN9 / P1.7 U4 PIN10 / RST U4 PIN11 / P3.0(RXD) U4 PIN13 / P3.1(TXD) U4 PIN14 / P3.2(INT0) U4 PIN15 / P3.3(INT1) U4 PIN16 / P3.4(T0) U4 PIN17 / P3.5(T1) U4 PIN18 / P3.6 U4 PIN19 / P3.7 U4 PIN33 / ALE GND GND

Tables 8
MAX II Connector J3 Pin1 J3 Pin2 73 74 75 76 77 78 79 80 81 84 85 86 87 88 93 94 95 96 97 J3 Pin3 J3 Pin4 J3 Pin5 J3 Pin6 J3 Pin7 J3 Pin8 J3 Pin9 J3 Pin10 J3 Pin11 J3 Pin12 J3 Pin13 J3 Pin14 J3 Pin15 J3 Pin16 J3 Pin17 J3 Pin18 J3 Pin19 J3 Pin20 J3 Pin21 VCC / 3.3V VCC / 3.3V U4 PIN32 / PSEN U4 PIN31 / P2.7 U4 PIN30 / P2.6 U4 PIN29 / P2.5 U4 PIN28 / P2.4 U4 PIN27 / P2.3 U4 PIN26 / P2.2 U4 PIN25 / P2.1 U4 PIN24 / P2.0 U4 PIN43 / P0.0 U4 PIN42 / P0.1 U4 PIN41 / P0.2 U4 PIN40 / P0.3 U4 PIN39 / P0.4 U4 PIN38 / P0.5 U4 PIN37 / P0.6 U4 PIN35 / R0.7 109 110 111 112 113 114 117 118 119 120 121 122 123 124 125 127 129 130 131 MAX II Connector J4 Pin1 J4 Pin2 J4 Pin3 J4 Pin4 J4 Pin5 J4 Pin6 J4 Pin7 J4 Pin8 J4 Pin9 J4 Pin10 J4 Pin11 J4 Pin12 J4 Pin13 J4 Pin14 J4 Pin15 J4 Pin16 J4 Pin17 J4 Pin18 J4 Pin19 J4 Pin20 J4 Pin21 VCC / 3.3V VCC / 3.3V

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98 101 102 103 104 105 106 107 108

J3 Pin22 J3 Pin23 J3 Pin24 J3 Pin25 J3 Pin26 J3 Pin27 J3 Pin28 J3 Pin29 J3 Pin30 J3 Pin31 J3 Pin32 J3 Pin33 J3 Pin34 GND GND GND GND

132 133 134 137 138 139 140 141 142 143 144

J4 Pin22 J4 Pin23 J4 Pin24 J4 Pin25 J4 Pin26 J4 Pin27 J4 Pin28 J4 Pin29 J4 Pin30 J4 Pin31 J4 Pin32 J4 Pin33 J4 Pin34 GND GND

DC Input Connector
The emulation board is powered by a built-in 3.3V/500mA voltage regulator, and the power can be directly inserted into J5 by using the AC Adapter or the USB-to-DC Cable. Please note that the AC Adapter accepts only 110VAC/60 Hz power signal. Or you can power the board using a power supply (the recommended input voltage is 5~6V) through J6. The G_LED will be lit when the power is supplied to the board.

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JTAG 5X2 Header Connector

Altera MAX II Device features the ISP (In-System Programmable) function. You can use the download cable (Byte Blaster II) supplied with the emulation board, to connect a PCs parallel port with the J7 header on the emulator board. By using Alteras Quartus II software development tool you can download data to the emulation board. Please refer to Fig3 for the definition of pins on the J7 header. Fig3

44 Pin PLCC Socket for MPU(8051)

Place the standard 3.3V 8051 MCU in this socket. Please note that the 8051 MCU I/O Port lines of the emulation board are directly connected to the MAX II Device. Both 8051 CLK and Reset signal buttons are also provided. Please refer to Table 9 for the pin-definitions of the MCU socket.

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Table 9 44 Pin PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 8051 MPU NC P1.0 (T2) P1.1(T2 EX) P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0(RXD) NC P3.1(TXD) P3.2(/INT0) P3.3(/INT1) P3.4(T0) P3.5(T1) P3.6(/WR) P3.7(/RD) XTAL2 XTAL1 GND 63 66 67 68 69 70 71 51 52 53 55 57 58 59 60 61 62 MAX II I/O 44 Pin PLCC 8051 MPU MAX II I/O 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 NC P2.0(A8) P2.1(A9) P2.2(A10) P2.3(A11) P2.4(A12) P2.5(A13) P2.6(A14) P2.7(A15) /PSEN ALE NC /EA P0.7(AD7) P0.6(AD6) P0.5(AD5) P0.4(AD4) P0.3(AD3) P0.2(AD2) P0.1(AD1) P0.0(AD0) VCC/3.3V 95 94 93 88 87 86 85 84 81 80 79 78 77 76 75 74 73 72

List of all devices on the emulation board

Component Reference No. U1 U4 J1,J2,J3,J4 J5 J6 J7 J8
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Feature Altera MaxII family device MPU 44 Pin PLCC Socket Extension I/O Connectors DC JACK DC Input Header JTAG Header UART Connector

JP1 D1,D2,D3,D4,D5,D6,D7,D8 D9 , D10 SW1,SW2,SW3,SW4 SW6 DS1 Y1 SW5

Clock Input Selector LED UART Data Displayer Push Button Switch DIP Switch 4 Digital 7 Segment LED Displayer Oscillator Socket MPU Reset Push Button Switch Power LED

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Installing Quartus II and downloading data

. To install Altera Quartus II 4.1 SP2 version, from the CD-ROM menu, and click Install Quartus II Web Edition.

. Before you start on your design you need to apply for a license from Altera 1. Open Quartus II 4.1 menu (Start => Program => Altera => Quartus II 4.1) 2. In the main menu, choose Tools => License Seup => copy (NIC) ID 3. Then click on Quartus II Web Edition Software License in http://www.altera.com/support/licensing/lic-index.html, to get a free Quartus II license from Altera. 4. Altera will send back a License.dat file through e-mail. By opening the window of License Setup and going through the License file, you provide the location of the License.dat file 5. The installation is complete when the screen on the right appears

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. Open Programmer from Tools after finishing Compiling 1. Select Hardware Setup 2. Select ADD Hardware and click OK 3. Highlight ByteBlaster, Select Hardware, and click close.

. Set Mode => JTAG . Add File, select pof file . Click as shown if UFM is unused. . Insert J7 in download cable. . Insert Special Adapter or USB to DC Cable in J6. . Click Start and then you can programming

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Chapter 2 Quartus II Quick Overview

In this chapter, we will demonstrate a marquee example designed using VHDL, showing how we can use Quartus II to perform process such as adding new projects, program design, compilation & downloading. Prior to starting the procedures below, you will need to copy files located under "ledtest" folder in the CD-ROM to your hard disk, the example below copies "ledtest" folder to "C:\altera\qdesigns42"

Part 1. Adding New Projects

Step 1. Open Project Wizard, [File] [New Project Wizard].

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Step 2. Click [Next]

Step 3.

Enter Working directory and project name, then click [Next]

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Step 4.

Click [Add All] to add "ledtest.vhd" into this project, then click [Next]

Step 5.

Select device, select MAX II series' EPM1270T144C5ES

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Step 6.

Click [Next]

Step 7.

Click [Finish] to complete creation of a new project.

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Part 2. Create Program File

Quartus II has a few means of inputting circuits that include AHDL, Block Diagram/Schematic, EDIF, Verilog HDL, and VHDL File. In this chapter we will use VHDL to complete marquee program example. To create new VHDL program select [File][New], to open design method option. Under [Device Design Files] choose [VHDL File] to open new VHDL design file. Since a completed program code has been provided for this example, therefore all you need to do is open the file "ledtest.vhd"

Step 8. Open File ledtest.vhd

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Marquee Program Code and Explanation

Marquee Program Code
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity ledtest is port( clk :in std_logic; rst :in std_logic; u_d :in std_logic; sel :in std_logic_vector(1 downto 0); led :out std_logic_vector(7 downto 0) ); end ledtest; architecture a of ledtest is signal cnt : std_logic_vector(2 downto 0); signal clkcnt: std_logic_vector(19 downto 0); signal clk2 : std_logic; signal led_t1,led_t2,led_t3,led_t4:std_logic_vector(7 downto 0); begin process(rst,clk) begin if rst='0' then clkcnt<=(others=>'0'); clk2<='0'; elsif clk'event and clk='1' then if clkcnt="11110100001001000000" then clk2<=not clk2; clkcnt<=(others=>'0'); else clkcnt<=clkcnt+1; end if; end if; end process; process(rst,clk2) begin if rst='0' then cnt<="000"; elsif clk2'event and clk2='1' then if u_d='1' then cnt<=cnt+1; else cnt<=cnt-1; end if; end if; end process; led_t1<="11111110" when cnt="000" else "11111101" when cnt="001" else "11111011" when cnt="010" else 24

54 "11110111" when cnt="011" else 55 "11101111" when cnt="100" else 56 "11011111" when cnt="101" else 57 "10111111" when cnt="110" else 58 "01111111"; 59 60 led_t2<="01111110" when cnt="000" else 61 "10111101" when cnt="001" else 62 "11011011" when cnt="010" else 63 "11100111" when cnt="011" else 64 "01111110" when cnt="100" else 65 "10111101" when cnt="101" else 66 "11011011" when cnt="110" else 67 "11100111"; 68 69 led_t3<="00000000" when cnt="000" else 70 "11111111" when cnt="001" else 71 "00000000" when cnt="010" else 72 "11111111" when cnt="011" else 73 "00000000" when cnt="100" else 74 "11111111" when cnt="101" else 75 "00000000" when cnt="110" else 76 "11111111"; 77 78 led_t4<="11101110" when cnt="000" else 79 "11011101" when cnt="001" else 80 "10111011" when cnt="010" else 81 "01110111" when cnt="011" else 82 "10111011" when cnt="100" else 83 "11011101" when cnt="101" else 84 "11101110" when cnt="110" else 85 "11111111"; 86 87 led <= led_t2 when sel="10" else 88 led_t3 when sel="01" else 89 led_t4 when sel="00" else 90 led_t1; 91 end a;

Marquee Program Code Explanation Line No. 1~4 6~14 16~21 23~36 Explanation Component Library Declaration Input & Output Port Declaration Internal Signal Declaration Frequency divider, drops the system frequency of 16MHz to that of marquee frequency of 8Hz clk2.
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38~49 51 ~ 85

3 bits up/down counter. 4 decoder circuit, to generate 4 different combination of marquee signal. Multiplexer, use sel to choose which variation signal is used for output to display on LED.

87~90

We can use this VHDL file to create symbol file, to allow design of circuit using block diagram. Creation of symbols is as follows: Step1. Open the VHDL file for creation of symbol file, click [File][Create/Update][Create Symbol Files for Current File].

Step2.

Complete creation of symbol file.

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Step3.

To create new Block Diagram File, click [File] [New] to open design method option, in [Device Design Files] select [Block Diagram/Schematic File] to open new block diagram design file.

Step4.

After open the new block diagram file, double click left mouse button in the blank space to open symbol selection window, you can see the created ledtest symbol in [Project].

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Part 3. Pin Assignment

Quartus II provides a few methods to specify pins, one of them is to use menu option [Assignments] [Pins] to individually specify, and the other is to use Tcl script. In this example, well introduce how to specify pins using Tcl script. Step 9. Open Tcl Console located in [View][Utility Windows][Tcl Console].

Step 10. In Tcl Console window type source pin_assign.tcl, then press Enter to finish Pin assignment.

Tcl pin assignment program code and explanation

pin_assign.tcl Program Code
1 2 3 ################################################################## # pin_assign.tcl # 28

4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

# This script allows you to make pin assignments to the Ledtest design # # Written by: Hans.Lin # Rev 1.0 # 2005/04/10 # # You can run this script from Quartus by observing the following steps: # 1. Place this TCL script in your project directory # 2. Open your project # 3. Go to the View Menu and Auxilary Windows -> TCL console # 4. In the TCL console type: # source pin_assign.tcl # 5. The script will assign pins. ################################################################## set_location_assignment PIN_18 -to clk set_location_assignment PIN_23 -to rst set_location_assignment PIN_24 -to u_d set_location_assignment PIN_27 -to sel\[0\] set_location_assignment PIN_28 -to sel\[1\] set_location_assignment PIN_1 -to led\[0\] set_location_assignment PIN_2 -to led\[1\] set_location_assignment PIN_3 -to led\[2\] set_location_assignment PIN_4 -to led\[3\] set_location_assignment PIN_5 -to led\[4\] set_location_assignment PIN_6 -to led\[5\] set_location_assignment PIN_7 -to led\[6\] set_location_assignment PIN_8 -to led\[7\]

pin_assign.tcl Program code explanation Line No. 1~17 18~30 Comments Pin Assignment Explanation

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Part 4. Program Compilation

Step 11. Perform compilation by selecting [Processing][Start Compilation].

Step 12. Complete Compilation

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Part 5. Download Program

Step 13. Open Programmer by selecting [Tools][Programmer]

Step 14. Make sure you have installed Altera Byteblaster, if not, please refer to Install Byteblaster under Windows XP/2000. In Hardware Setup select ByteBlaster[LPT1], please refer to Hardware Setup chapter, if setting differs. Select ledtest.pof to download, tick [Program/Configure], and make sure MAX II Kit is connected to ByteBlaster II download & power cable, lastly click [Start] to complete download action.

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Part 6. Hardware settings and operational instructions

Hardware Interface
JP1

Explanation Putting Jumper on JP1 first set of pins provide system frequency to MAX II Pin 18

SW1: Perform reset function when pressed. SW2 Up/Down counter control button, LED
SW1 SW2 SW3 SW4

illuminating sequence is reversed when switch is pressed. SW3,SW4Allowing for 4 types of marquee to choose from SW3 OFF OFF ON ON SW4 OFF ON OFF ON Marquee LED lit sequentially Continuous flash on & off for all Lit 2 LED in circular sequence The 2 LED lit in Top/Bottom order

Marquee output display to these 8 LED

D1 D2 D3 D4

D5

D6

D7

D8

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Part 7. Hardware Setup

Step 1. [Tools][Programmer]

Step 2. Click [Hardware Setup]

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Step 3. Click [Add Hardware]

Step 4. In Hardware type select ByteBlasterMV or ByteBlaster IIPort type select LPT1, then press [OK]

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Step 5. Click [Close]

Step 6. Complete Hardware Setup

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Chapter 3 Download testing program

This chapter will explain how to test MAX II emulation board to check whether its interface is working correctly. This is done by using Quartus II to compile testing program and pin assignment file, then flash to MAX II. Step 1. Hardware Setting: Connect MAX II emulation board to power source and Download cable, then connect Download cable to computers LPT1 and connect jumper to pin 1&2 of JP1. Step 2. Copy max2_test folder from CD-ROM to your hard disk, then run Quartus II. Step 3. Click [File][New Project Wizard] to open create project wizard windows.

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Step 4. Point the working directory for this project to the max2_test folder, the location where you have placed the folder max2_test on you hard disk in Step 2. Click [Next]

Step 5. Click [Add All] to place max2_test.vhd in the project, then click [Next]

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Step 6. Choose device model, Family: select MAX II; specify device as TQFP package, 144 Pin count, 5 Speed grade, device type is

EPM1270T144C5ES

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Step 7. Click [Next]

Step 8. Click [Finish] to complete new project creation.

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Step 9. Click [View]

[Utility Windows]

[Tcl Console] to set pin assignment.

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Step 10. In Tcl Console window input the following command to complete pin assignment. source pin_assign.tcl

Step 11. Click [Processing]

[Start Compilation]

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Step 12. Finish compilation

Step 13. Click [Tools][Programmer]

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Step 14. In Hardware Setup select ByteBlasterII, choose max2_test.pof download file and tick Program/Configure, press [Start] to begin flash process.

MAX II Emulation board testing program code and explanation

MAX II Emulation Board testing program code
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 -----------------------------------------Name of the exampleMAX2 Starter Kit Test --FunctionDIP ON -> LED ON -7Segment:Clock Function; display minute and second -SW1:reset;SW2:hold function -SW3:turn off minute display;SW4:turn off second display -----------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity max2_test is Port( clk,rst,en: in std_logic; dip : in std_logic_vector(7 downto 0); sw3,sw4 : in std_logic; led : out std_logic_vector(7 downto 0); seven_seg :out std_logic_vector(7 downto 0); dig4,dig3,dig2,dig1:out std_logic); end max2_test; architecture arch of max2_test is signal clk_cnt,clk_scan:std_logic; signal min_ten,min_one,sec_ten,sec_one:std_logic_vector(3 downto 0); signal com_sten,com_sone,com_mten,com_mone:std_logic; signal en_d0,en_d1,en_d2,ce:std_logic; begin led<=dip; dig4<=com_mten when sw3='1' else '0'; dig3<=com_mone when sw3='1' else '0'; dig2<=com_sten when sw4='1' else '0'; dig1<=com_sone when sw4='1' else '0'; 43

36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

clk_div:block signal cnt : std_logic_vector(23 downto 0); signal reset: std_logic; begin process (clk) begin if reset='1' then cnt<=(others=>'0'); elsif clk'event and clk='1' then cnt<=cnt+1; end if; end process; reset<='1' when cnt=16000000 else '0'; clk_cnt<=cnt(23); clk_scan<=cnt(13); end block clk_div; counter:block begin process (clk_cnt,rst,en) begin if rst='0' then min_ten<="0000";min_one<="0000"; sec_ten<="0000";sec_one<="0000"; elsif clk_cnt'event and clk_cnt='1' then if ce='1' then if sec_one="1001" then if sec_ten="0101" then if min_one="1001" then if min_ten="0101" then min_ten<="0000";min_one<="0000"; sec_ten<="0000";sec_one<="0000"; else min_ten<=min_ten+1;min_one<="0000"; sec_ten<="0000";sec_one<="0000"; end if; else min_one<=min_one+1; sec_ten<="0000";sec_one<="0000"; end if; else sec_ten<=sec_ten+1; sec_one<="0000"; end if; else sec_one<=sec_one+1; end if; end if; end if; end process; end block counter; scan:block signal bin: std_logic_vector(3 downto 0); signal sel: integer range 0 to 3; begin process (clk_scan,rst) begin if rst='0' then 44

96 com_sten<='0';com_sone<='0';com_mten<='0';com_mone<='0'; 97 sel<=0; 98 elsif clk_scan'event and clk_scan='1' then 99 sel<=sel+1; 100 case sel is 101 when 0 => 102 bin<=sec_one; 103 com_mten<='0';com_mone<='0';com_sten<='0';com_sone<='1'; 104 when 1 => 105 bin<=sec_ten; 106 com_mten<='0';com_mone<='0';com_sten<='1';com_sone<='0'; 107 when 2 => 108 bin<=min_one; 109 com_mten<='0';com_mone<='1';com_sten<='0';com_sone<='0'; 110 when 3 => 111 bin<=min_ten; 112 com_mten<='1';com_mone<='0';com_sten<='0';com_sone<='0'; 113 when others => 114 null; 115 end case; 116 end if; 117 end process; 118 119 process (bin) 120 begin 121 case bin is 122 when "0000" => seven_seg <= "01000000"; -- 0 123 when "0001" => seven_seg <= "01111001"; -- 1 124 when "0010" => seven_seg <= "00100100"; -- 2 125 when "0011" => seven_seg <= "00110000"; -- 3 126 when "0100" => seven_seg <= "00011001"; -- 4 127 when "0101" => seven_seg <= "00010010"; -- 5 128 when "0110" => seven_seg <= "00000010"; -- 6 129 when "0111" => seven_seg <= "01111000"; -- 7 130 when "1000" => seven_seg <= "00000000"; -- 8 131 when "1001" => seven_seg <= "00010000"; -- 9 132 when others => seven_seg <= "01111111"; 133 end case; 134 end process; 135 end block scan; 136 137 process (clk) 138 begin 139 if clk'event and clk='1' then 140 en_d1<=en_d0;en_d0<=en; 141 if en_d2='1' then 142 ce<=not ce; 143 end if; 144 end if; 145 end process; 146 en_d2<= not en_d0 and en_d1; 147 end arch;

MAX II Emulation board testing program code explanation

45

Line No. 1~7 8~11 13~21 23~28 30 32~33 Comments

Explanation

Component library declaration Input/Output port declaration Internal signal declaration Dip input signal assigned to LED output When SW3 is on high, 7 segment displays Dig3 & Dig4 display normally, when on low, the display is off. When SW4 is on high, 7 segment displays Dig1 & Dig2 display normally, when on low, the display is off. Frequency divider, generate clock count clk_cnt and 7 segment display clock scan clk_scan. Clock counter 7 segment display scan

34~35

37~52

54 ~ 87 89~117

119~135 7 segment display decoding circuit Signal enable transition circuit, in which line 140 is signal enable delay circuit and line 146 is signal enable differential circuit .

137~147

46

Hardware settings and operational instructions

Hardware Interface
JP1

Explanation Putting Jumper on JP1 first set of pins provide system frequency to MAX II Pin 18

Moving switch to ON position, the respective LED light up, when switch is in OFF position, LED light goes out. Controlling LED On/Off through the use of DIP switch Switch used to control 7-segment display status. SW1 reset display, when pressed down, there is no display shown, after releasing the counter start from 0000. SW2 is the hold button, press it once pause the display, press it again the display counter continues. SW3 is Dig3 & Dig4 enabling button, when pressed down, no display shown for Dig3 & Dig4. SW4 is Dig1 & Dig2 enabling button, when pressed down, no display shown for Dig1 & Dig2. Display clocks minute and second function, the two left hand digits show the minute (Dig4, Dig3) and the two right hand digits shows the second (Dig2, Dig1).

47

Chapter 4 ALU example

Function Overview
This example is to create ALU circuit structure allowing for input of two values and performing logical and mathematical calculations, where is function is determined by M, S1 and S0 input value. M sets the circuit to perform either logical or mathematical calculations, when M=0, it performs logical calculation and M=1 mathematical calculation is performed. Further more, S1, S0 determines the calculation mode, there are 4 types of logic and mathematic functions. The available functions are as follows: ALU function table M 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Operation F<=A and B F<=A or B F<=A xor B F<=A nand B F<=A+B F<=A-B F<=A+1 F<=A-1

ALU program code and explanation

ALU program code
1 2 3 4 5 6 7 8 9 10 11 12 13 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity alu is port ( M :in std_logic; S :in std_logic_vector(1 downto 0); A,B:in std_logic_vector(2 downto 0); F :out std_logic_vector(2 downto 0)); end alu; 48

14 architecture a of alu is 15 begin 16 process(S,A,B) 17 begin 18 if M='0' then 19 case S is 20 when "00"=> --"000" 21 F<=A and B; 22 when "01"=> --"001" 23 F<=A or B; 24 when "10"=> --"010" 25 F<=A xor B; 26 when others=> --"011" 27 F<=A nand B; 28 end case; 29 else 30 case S is 31 when "00"=> --"100" 32 F<=A+B; 33 when "01"=> --"101" 34 F<=A-B; 35 when "10"=> --"110" 36 F<=A + "001"; 37 when others=> --"111" 38 F<=A - "001"; 39 end case; 40 end if; 41 end process; 42 end a;

ALU program code explanation Line No. 1~4 6~12 18~28 29~39 Explanation Component library declaration Input/output port declaration Logic calculation Mathematic calculation

49

Hardware settings and operational instructions

Hardware Interface SW1 => M 1=>A(2) ; 2=>A(1) ; 3=>A(0) 4=>B(2) ; 5=>B(1) ; 6=>B(0) 7=> S0 ; 8=>S1 LED1=>F(2) ; LED2=>F(1) ; LED3=>F(0) Note Please note when press down SW, it is at LOW 0. When DIP is switched to the ON position, it is LOW 0. LED lights up with LOW 0. Explanation

50

Chapter 5 7-display segment example

Function Overview
MAX II emulation board uses a 4-in-1 7-segment display component as numerical output interface. Its common point is that it is HIGH driven, they all share the same positive electrode. When a,b,,dp input is LOW, the respective LED lights up. When Digital 1 is connected to HIGH, the right most digit will light up. If Digital 4 is connected to HIGH, the left most digit will light up. Because the same segment of these 4 digits are already connected together, so when Digital 1, Digital 2, Digital 3, Digital 4 are connected to HIGH, the data will simultaneously sent to all 4 digits causing all to be lit. This example use Dip switch Dip5, Dip6, Dip7, Dip8 for binary number entry and use button SW1, SW2, SW3, SW4 as signal control for Digital 4, Digital 3, Digital 2, Digital 1. When SW1 is depressed, Digital 4 is on HIGH and the left most digit light up, the displayed number will depends on position of Dip switch Dip5, Dip6, Dip7, Dip8 in binary format and convert to hexadecimal for output.

ALU Program Code and Explanation

[Seven Segment display program code]
1 2 3 4 5 6 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity seven_seg is 51

7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

port ( sw : in std_logic_vector(4 downto 1); dip : in std_logic_vector(5 to 8); seg_out: out std_logic_vector(7 downto 0); d : out std_logic_vector(1 to 4) ); end seven_seg; architecture arch of seven_seg is begin d<= not sw; process (dip) begin case dip is when "0000" => seg_out <= "01000000"; when "0001" => seg_out <= "01111001"; when "0010" => seg_out <= "00100100"; when "0011" => seg_out <= "00110000"; when "0100" => seg_out <= "00011001"; when "0101" => seg_out <= "00010010"; when "0110" => seg_out <= "00000010"; when "0111" => seg_out <= "01111000"; when "1000" => seg_out <= "00000000"; when "1001" => seg_out <= "00010000"; when "1010" => seg_out <= "00001000"; when "1011" => seg_out <= "00000011"; when "1100" => seg_out <= "01000110"; when "1101" => seg_out <= "00100001"; when "1110" => seg_out <= "00000110"; when "1111" => seg_out <= "00001110"; when others => seg_out <= "11111111"; end case; end process; end arch;

-- 0 -- 1 -- 2 -- 3 -- 4 -- 5 -- 6 -- 7 -- 8 -- 9 -- a -- b -- c -- d -- e -- f

active low '0'

7 Segment display program code explanation Line No. 1~4 6~13 17 Explanation Component library declaration Input/Output port declaration Pop-up button sending reverse signal to 7 segment displays common point. Decode Dip switch binary input to hexadecimal, then output to 7 segment display.

18~39

52

Hardware setting and operating instructions

Hardware Interface Explanation The 4 right hand side Dip switch input number in binary format, Dip5 is the most significant bit, and Dip8 is the least significant bit. Please note, when moving the switch to ON position represents 0 Push button can control 7 segment display status Depress SW1, the left most digit light up Depress SW2, the second digit from the left light up Depress SW3, the third digit from the left light up Depress SW4, the right most digit light up Based on binary input from Dip switch and push buttons common point to display hexadecimal number

53

Chapter 6 Clock example

Function Overview
This example employ frequency divider, 7 segment display scan and state machine to complete a clock example. The MAX II Emulation Board that will be used include the 4 push buttons and 7 segment display. The function of this example is as follows: Able to display minute and second Has reset, start, pause and setup time functions. Can individually set up number to each digit. When SW1 is depressed, time will reset and display 0000 When SW2 is depressed, the display will start counting, ranging from 0 min 0 sec to 59 min 59 sec. When SW3 is depressed, individual digit can be configured, starting from the left most digit and all other digit will display F and retain original value. Each time SW3 is pressed, the next digit can be configured. During configuration condition, press SW4, the number increase by 1 Press SW4 while the clock is running will pause time, you will need to press SW2 again to start counting.

Clock program code and explanation

The diagram below is the clock example block diagram (clock.bdf)

54

[Frequency divider program code]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clk_gen is port( clk_in : in std_logic; clk_out1: out std_logic; clk_out2: out std_logic ); end clk_gen; architecture a of clk_gen is signal cnt : std_logic_vector(23 downto 0); signal reset: std_logic; begin process (clk_in) begin if reset='1' then cnt<=(others=>'0'); elsif clk_in'event and clk_in='1' then cnt<=cnt+1; end if; end process; reset<='1' when cnt=16000000 else '0'; clk_out1<=cnt(23); clk_out2<=cnt(13); end a;

Frequency divider program code explanation Line No. 1~3 5~11 Explanation Component library declaration Input/Output port declaration

55

13~16 19~25 26 27

Internal signal declaration Up counter Clock count pulse 7 segment display clock scan

[Clock control state machine program code]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity clock_sm is port( clk1 : in std_logic; clk2 : in std_logic; rst : in std_logic; sw1 : in std_logic; sw2 : in std_logic; sw3 : in std_logic; sw4 : in std_logic; seg_en : out std_logic; min_ten :out std_logic_vector(3 downto 0); min_one :out std_logic_vector(3 downto 0); sec_ten :out std_logic_vector(3 downto 0); sec_one :out std_logic_vector(3 downto 0) ); end clock_sm; architecture arch of clock_sm is type state_type is (reset,pause,start,set_d1,set_d2,set_d3,set_d4); signal present_state,next_state : state_type; signal cnt_min_one,cnt_min_ten:std_logic_vector(3 downto 0); signal cnt_sec_one,cnt_sec_ten:std_logic_vector(3 downto 0); signal sw3_d0,sw3_d1,sw3_d2: std_logic; signal sw4_d0,sw4_d1,sw4_d2: std_logic; signal clk2_d0,clk2_d1,clk2_d2: std_logic; begin seg_en<='1'; sw3_d2<=sw3_d1 and not sw3_d0; sw4_d2<=sw4_d1 and not sw4_d0; clk2_d2<=not clk2_d1 and clk2_d0; process(present_state) begin case present_state is when reset =>if sw2='0' then next_state<=start; elsif sw3_d2='1' then next_state<=set_d1; else next_state<=reset; end if; when pause =>if sw2='0' then next_state<=start; 56

45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104

elsif sw3_d2='1' then next_state<=set_d1; elsif sw1='0' then next_state<=reset; else next_state<=pause; end if; when start => if sw3_d2='1' then next_state<=set_d1; elsif sw4='0' then next_state<=pause; elsif sw1='0' then next_state<=reset; else next_state<=start; end if; when set_d1 =>if sw2='0' then next_state<=start; elsif sw3_d2='1' then next_state<=set_d2; else next_state<=set_d1; end if; when set_d2 =>if sw2='0' then next_state<=start; elsif sw3_d2='1' then next_state<=set_d3; else next_state<=set_d2; end if; when set_d3 =>if sw2='0' then next_state<=start; elsif sw3_d2='1' then next_state<=set_d4; else next_state<=set_d3; end if; when set_d4 =>if sw2='0' then next_state<=start; elsif sw3_d2='1' then next_state<=set_d1; else next_state<=set_d4; end if; end case; end process; process(clk1,rst) begin if rst='0' then present_state<=reset; elsif clk1'event and clk1='1' then present_state<=next_state; sw3_d1<=sw3_d0;sw3_d0<=sw3; sw4_d1<=sw4_d0;sw4_d0<=sw4; clk2_d1<=clk2_d0;clk2_d0<=clk2; end if; end process; process(clk1) begin if clk1'event and clk1='1' then case present_state is when reset => min_ten<="0000";min_one<="0000"; sec_ten<="0000";sec_one<="0000"; cnt_min_ten<="0000"; cnt_min_one<="0000"; cnt_sec_ten<="0000"; cnt_sec_one<="0000"; when pause => min_ten<=cnt_min_ten;min_one<=cnt_min_one; sec_ten<=cnt_sec_ten;sec_one<=cnt_sec_one; when start => if clk2_d2='1' then if cnt_sec_one="1001" then if cnt_sec_ten="0101" then if cnt_min_one="1001" then if cnt_min_ten="0101" then cnt_min_ten<="0000";cnt_min_one<="0000"; cnt_sec_ten<="0000";cnt_sec_one<="0000"; 57

105 else 106 cnt_min_ten<=cnt_min_ten+1;cnt_min_one<="0000"; 107 cnt_sec_ten<="0000";cnt_sec_one<="0000"; 108 end if; 109 else 110 cnt_min_one<=cnt_min_one+1; 111 cnt_sec_ten<="0000";cnt_sec_one<="0000"; 112 end if; 113 else 114 cnt_sec_ten<=cnt_sec_ten+1; 115 cnt_sec_one<="0000"; 116 end if; 117 else 118 cnt_sec_one<=cnt_sec_one+1; 119 end if; 120 end if; 121 min_ten<=cnt_min_ten;min_one<=cnt_min_one; 122 sec_ten<=cnt_sec_ten;sec_one<=cnt_sec_one; 123 when set_d1=> 124 if sw4_d2='1' then 125 if cnt_min_ten = 5 then cnt_min_ten <= "0000"; 126 else cnt_min_ten <= cnt_min_ten + 1; 127 end if; 128 end if; 129 min_ten<=cnt_min_ten;min_one<="1111"; 130 sec_ten<="1111";sec_one<="1111"; 131 when set_d2=> 132 if sw4_d2='1' then 133 if cnt_min_one = 9 then cnt_min_one <= "0000"; 134 else cnt_min_one <= cnt_min_one + 1; 135 end if; 136 end if; 137 min_ten<="1111";min_one<=cnt_min_one; 138 sec_ten<="1111";sec_one<="1111"; 139 when set_d3=> 140 if sw4_d2='1' then 141 if cnt_sec_ten = 5 then cnt_sec_ten <= "0000"; 142 else cnt_sec_ten <= cnt_sec_ten + 1; 143 end if; 144 end if; 145 min_ten<="1111";min_one<="1111"; 146 sec_ten<=cnt_sec_ten;sec_one<="1111"; 147 when set_d4=> 148 if sw4_d2='1' then 149 if cnt_sec_one = 9 then cnt_sec_one <= "0000"; 150 else cnt_sec_one <= cnt_sec_one + 1; 151 end if; 152 end if; 153 min_ten<="1111";min_one<="1111"; 154 sec_ten<="1111";sec_one<=cnt_sec_one; 155 end case; 156 end if; 157 end process; 158 end arch;

Clock control state machine program code explanation

58

Line No. 1~4 6~21 23~31 32 33~35

Explanation Component library declaration Input/Output port declaration Internal signal declaration Enable 7 segment display scan SW3, SW4, CLK2 derivative circuit, function is to detect changes in input signal Combination logic circuit for clock state machine Sequence logic circuit for clock state machine and SW3,SW4,CLK2 delay circuit Output decoding circuit for clock state machine

37~71 73~83

85~157

[Multi-scan 7 segment display program code]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity bin2seg0_scan is port ( clk_scan : in std_logic; rst : in std_logic; seg_en : in std_logic; min_ten : in std_logic_vector(3 downto 0); min_one : in std_logic_vector(3 downto 0); sec_ten : in std_logic_vector(3 downto 0); sec_one : in std_logic_vector(3 downto 0); seven_seg : out std_logic_vector(7 downto 0); dig1,dig2,dig3,dig4: out std_logic ); end bin2seg0_scan; architecture arch of bin2seg0_scan is signal bin: std_logic_vector(3 downto 0); signal sel: integer range 0 to 3; begin process (clk_scan,rst) begin 59

26 if rst='0' then 27 dig2<='0';dig1<='0';dig4<='0';dig3<='0'; 28 sel<=0; 29 elsif clk_scan'event and clk_scan='1' then 30 sel<=sel+1; 31 case sel is 32 when 0 => 33 bin<=sec_one; 34 dig4<='0';dig3<='0';dig2<='0';dig1<='1'; 35 when 1 => 36 bin<=sec_ten; 37 dig4<='0';dig3<='0';dig2<='1';dig1<='0'; 38 when 2 => 39 bin<=min_one; 40 dig4<='0';dig3<='1';dig2<='0';dig1<='0'; 41 when 3 => 42 bin<=min_ten; 43 dig4<='1';dig3<='0';dig2<='0';dig1<='0'; 44 when others => 45 null; 46 end case; 47 end if; 48 end process; 49 50 process (bin) 51 begin 52 case bin is 53 when "0000" => seven_seg <= "01000000"; 54 when "0001" => seven_seg <= "01111001"; 55 when "0010" => seven_seg <= "00100100"; 56 when "0011" => seven_seg <= "00110000"; 57 when "0100" => seven_seg <= "00011001"; 58 when "0101" => seven_seg <= "00010010"; 59 when "0110" => seven_seg <= "00000010"; 60 when "0111" => seven_seg <= "01111000"; 61 when "1000" => seven_seg <= "00000000"; 62 when "1001" => seven_seg <= "00010000"; 63 when "1111" => seven_seg <= "00001110"; 64 when others => seven_seg <= "11111111"; 65 end case; 66 end process; 67 end arch;

Multi-scan 7 segment display program code explanation Line No. 1~4 6~18 20~23 Explanation Component library declaration Input/Output port declaration Internal signal declaration

60

24~48 50~66

7 segment display common pin scan 7 segment display output decoding circuit

61

Hardware setting and operating instructions

Hardware Interface Explanation Clock function control buttons SW1 resets clock, once pressed, time is reset back to 00 min 00 sec. SW2 start timer, after performing reset function and/or configuration function, youll need to press SW2 again to start clock function. SW3 configure time, individual digit can be configured, starting from the left most digit and all other digit will display F and retain original value. Each time SW3 is pressed, the next digit can be configured. SW4 pause time or increase number by 1, if SW4 is pressed while clock is running, the time pause. When SW4 is pressed during time configuration, the number increase by 1. Will display minute and second according to pop-up button settings.

62

Chapter 7 Traffic signal example

Function Overview
This example emulates a traffic signal with reset and manual control functions. Using SW1 as reset button, Dip switch to control traffic signal behaviour. East/West direction traffics green, yellow and red lights are displayed on LED D1, D2, D3, North/South direction traffic signals are displayed on LED D5, D6,D7. Also while traffic on east/west direction or north/south direct traffic is moving, Digital 4 or Digital 1 of the display will display count down timer. When reset key (SW1) is pressed, the system resets, the east/west direction shows green light (D1), north/south direction shows red light (D7). At the same time the count down timer display time remaining on Digital 4 for east/west direction. When north/south direction shows green light and remaining time displayed on Digital 1. If you wish to manually control east/west direction traffic flow, you can set the Dip switch to 01 (DIP2 ON, DIP1 OFF), then the east/west direction traffic will remain green indefinitely until change in switch setting for lights to change. On the other hand, setting Dip switch to 10 (DIP2 OFF, DIP1 ON) reverse the order, making north/south direction traffic light showing green.

63

Traffic Light

Traffic light program code and explanation

Below is the traffic light block diagram (traffic.bdf) , in it CLK_GEN is the frequency divider circuit, providing counter clock and 7 segment display scan clock. TRAFFIC_SM is the traffic signal control state circuit, BIN2SEG0_SCAN is the 7 segment display scan.

64

Traffic Light Circuit Diagram (traffic.bdf)

Frequency divider program code

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clk_gen is port( clk_in : in std_logic; clk_out1: out std_logic; clk_out2: out std_logic ); end clk_gen; architecture a of clk_gen is signal cnt : std_logic_vector(23 downto 0); signal reset: std_logic; begin process (clk_in) begin if reset='1' then cnt<=(others=>'0'); elsif clk_in'event and clk_in='1' then cnt<=cnt+1; end if; end process; reset<='1' when cnt=16000000 else '0'; clk_out1<=cnt(23); clk_out2<=cnt(13); end a;

Frequency divider program code explanation Line No. 1~3 5~11 13~16 17~25 26 Explanation Component library declaration Input/Output port declaration Internal signal declaration Up Counter Clock counter pulse

65

27

7 segment display scan

Traffic signal control state machine program code

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 library ieee; use ieee.std_logic_1164.all; entity traffic_sm is port ( clk : in std_logic; rst : in std_logic; dip : in std_logic_vector(1 downto 0); red1, yellow1, green1 : out std_logic; red2, yellow2, green2 : out std_logic; time1,time2: out std_logic_vector(3 downto 0) ); end traffic_sm; architecture a of traffic_sm is type state is (s0,s1,s2,s3,s4,s5,s6,s7); signal present_state,next_state : state; begin process (present_state, dip) begin red1 <= '1'; yellow1 <= '1'; green1 <= '1'; red2 <= '1'; yellow2 <= '1'; green2 <= '1'; time1<= "1111"; time2<="1111"; case present_state is when s0 => green1 <= '0'; red2 <= '0'; time1<="0011"; if dip= "01" then next_state <= s0; else next_state <= s1; end if; when s1 => green1 <= '0'; red2 <= '0'; time1<="0010"; next_state <= s2; when s2 => green1 <= '0'; red2 <= '0'; time1<="0001"; next_state <= s3; when s3 => yellow1 <= '0'; red2 <= '0'; time1<="0000"; next_state <= s4; when s4 => red1 <= '0'; green2 <= '0'; time2<="0011"; if dip= "10" then next_state <= s4; else next_state <= s5; end if; when s5 => red1 <= '0'; green2 <= '0'; 66

55 time2<="0010"; 56 next_state <= s6; 57 when s6 => 58 red1 <= '0'; green2 <= '0'; 59 time2<="0001"; 60 next_state <= s7; 61 when s7 => 62 red1 <= '0'; yellow2 <= '0'; 63 time2<="0000"; 64 next_state <= s0; 65 end case; 66 end process; 67 68 process(rst,clk) 69 begin 70 if (rst='0') then 71 present_state <= s0; 72 elsif clk'event and clk='1' then 73 present_state <= next_state ; 74 end if ; 75 end process; 76 end a;

Traffic signal control state machine program code explanation Line No. 1~2 4~13 15~18 19~66 68~75 Explanation Component library declaration Input/Output port declaration Internal signal declaration Combination logic circuit for traffic signal state machine Sequence logic circuit for traffic signal state machine

7 segment display scan program code

1 2 3 4 5 6 7 8 9 10 11 12 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity bin2seg0_scan is port ( clk_scan : in rst : in seg_en : in min_ten : in min_one : in

std_logic; std_logic; std_logic; std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); 67

13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

sec_ten : in std_logic_vector(3 downto 0); sec_one : in std_logic_vector(3 downto 0); seven_seg : out std_logic_vector(7 downto 0); dig1,dig2,dig3,dig4: out std_logic ); end bin2seg0_scan; architecture arch of bin2seg0_scan is signal bin: std_logic_vector(3 downto 0); signal sel: integer range 0 to 3; begin process (clk_scan,rst) begin if rst='0' then dig2<='0';dig1<='0';dig4<='0';dig3<='0'; sel<=0; elsif clk_scan'event and clk_scan='1' then sel<=sel+1; case sel is when 0 => bin<=sec_one; dig4<='0';dig3<='0';dig2<='0';dig1<='1'; when 1 => bin<=sec_ten; dig4<='0';dig3<='0';dig2<='1';dig1<='0'; when 2 => bin<=min_one; dig4<='0';dig3<='1';dig2<='0';dig1<='0'; when 3 => bin<=min_ten; dig4<='1';dig3<='0';dig2<='0';dig1<='0'; when others => null; end case; end if; end process; process (bin) begin case bin is when "0000" => seven_seg <= "01000000"; when "0001" => seven_seg <= "01111001"; when "0010" => seven_seg <= "00100100"; when "0011" => seven_seg <= "00110000"; when "0100" => seven_seg <= "00011001"; when "0101" => seven_seg <= "00010010"; when "0110" => seven_seg <= "00000010"; when "0111" => seven_seg <= "01111000"; when "1000" => seven_seg <= "00000000"; when "1001" => seven_seg <= "00010000"; when others => seven_seg <= "11111111"; end case; end process; end arch;

7 segment display scan program code explanation

68

Line No. 1~4 6~18 20~23 24~48 50~65

Explanation Component library declaration Input/Output port declaration Internal signal declaration 7 segment display common point scan 7 segment display numerical output decoder circuit

69

Hardware setting and operating instructions

Hardware Interface
JP1

Explanation Putting Jumper on JP1 first set of pins provide system frequency to MAX II Pin 18

SW1 is the reset button Control switch (DIP2,DIP1) DIP1OFF, DIP2ON: maintain east/west traffic flow, D1 (green light for east/west) & D7 (red light for north/south) lit. DIP1ON, DIP2OFF: maintain north/south traffic flow, D3 (red light for east/west) & D5 (green light for north/south) lit. DIP1OFF, DIP2OFF or DIP1ON, DIP2ON: traffic light changes with pre-determined change over time, east/west direction will display count down time on Digital 4 and north/south direction will display count down time on Digital 1. East/west direction green/yellow/red traffic light. (D1,D2,D3) North/south direction green/yellow/red traffic light. (D5,D6,D7) Display green light time remaining Digital 4 shows east/west direction green light time remaining. Digital 1 shows north/south direction green light time remaining.

70

Chapter 8 Gaming machine example

Function Overview
This example is a gaming machine allowing two people to play a game of large or small. Using SW1 as reset button, SW2 as player1s decision button, SW3 as player 2s decision button. The games sequence is as follows: Step 1. Dip1 determine which side has the larger number wins. If Dip1 is OFF, then its when player 1s number is larger than player 2. If Dip 1 is ON, then its when player 2s number greater than player 1. Winning is determined by all LED light up, when theres no winning, all the LEDs do not light up. Step 2. Press SW1 to reset the gaming machine, then LED will flash in circular sequence. Step 3. Player 1 press SW2, the left hand side of the display will display randomly generated number Step 4. Player 2 press SW3, the right hand side of the display will display randomly generated number. Step 5. Step 1 defines the winning requirement, repeat step 2~4 to start new game.

Gaming machine program code and explanation

Below is the gaming machine block diagram (game.bdf), in it CLK_DIV module is the frequency divider, providing counter clock and display clock scan, GAME_SM is the gaming machine control state circuit, BIN2SEG0_SCAN is the 7 segment display scan, LED module is the LED display circuit.

71

Gaming machine block diagram(game.bdf) Frequency divider program code

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clk_div is port( clk_in : in std_logic; clk_out1: out std_logic; clk_out2: out std_logic ); end clk_div; architecture a of clk_div is signal cnt : std_logic_vector(23 downto 0); signal reset: std_logic; begin process (clk_in) begin if reset='1' then cnt<=(others=>'0'); elsif clk_in'event and clk_in='1' then cnt<=cnt+1; end if; end process; reset<='1' when cnt=16000000 else '0'; clk_out1<=cnt(19); clk_out2<=cnt(14); end a;

Frequency divider program code explanation Line No. 1~3 Explanation Component library declaration

72

5~11 13~16 17~25 26 27

Input/Output port declaration Internal signal declaration Up counter LED counter clock 7 segment display scan with random generator clock.

Gaming machine control state machine program code

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity game_sm is port( clk : in std_logic; rst : in std_logic; sw2,sw3 : in std_logic; dip1 : in std_logic; min_ten : out std_logic_vector(3 downto 0); min_one : out std_logic_vector(3 downto 0); sec_ten : out std_logic_vector(3 downto 0); sec_one : out std_logic_vector(3 downto 0); led_sel : out std_logic_vector(1 downto 0) ); end game_sm; architecture a of game_sm is type state_type is (S0,S1,S2); signal present_state,next_state : state_type; signal cnta1,cnta2,cntb1,cntb2 : std_logic_vector(3 downto 0); signal randoma,randomb:std_logic; begin min_ten<=cnta2;min_one<=cnta1; sec_ten<=cntb2;sec_one<=cntb1; process(present_state,rst,sw2,sw3,dip1) begin case present_state is when S0 => randoma<='1';randomb<='1'; led_sel<="01"; if sw2='0' then next_state<=S1; else next_state<=S0; end if; 73

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

when S1 => randoma<='0';randomb<='1'; led_sel<="01"; if sw3='0' then next_state<=S2; else next_state<=S1; end if; when S2 => randoma<='0';randomb<='0'; if rst='0' then next_state<=S0; else next_state<=S2; end if; if dip1='1' then if cnta2>cntb2 then led_sel<="10"; elsif cnta2=cntb2 and cnta1>cntb1 then led_sel<="10"; else led_sel<="00"; end if; else if cntb2>cnta2 then led_sel<="10"; elsif cntb2=cnta2 and cntb1>cnta1 then led_sel<="10"; else led_sel<="00"; end if; end if; end case; end process; process(clk,rst) begin if rst='0' then present_state<=S0; elsif clk'event and clk='1' then present_state<=next_state; end if; end process; process(clk,randoma) begin if clk'event and clk='1' then if randoma='1' then if cnta2 = "1001" then if cnta1 = "1001" then cnta1 <= "0000"; cnta2 <= "0000"; else cnta1 <= cnta1 + 1; end if; elsif cnta1 = "1001" then cnta1 <= "0000"; cnta2 <= cnta2 + 1; else cnta1 <= cnta1 + 1; 74

100 end if; 101 end if; 102 end if; 103 end process; 104 105 process(clk,randomb) 106 begin 107 if clk'event and clk='1' then 108 if randomb='1' then 109 if cntb2 = "1001" then 110 if cntb1 = "1001" then 111 cntb1 <= "0000"; 112 cntb2 <= "0000"; 113 else 114 cntb1 <= cntb1 + 1; 115 end if; 116 elsif cntb1 = "1001" then 117 cntb1 <= "0000"; 118 cntb2 <= cntb2 + 1; 119 else 120 cntb1 <= cntb1 + 1; 121 end if; 122 end if; 123 end if; 124 end process; 125 end a;

Gaming machine control state machine program code explanation Line No. 1~4 6~18 20~25 26~27 29~73 75~82 84~124 Explanation Component library declaration Input/Output port declaration Internal signal declaration 4 display number output Combination logic circuit for gaming machine state Sequence logic circuit for gaming machine state Gaming machine counter

7 segment display scan program code

75

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity bin2seg0_scan is port ( clk_scan : in std_logic; rst : in std_logic; min_ten : in std_logic_vector(3 downto 0); min_one : in std_logic_vector(3 downto 0); sec_ten : in std_logic_vector(3 downto 0); sec_one : in std_logic_vector(3 downto 0); seven_seg : out std_logic_vector(7 downto 0); dig1,dig2,dig3,dig4: out std_logic ); end bin2seg0_scan; architecture arch of bin2seg0_scan is signal bin: std_logic_vector(3 downto 0); signal sel: integer range 0 to 3; begin process (clk_scan,rst) begin if rst='0' then dig2<='0';dig1<='0';dig4<='0';dig3<='0'; sel<=0; elsif clk_scan'event and clk_scan='1' then sel<=sel+1; case sel is when 0 => bin<=sec_one; dig4<='0';dig3<='0';dig2<='0';dig1<='1'; when 1 => bin<=sec_ten; dig4<='0';dig3<='0';dig2<='1';dig1<='0'; when 2 => bin<=min_one; dig4<='0';dig3<='1';dig2<='0';dig1<='0'; when 3 => bin<=min_ten; dig4<='1';dig3<='0';dig2<='0';dig1<='0'; when others => null; end case; end if; end process; process (bin) begin case bin is when "0000" => seven_seg <= "01000000"; when "0001" => seven_seg <= "01111001"; when "0010" => seven_seg <= "00100100"; when "0011" => seven_seg <= "00110000"; when "0100" => seven_seg <= "00011001"; when "0101" => seven_seg <= "00010010"; when "0110" => seven_seg <= "00000010"; when "0111" => seven_seg <= "01111000"; when "1000" => seven_seg <= "00000000"; 76

61 when "1001" => seven_seg <= "00010000"; 62 when "1111" => seven_seg <= "00001110"; 63 when others => seven_seg <= "11111111"; 64 end case; 65 end process; 66 end arch;

7 segment display scan program code explanation Line No. 1~4 6~17 19~22 23~47 49~65 Explanation Component library declaration Input/Output port declaration Internal signal declaration 7 segment display common point scan 7 segment display numerical output decoder circuit

LED display circuit program code

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity led is port( clk :in std_logic; rst :in std_logic; sel :in std_logic_vector(1 downto 0); led :out std_logic_vector(7 downto 0) ); end led; architecture a of led is signal cnt : std_logic_vector(2 downto 0); signal led_t1,led_t2:std_logic_vector(7 downto 0); begin process(clk,rst) begin if rst='0' then cnt<="000"; elsif clk'event and clk='1' then cnt<=cnt+1; 77

26 end if; 27 end process; 28 29 led_t1<="11111110" when cnt="000" else 30 "11111101" when cnt="001" else 31 "11111011" when cnt="010" else 32 "11110111" when cnt="011" else 33 "01111111" when cnt="100" else 34 "10111111" when cnt="101" else 35 "11011111" when cnt="110" else 36 "11101111"; 37 led_t2<="00000000" when cnt="000" else 38 "11111111" when cnt="001" else 39 "00000000" when cnt="010" else 40 "11111111" when cnt="011" else 41 "00000000" when cnt="100" else 42 "11111111" when cnt="101" else 43 "00000000" when cnt="110" else 44 "11111111"; 45 46 led <= led_t1 when sel="01" else 47 led_t2 when sel="10" else 48 "11111111"; 49 end a;

LED Display circuit program code explanation Line No. 1~4 6~13 15~18 20~27 29~44 46~48 Explanation Component library declaration Input/Output port declaration Internal signal declaration Up counter LED decoder circuit LED multi-output circuit

Hardware setting and operating instructions

Hardware Interface
78

Explanation

JP1

Putting Jumper on JP1 first set of pins provide system frequency to MAX II Pin 18

SW1 is the reset button SW2 is player 1s selection button SW3 is player 2s selection button DIP1 sets which player has the larger number wins, if DIP1 OFF, then when player 1s number is larger than player 2 wins, on the other hand if DIP1 ON, then its player 2s number larger than player 1 wins. After reset, the LED will flash in sequential circular motion. When the preset side wins, the all the LEDs flash simultaneously. When theres no winning, LEDs do not flash. Player 1s number

Player 2s number

79

Chapter 9

RS-232 Example

Function Overview
This example test UART serial transfer and receive function, via the use of Comm. Port on the computer to send serial data to MAX II emulation board. The first time data is transferred to MAX II emulation board, the received data will be displayed on Digital 1 and Digital 2 of the display, as well as stored in the internal temporary buffer. When there are new data sent to MAX II, the previous set of data will be shifted to Digital 3 and Digital 4, the new data displayed on Digital 1 and Digital 2, and the internal temporary buffer location updated accordingly. In addition, data contained in MAX II internal temporary buffer can be retrieved via Comm. Port and displayed on computer screen. Below is testing procedure: Step 1. Connect MAX II with PC using 9 pin RS-232 Cable Step 2. Flash uart.pof file to MAX II emulation board Step 3. Run MAX II RS-232.exe application, the appearance is as follows.

Step 4. Setting COM Port number and Baud rate in the application, click [OK] when
80

done. User need to verify COM Port on the computer and set the respective baud rate on MAX II emulation board using Dip switches DIP1, DIP2, DIP3. Step 5. In TX Data input 1 character, then press [Transmit] Step 6. Immediately following step 6, the display on MAX II emulation board will display ASCII code of the transmitted character. Step 7. Press SW2 on MAX II to return the ASCII code received by UART back to the computer. Step 8. Click [Receive] Step 9. In the receiving text box will display the character representing the ASCII Code. Below is MAXIIs UART functional specification

Signal Pin CLK RST_N SEL[2:0] RXD TXD_STARTH TXD GCLK0P

I/O Position P18

Function Explained

SW1 DIP3,DIP2,DIP1 RS-232_RXD SW2 RS-232_TXD

81

System operating frequency P23 System reset signal P16,P21,P22 Baud rate selection P49 RS-232 receiving signal P24 Transmit button P45 RS-232Transmit signal

SEVEN_SEG[7..0] DIG4 DIG3 DIG2 DIG1

SEGMENT[DIP~A] COMMON4 COMMON3 COMMON2 COMMON1

P44~37 P32 P31 P30 P29

7 segment display signal Digital 4 common pin Digital 3 common pin Digital 2 common pin Digital 1 common pin

Baud rate generator program code

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity br_gen is generic(divisor: integer := 26); port( sysclk:in std_logic; sel :in std_logic_vector(2 downto 0); bclkx8:buffer std_logic; bclk :out std_logic ); end br_gen; architecture arch of br_gen is signal cnt2,clkdiv: std_logic; signal ctr2: std_logic_vector (7 downto 0):= "00000000"; signal ctr3: std_logic_vector (2 downto 0):= "000"; begin process (sysclk) variable cnt1 : integer range 0 to divisor; variable divisor2 : integer range 0 to divisor; begin divisor2 := divisor/2; if (sysclk'event and sysclk='1') then if cnt1=divisor then cnt1 := 1; else cnt1 := cnt1 + 1; end if; end if; if (sysclk'event and sysclk='1') then if (( cnt1=divisor2) or (cnt1=divisor)) then cnt2 <= not cnt2; end if; end if; end process; clkdiv<= cnt2 ; process (clkdiv) begin if(rising_edge(clkdiv)) then ctr2 <= ctr2+1; end if; end process; bclkx8<=ctr2(CONV_INTEGER(sel)); process (bclkx8) begin if(rising_edge(bclkx8)) then ctr3 <= ctr3+1; 82

50 end if; 51 end process; 52 bclk <= ctr3(2); 53 end arch;

Baud rate generator program code explanation Line No. 1~3 5~13 15~19 20~38 39~44 45 46~52 Explanation Component library declaration Input/Output port declaration Internal signal declaration Frequency divider (clkdiv = sysclk / divisor) 8 bit up counter Miltitasker; generate 8 time baud rate Frequency divider (bclk = bclkx8 / 8)

[RS-232 receiver program code]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity uart_receiver is port( sysclk :in std_logic; rst_n :in std_logic; bclkx8 :in std_logic; rxd :in std_logic; rxd_readyH:out std_logic; RDR :out std_logic_vector(7 downto 0) ); end uart_receiver; architecture arch of uart_receiver is type statetype is (idle,start_detected,recv_data); 83

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

signal state,nextstate:statetype; signal inc1,inc2,clr1,clr2:std_logic; signal shftRSR,load_RDR:std_logic; signal bclkx8_dlayed,bclkx8_rising:std_logic; signal RSR:std_logic_vector(7 downto 0); signal ct1:integer range 0 to 7; signal ct2:integer range 0 to 8; signal ok_en: std_logic; begin bclkx8_rising<=bclkx8 and(not bclkx8_dlayed); process(state,rxd,ct1,ct2,bclkx8_rising) begin inc1<='0';inc2<='0';clr1<='0';clr2<='0'; shftRSR<='0';load_RDR<='0';ok_en<='0'; case state is when idle=> if (rxd='0') then nextstate<=start_detected; else nextstate<=idle; end if; when start_detected=> if (bclkx8_rising='0') then nextstate<=start_detected; elsif (rxd='1') then clr1<='1'; nextstate<=idle; elsif (ct1=3) then clr1<='1'; nextstate<=recv_data; else inc1<='1'; nextstate<=start_detected; end if; when recv_data=> if (bclkx8_rising='0') then nextstate<=recv_data; else inc1<='1'; if (ct1/=7) then nextstate<=recv_data; elsif (ct2/=8) then shftRSR<='1'; inc2<='1'; clr1<='1'; nextstate<=recv_data; elsif (rxd='0') then nextstate<=idle; clr1<='1'; clr2<='1'; else load_RDR<='1'; ok_en<='1'; clr1<='1'; clr2<='1'; nextstate<=idle; end if; end if; end case; end process; 84

79 process(sysclk,rst_n) 80 begin 81 if (rst_n='0') then 82 state<=idle; 83 bclkx8_dlayed<='0'; 84 ct1<=0; 85 ct2<=0; 86 RDR<="00101011"; 87 elsif (sysclk'event and sysclk='1') then 88 state<=nextstate; 89 90 if(clr1='1')then ct1<=0;elsif(inc1='1')then ct1<=ct1+1;end if; 91 92 if(clr2='1')then ct2<=0;elsif(inc2='1')then ct2<=ct2+1;end if; 93 94 if(shftRSR='1')then RSR<=rxd & RSR(7 downto 1);end if; 95 96 if(load_RDR='1')then RDR<=RSR;end if; 97 98 if(ok_en='1')then rxd_readyH<='1';else rxd_readyH<='0';end if; 99 bclkx8_dlayed<=bclkx8; 100 end if; 101 end process; 102 end arch;

RS-232 receiver program code explanation Line No. 1~4 6~15 17~27 28 Explanation Component library declaration Input/Output port declaration Internal signal declaration bclkx8 upper derivation, detect whether theres upper signal for bclkx8 Serial transfer receiver state machine Serial transfer receiver state and signal update

29~78 79~101

[RS-232 transmitter program code]

1 2 3 library ieee; use ieee.std_logic_1164.all;

85

4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

entity uart_transmitter is port( sysclk : in std_logic; rst_n : in std_logic; bclk : in std_logic; txd_startH : in std_logic; DBUS : in std_logic_vector(7 downto 0); txd_doneH : out std_logic; txd : out std_logic ); end uart_transmitter; architecture arch of uart_transmitter is type statetype is (idle, synch, tdata); signal state, nextstate : statetype; signal tsr : std_logic_vector (8 downto 0); signal bct: integer range 0 to 9; signal inc, clr, loadTSR, shftTSR, start: std_logic; signal bclk_rising, bclk_dlayed, txd_done: std_logic; signal txd_startH_d0,txd_startH_d1,txd_startH_d2:std_logic; begin txd <= tsr(0); txd_doneH <= txd_done; bclk_rising <= bclk and (not bclk_dlayed); txd_startH_d2<=not txd_startH_d0 and txd_startH_d1; process(state,txd_startH_d2, bct, bclk_rising) begin inc <= '0'; clr <= '0'; loadTSR <= '0'; shftTSR <= '0'; start <= '0'; txd_done <= '0'; case state is when idle => if (txd_startH_d2 = '1' ) then loadTSR <= '1'; nextstate <= synch; else nextstate <= idle; end if; when synch => if (bclk_rising = '1') then start <= '1'; nextstate <= tdata; else nextstate <= synch; end if; when tdata => if (bclk_rising = '0') then nextstate <= tdata; elsif (bct /= 9) then shfttsr <= '1'; inc <= '1'; nextstate <= tdata; else clr <= '1'; txd_done <= '1'; nextstate <= idle; end if; 86

64 end case; 65 end process; 66 process (sysclk, rst_n) 67 begin 68 if (rst_n = '0') then 69 TSR <= "111111111"; 70 state <= idle; 71 bct <= 0; 72 bclk_dlayed <= '0'; 73 elsif (sysclk'event and sysclk = '1') then 74 state <= nextstate; 75 txd_startH_d0<=txd_startH;txd_startH_d1<=txd_startH_d0; 76 if (clr = '1') then 77 bct <= 0; 78 elsif (inc = '1') then 79 bct <= bct + 1; 80 end if; 81 if (loadTSR = '1') then 82 TSR <= DBUS & '1'; 83 elsif (start = '1') then 84 TSR(0) <= '0'; 85 elsif (shftTSR = '1') then 86 TSR <= '1' & TSR(8 downto 1); 87 end if; 88 bclk_dlayed <= bclk; 89 end if; 90 end process; 91 end arch;

RS-232 transmitter program code explanation Line No. 1~2 4~14 16~24 25 27 28 29~65 Explanation Component library declaration Input/Output port declaration Internal signal declaration Send TSR LOW to txd Data transfer complete signal Bclk positive derivation Serial transfer transmitter state machine

87

66~90

Serial transfer transmitter state and signal update

[RS-232 module program code]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity uart is port( clk : in std_logic; rst_n : in std_logic; sel : in std_logic_vector(2 downto 0); rxd : in std_logic; rxd_readyH: out std_logic; rxd_data : out std_logic_vector(7 downto 0); txd_startH: in std_logic; DBUS : in std_logic_vector(7 downto 0); txd_doneH : out std_logic; txd : out std_logic ); end uart; architecture a of uart is component br_gen generic(divisor: integer := 3); port( sysclk:in std_logic; sel :in std_logic_vector(2 downto 0); bclkX8:buffer std_logic; bclk :out std_logic ); end component; component uart_receiver port( sysclk :in std_logic; rst_n :in std_logic; bclkx8 :in std_logic; rxd :in std_logic; rxd_readyH:out std_logic; RDR :out std_logic_vector(7 downto 0) ); end component; component uart_transmitter port( sysclk : in std_logic; rst_n : in std_logic; bclk : in std_logic; txd_startH : in std_logic; DBUS : in std_logic_vector(7 downto 0); txd_doneH : out std_logic; txd : out std_logic ); end component; 88

54 signal bclkx8,bclk: std_logic; 55 begin 56 u1: br_gen generic map(26) 57 port map(clk,sel,bclkx8,bclk); 58 u2:uart_receiver 59 port map(clk,rst_n,bclkx8,rxd,rxd_readyH,rxd_data); 60 u3: uart_transmitter 61 port map(clk,rst_n,bclk,txd_startH,DBUS,txd_doneH,txd); 62 end a;

RS-232 module program code explanation Line No. 1~4 6~19 21~55 56~61 Explanation Component library declaration Input/Output port declaration Internal signal declaration Module connection

Frequency divider program code

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clk_div is port( clk_in : in std_logic; clk_out1: out std_logic ); end clk_div; architecture a of clk_div is signal cnt : std_logic_vector(23 downto 0); signal reset: std_logic; begin process (clk_in) begin if reset='1' then cnt<=(others=>'0'); elsif clk_in'event and clk_in='1' then cnt<=cnt+1; end if; end process; reset<='1' when cnt=16000000 else '0'; clk_out1<=cnt(13); end a; 89

Frequency divider program code explanation Line No. 1~3 5~10 12~15 16~24 25 Explanation Component library declaration Input/Output port declaration Internal signal declaration Up counter Clock scan

7 segment display scan program code

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity scan is port ( clk,clk_scan,rst : in std_logic; rxd_readyH : in std_logic; rxd_data : in std_logic_vector(7 downto 0); seven_seg : out std_logic_vector(7 downto 0); com_mten,com_mone: out std_logic; com_sten,com_sone: out std_logic); end scan; architecture arch of scan is signal bin: std_logic_vector(3 downto 0); signal sel: integer range 0 to 3; signal min_ten,min_one: std_logic_vector(3 downto 0); signal sec_ten,sec_one: std_logic_vector(3 downto 0); begin process (clk,rxd_readyH) begin if rst='0' then sec_one<=rxd_data(3 downto 0); sec_ten<=rxd_data(7 downto 4); min_one<="0000"; min_ten<="0000"; elsif clk'event and clk='1' then if rxd_readyH='1' then sec_one<=rxd_data(3 downto 0); 90

33 sec_ten<=rxd_data(7 downto 4); 34 min_one<=sec_one; 35 min_ten<=sec_ten; 36 end if; 37 end if; 38 end process; 39 40 process (clk_scan,rst) 41 begin 42 if rst='0' then 43 com_sten<='0';com_sone<='0';com_mten<='0';com_mone<='0'; 44 sel<=0; 45 elsif clk_scan'event and clk_scan='1' then 46 sel<=sel+1; 47 case sel is 48 when 0 => 49 bin<=sec_one; 50 com_mten<='0';com_mone<='0';com_sten<='0';com_sone<='1'; 51 when 1 => 52 bin<=sec_ten; 53 com_mten<='0';com_mone<='0';com_sten<='1';com_sone<='0'; 54 when 2 => 55 bin<=min_one; 56 com_mten<='0';com_mone<='1';com_sten<='0';com_sone<='0'; 57 when 3 => 58 bin<=min_ten; 59 com_mten<='1';com_mone<='0';com_sten<='0';com_sone<='0'; 60 when others => 61 null; 62 end case; 63 end if; 64 end process; 65 66 process (bin) 67 begin 68 case bin is 69 when "0000" => seven_seg <= "01000000"; -- 0 70 when "0001" => seven_seg <= "01111001"; -- 1 71 when "0010" => seven_seg <= "00100100"; -- 2 72 when "0011" => seven_seg <= "00110000"; -- 3 73 when "0100" => seven_seg <= "00011001"; -- 4 74 when "0101" => seven_seg <= "00010010"; -- 5 75 when "0110" => seven_seg <= "00000010"; -- 6 76 when "0111" => seven_seg <= "01111000"; -- 7 77 when "1000" => seven_seg <= "00000000"; -- 8 78 when "1001" => seven_seg <= "00010000"; -- 9 79 when "1010" => seven_seg <= "00001000"; -- a 80 when "1011" => seven_seg <= "00000011"; -- b 81 when "1100" => seven_seg <= "01000110"; -- c 82 when "1101" => seven_seg <= "00100001"; -- d 83 when "1110" => seven_seg <= "00000110"; -- e 84 when "1111" => seven_seg <= "00001110"; -- f 85 when others => seven_seg <= "01111111"; 86 end case; 87 end process; 88 end arch;

7 segment display scan program code explanation

91

Line No. 1~4 6~14 16~21 23~38 40~64 66~88

Explanation Component library declaration Input/Output port declaration Internal signal declaration 4 display number update 7 segment display common point scan 7 segment display numerical output decoder circuit

Hardware setting and operating instructions

Hardware Interface
JP1

Explanation Putting Jumper on JP1 first set of pins provide system frequency to MAX II Pin 18

SW1 is the reset button SW2 sends the received data back to computer Baud rate selection switch DIP1,DIP2,DIP3 Baud rate selection chart Selection Signal DIP3,DIP2,DIP1 Baud rate 0 0 0 0 1 0 0 1 1 0
92

0 1 0 1 0

38400 19200 9600 4800 2400

1 1 1

0 1 1

1 0 1

1200 600 300

The ASCII code received from computer

Data sent back to computer

ASCII reference table

ASCII (HEX) 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f Text SPACE ! " # $ % & ' ( ) * + , . / ASCII (HEX) 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f Text 0 1 2 3 4 5 6 7 8 9 : ; < = > ? ASCII (HEX) 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f Text @ A B C D E F G H I J K L M N O ASCII (HEX) 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f Text P Q R S T U V W X Y Z [ \ ] ^ _ ASCII (HEX) 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f Text ASCII (HEX) 70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f Text p q r s t u v w x y z { | } ~ DEL

`
a b c d e f g h i j k l m n o

93

Appendix A
Step 1. Click [Next]

QuartusII 4.2 installation procedure

Step 2. Click [I accept the terms of the license agreement], then click [Next]

94

Step 3. Fill in User Name and Company Name, click [Next]

Step 4. Specify Quartus42 Installation path, then click [Next]

95

Step 5. Specify Qdesigns42 Installation path, click [Next]

Step 6. Select Complete, the click [Next]

96

Step 7. Specify program folder, click [Next]

Step 8. Complete setting, click [Next]

97

Step 9. Start installation process

Step 10. Click [Finish] to complete installation.

98

Appendix B

License application procedure

Step 1. Connect to Altera website http://www.altera.com, click on [Licensing]

Step 2. click Quartus II Web Edition Software

99

Step 3. Fill in personal details, then click[Submit Request]

Step 4. Go to [Start][Run] and enter cmd, ipconfig all, to record computers network card MAC address (Physical Address)

100

Step 5. Enter computers 12 digit MAC address, click [Continue]

Step 6. Complete the survey form, then click [Continue]

101

Step 7. Complete License application procedure

Step 8. Check your e-mail box for License file and save it to your computer.

102

Step 9. Click [Tools][License Setup]

Step 10. Specify path where the License file was stored.

103

Appendix C Install Byteblaster in Windows XP/2000

Byteblaster is a standard parallel port interface, a separate driver will need to be installed under Windows 2000 & XP system in order to use LPT1 for emulation board chip flashing.

Adding new hardware in Windows XP

Step 1. [Start][Settings][Control Panel][Printer and other hardware][Add hardware], add new hardware wizard appears, click [Next]

104

Step 2. Choose [Yes, I have already connected the hardware][Next]

Step 3. In adding new hardware wizard window select [Add a new hardware device] [Next]

105

Step 4. Select [Install the hardware that I manually from the list (advanced)][Next]

Step 5. Select [Sound, video and game controllers][Next]

106

[Have disk..][Next]

Step 6. Click [Browse] to choose location of the folder or the driver

107

Step 7. Move to \quartus50\drivers\win2000 Win2000.inffile, select [Open][Ok]

directory

to

look

for

Step 8. Click on [Continue Anyway]

108

Step 9. Select the device driver to install for this hardware: [Altera ByteBlaster] [Next]

Step 10. Click [Next] to start installation of new hardware

109

Step 11. Select [Continue Anyway]

Step 12. Click [Finish] to close adding new hardware wizard.

110

Step 13. Go to [My Computer], right mouse click and select [Properties], System information window appears, select [Device Manager] under [Hardware].

Appendix D MAX II Starter Kit Schematic

111

+3.3V +3.3V PIN[112:1] VCC GND GND PIN98 VCC PIN97 PIN96 PIN95 PIN94 PIN93 PIN92 PIN91 PIN90 PIN89 VCC GND PIN88 PIN87 PIN86 PIN85 PIN84 PIN83 MIC5209-3.3BS U2 PIN[112:1]

Vin GND Vout GND

J5

A
G_LED POWER

PIN112 PIN111 PIN110 PIN109 PIN108 PIN107 PIN106 PIN105

PIN104 PIN103 PIN102 PIN101 PIN100 PIN99

POWER_JACK J6 +3.3V

1 2 3 4

3 2 1

144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109

R1 300

IO109 IO108 IO107 IO106 IO105 IO104 IO103 IO102 VCCIO2(1)1 GNDIO7 IO101 IO100 IO99 IO98 IO97 IO96 GNDINT3 IO95 VCCINT(3.3V or 2.5V)3 IO94 IO93 IO92 IO91 IO90 IO89 IO88 IO87 IO86 VCCIO2(1) GNDIO6 IO85 IO84 IO83 IO82 IO81 IO80

1 2
DC5VIN

+3.3V

C3 0.1u

C4 0.1u

C2 22u

+3.3V VCC GND

VCC GND PIN74 PIN73 PIN72 PIN71 PIN70 PIN69 GND GCLK3 VCC GCLK2 PIN68 PIN67 PIN66 PIN65 PIN64 GND VCC PIN63 PIN62 PIN61 PIN60 PIN59 PIN58 PIN57 PIN56 PIN55 C10 +3.3V TDI

4 3 2 1

PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 PIN8

GND VCC

VCC GND

IO24 IO25 IO26 IO27 IO28 IO29 IO30 IO31 IO32 VCCIO4(1) GNDIO2 IO33 IO34 IO35 IO36 IO37 IO38 GNDINT1 IO39 VCCINT(3.3V or 2.5V)1 IO40 IO41 IO42 IO/DEV_OE IO/DEV_CLRn IO43 IO44 VCCIO4(1)1 GNDIO3 IO45 IO46 IO47 IO48 IO49 RS232 IO50 IO51

1 2 3 4 5 6 7 8 9 10 PIN9 11 PIN10 12 PIN11 13 PIN12 14 PIN13 15 PIN14 16 17 GCLK0 18 19 GCLK1 20 PIN15 21 PIN16 22 PIN17 23 PIN18 24 25 26 PIN19 27 PIN20 28 PIN21 29 PIN22 30 PIN23 31 PIN24 32 TMS 33 TDI 34 TCK 35 TDO 36

IO IO1 IO2 IO3 IO4 IO5 IO6 IO7 VCCIO1(1) GNDIO IO8 IO9 IO10 IO11 IO12 IO13 GNDINT IO/GCLK0 VCCINT(3.3V or 2.5V) IO/GCLK1 IO14 IO15 IO16 IO17 VCCIO1(1)1 GNDIO1 IO18 IO19 IO20 IO21 IO22 IO23 TMS TDI TCK TDO

U1

EPM1270-TQFP144

DIG SEL

IO79 IO78 IO77 IO76 IO75 IO74 IO73 IO72 VCCIO3(1)1 GNDIO5 IO71 IO70 IO69 IO68 IO67 IO66 GNDINT2 IO/GCLK3 VCCINT(3.3V or 2.5V)2 IO/GCLK2 IO65 IO64 IO63 IO62 IO61 GNDIO4 VCCIO3(1) IO60 IO59 IO58 IO57 IO56 IO55 IO54 IO53 KB/MS IO52

108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

PIN82 PIN81 PIN80 PIN79 PIN78 PIN77 PIN76 PIN75

+3.3V C5 0.1u C6 0.1u C7 0.1u C8 0.1u

RP1 1K

male header JTAG connections: pin# jtag 1 TCK 2 GND 3 TDO 4 Vcc 5 TMS 6 Vccio 7 (NC) 8 (NC) 9 TDI 10 GND

5 6 7 8

+3.3V J7 TCK TDO TMS

1 3 5 7 9

1 3 5 7 9

2 4 6 8 10

2 4 6 8 10

2x5Header
C

Y1 33mhz

JP1

14
0.1u

VCC

OUT2 OUT

8 11 1

4 7

GND OE_n GND2

1 3 5 7 9

2 4 6 8 10

R2 R3 R4 R5 R6

220Ohm 220Ohm 220Ohm 220Ohm 220Ohm

GCLK0 GCLK1 GCLK2 GCLK3 8051CLK

8051CLK

HEADER5X2-2.54 R7 220Ohm

PIN25 PIN26 PIN27 PIN28 PIN29 PIN30 PIN31 PIN32 PIN33

PIN34 PIN35 PIN36 PIN37 PIN38 PIN39

PIN40

PIN41 PIN42 PIN43 PIN44 PIN45 PIN46 PIN47

+3.3V

VCC GND

GND

VCC GND

VCC

PIN48 PIN49 PIN50 PIN51 PIN52 PIN53 PIN54

Do not Stuff R52 for Ocilator operation. Stuff R13 when using Clock input.

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
+3.3V
B

+3.3V J1

+3.3V J2

+3.3V

+3.3V J3

+3.3V

+3.3V J4

+3.3V
B

+3.3V

C9 0.1u

C12 0.1u

C13 0.1u

C14 0.1u

C15 0.1u

C16 0.1u

C17 0.1u

C18 0.1u

C19 0.1u

C11 0.1u

C1 0.1u

C33 0.1u

PIN1 PIN3 PIN5 PIN7 PIN9 PIN11 PIN13 PIN15 PIN17 PIN19 PIN21 PIN23

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34

PIN2 PIN4 PIN6 PIN8 PIN10 PIN12 PIN14 PIN16 PIN18 PIN20 PIN22 PIN24

PIN25 PIN27 PIN29 PIN31 PIN33 PIN35 PIN37 PIN39 PIN41 PIN43 PIN45 PIN47 PIN49 PIN51 PIN53

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34

PIN26 PIN28 PIN30 PIN32 PIN34 PIN36 PIN38 PIN40 PIN42 PIN44 PIN46 PIN48 PIN50 PIN52 PIN54

PIN55 PIN57 PIN59 PIN61 PIN63 PIN65 PIN67 PIN69 PIN71 PIN73 PIN75 PIN77 PIN79 PIN81

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34

PIN56 PIN58 PIN60 PIN62 PIN64 PIN66 PIN68 PIN70 PIN72 PIN74 PIN76 PIN78 PIN80 PIN82

PIN83 PIN85 PIN87 PIN89 PIN91 PIN93 PIN95 PIN97 PIN99 PIN101 PIN103 PIN105 PIN107 PIN109 PIN111

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34

PIN84 PIN86 PIN88 PIN90 PIN92 PIN94 PIN96 PIN98 PIN100 PIN102 PIN104 PIN106 PIN108 PIN110 PIN112

2x17

2x17

2x17

2x17

+3.3V

C34 10u

C35 10u

C36 10u

C37 10u

C38 10u

C39 10u

C40 10u

C41 10u

Title <Title> Size A3 Date:

5 4 3 2

Document Number <Doc> W ednesday, September 22, 2004 Sheet

1

Rev <RevCode> 1 of 2

+3.3V RP2 LedR LedY RP3 D3 PIN3 PIN4 PIN5 PIN6 PIN7 PIN8 LED_Y0 D4 LED_Y1 D5 LED_R0 D6 LED_R1 D7 LED_R2 D8 LED_R3 LedY LedG LedR R8 56.2 RS232A_TXD D9 LedY LedR LedY LedR 330 8 7 6 5 RS232A_TXD RS232A_CTS RS232A_RXD RS232A_RTS 330 8 7 6 5

D1 PIN1 PIN2 LED_G0 D2

D

U3

+3.3V

LED_G1

1 3 4 5
PIN33 PIN34 PIN35 PIN36

C1+ C1C2+ C2-

VCC V+ VGND

16 2 6 15 14 7 13 8
C23 0.1u C22

2 1

2 1

2 1

1 2 3 4

11 10 12 9

TX1IN TX1OUT TX2IN TX2OUT RX1OUT RX1IN RX2OUT RX2IN

ICL3232CA

0.1u

C24 0.1u

C25 0.1u PIN[112:1] PIN[112:1]

RS-232 Activity LEDs

TX
+3.3V

RX
RS232A_RXD +3.3V LedG RS232A1_CTS RS232A1_RXD RS232A1_RTS RS232A1_TXD RP5 1K

10

R9 56.2

D10

RP4 1K

5 9 4 8 3 7 2 6 1 11

J8 DB9RF

FEMALE RS232 CONNECTOR

5 6 7 8

5 6 7 8

Channel A

4 3 2 1

4 3 2 1

SW_S0 SW_S1 SW_S2 SW_S3 SW_S4 SW_S5 SW_S6 SW_S7

PIN9 PIN10 PIN11 PIN12 PIN13 PIN14 PIN15 PIN16 +3.3V R10 1K R11 1K C1 C2 C3 C4 R13 1K PIN21 PIN22 PIN23 PIN24

+3.3V RP6 1K

8 7 6 5

1 2 3 4

P0.0 P0.1 P0.2 P0.3

16 15 14 13 12 11 10 9

SW6 SW-DIP-8

R12 1K

RP7

1K

8 7 6 5
Q4 B MPSA13 +3.3V

1 2 3 4

P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD TXD INT0* INT1* T0 T1 P3.6 P3.7 ALE PSEN* P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 8051CLK

C C1

C C1

C C1

Q1 B MPSA13

Q2 B MPSA13

Q3 B MPSA13

C C1

1 2 3 4 5 6 7 8

U4 RP8 PIN25 PIN26 PIN27 PIN28 100 C42 0.1u

44

+3.3V

8 7 6 5
RP9 100

1 2 3 4

A B C D

VCC

+3.3V

RP10 1K
B

10

11

12

PIN29 PIN30 PIN31 PIN32

8 7 6 5

1 2 3 4

E F G DP

5 6 7 8

PBswitch

SW5 1 2

3 4
C26 10uF

DIG.2

DIG.3

DIG.4

DS1 RST 7SEG3

P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

SW1 1 2 SW2 1 2 SW3 1 2 SW4 1 2

PBswitch 3 4 PBswitch 3 4 PBswitch 3 4 PBswitch 3 4

1 2 3 4 5 6 7 8 9 10 12

user_PB0

NC P1.0(T2) P1.1(T2 EX) P1.2 P1.3 P1.4 P1.6 P1.7 P1.8 RST NC1 P3.0(RXD) P3.1(TXD) P3.2(/INT0) P3.3(/INT1) P3.4(T0) P3.5(T1) P3.6(/WR) P3.7(/RD)

W78L51(PLCC)

P0.0(AD0) P0.1(AD1) P0.2(AD2) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7)

43 42 41 40 39 38 37 36

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

2 1

PIN17

/EA NC3 ALE /PSEN

35 34 33 32

4 3 2 1

ALE PSEN*

R14 1K user_PB1 PIN18

user_PB2

PIN19

RXD TXD INT0* INT1* T0 T1 P3.6 P3.7

11 13 14 15 16 17 18 19

P2.7(A15) P2.6(A14) P2.5(A13) P2.4(A12) P2.3(A11) P2.2(A10) P2.1(A9) P2.0(A8)

31 30 29 28 27 26 25 24

P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0

DP

PIN20

20 21

C27

C28 0.1u

C29 0.1u

C30 0.1u

22 23

GND NC2

user_PB3

XTAL2 XTAL1

DIG.1

Switches Buttons

0.1u

Y2 CRYSTAL 8051CLK

C31 10p
A

C32 10p
A

Title <Title> Size C Date:

5 4 3 2

Document Number <Doc> Wednesday, September 22, 2004

1

1 2 3 4

C20 0.1u

C21 0.1u

H1 HOLEC173D71BC205-V6 5 4 6 3

H2 HOLEC173D71BC205-V6 5 4 6 3

H3 HOLEC173D71BC205-V6 5 4 6 3

H4 HOLEC173D71BC205-V6 5 4 6 3

2 1
D

+3.3V

PIN37 PIN38 PIN39 PIN40 PIN41 PIN42 PIN43 PIN44 PIN45 PIN46 PIN47 PIN48 PIN49 PIN50 PIN51 PIN52 PIN53 PIN54 PIN55 PIN56 PIN57 PIN58 PIN59 PIN60 PIN61 PIN62 PIN63 PIN64 PIN65 PIN66 PIN67 PIN68 PIN69 PIN70 PIN71 8051CLK

R15 1K

R16 R

Rev <RevCode> Sheet 2 of 2