VHDL Guide

Very high speed integrated circuit Hardware Descriptive Language

VHDL design flow

Write a HDL code for your target application or specification. Check the Simulation result

VHDL/VERILO G

Here convert HDL language to circuit net list and also checks it is Possible to convert a circuit

Synthesis

Map/Place & Route to target FPGA/CPLD IC and interconnect the Configurable logic Blocks & I/Os

Mapping / Place & Route

Placing logical blocks inside IC.It reduce the timing Of interconnected wires

Floor Planning

Generate a bit stream to download program to target IC

Bit Stream

Download to target Board or IC and check the result

Download

VHDL Syntax Rules

Not Case Sensitive Semicolon after each Statement Two Dashes indicates a Comment Identifiers must start with an Alpha Character Identifiers are composed of Alpha, Numeric, and Underscore Characters Strongly Typed Language Units of VHDL design are called BLOCKS Library references a group of previously defined VHDL designs Use selects which items in a library to use IEEE.STD_LOGIC_1164 Library Defines data types Bits are std_logic Buses are std_logic_vector (range) Z - High impedance 1 or H - logic high 0 or L - logic low - For don't care Includes basic logic function designs IEEE.STD_ULOGIC Library defines these additional types: U for uninitialized X for forcing unknown W for weak unknown

Levels of Abstraction (Design Description)

Behavior

Highest level Describe circuit in terms of operation over time Includes State diagram Timing diagrams Algorithmic descriptions Time expressed using delays Time expressed as an order of sequential operation

Synthesis tool ignore specific timing leaving actual results to target device technology Describe circuit in terms of how data moves through system Combinational logic (Boolean expressions) Also known as register transfer level (RTL) No built in registers in VHDL Create register elements

Dataflow

Add register elements to design as components, functions or procedures Describe circuit in terms of components Structure Netlist - interconnecting signals

Modular design approach

VHDL BASIC

Entity and Architecture Data Types Components and Signals Process, Variables, Sensitivity List Generic Conditional Statements Loops Subprograms - Functions and Procedures State Diagram Design Libraries, Packages Test Bench Configuration Statement

Entity Block

Syntax
ENTITY entity_name IS PORT ( identifier : mode type; identifier : mode type ); END entity_name; Notes: External view of our component Entity defines interface signals for the design. mode is IN, OUT, INOUT or BUFFER type is data type such as bit or std_logic

Example

entity my_and is port ( A, B : in std_logic; Y : out std_logic ); end my_and;

Architecture Block

Syntax

Example

ARCHITECTURE architecture_name OF entity_name IS signal declarations; constant declarations; component declarations; Type declaration; BEGIN statements conditions; END architecture_name; architecture AND_GATE OF my_and IS begin Y <= A and B; end AND_GATE;

Notes: Internal operation of our Target application or specification Inside the architecture all are concurrent Design's behavior or structure is defined in the architecture block. Statements in the architecture block are executed concurrently.

Operators Defined in IEEE.STD_LOGIC_1164 Type

Logic operate on: std_logic or and nand

Operator

std_logic_vector data types and for complex conditionals in if..then statements.

or nor xor xnor not <= for std_logic and std_logic_vector assignments

Assignment

:= to set initial values for any type and for assigning values to all types except std_logic and std_logic_vector.

Data Flow Example: Latch

-- Library block library ieee; use ieee.std_logic_1164.all; -- Entity Declaration entity latch is port ( s, r : in std_logic; q, nq : out std_logic); end latch; -- Architecture block architecture r_s of latch is begin q <= r nor nq; nq <= s nor q; end r_s;

ieee Parent library ieee.std_logic_1164 Sub library file all Specifies all parts of ieee.std_logic_1164 library latch entity name s, r, q, nq Interface signal names in, out Signal modes std_logic Defines logic bit type r_s Architecture name <= Signal assignment operator nor
ieee std_logic_1164 standard logic NOR function

Data Types

Type
1. Bit or std_logic Bit_vector or std_logic_vector Boolean Integer Natural Real Enumerated Record Array Access File Physical Line

Definition
1. Binary bit - bit is nonstandard Binary bus or array of bits True or false Whole numbers Positive numbers Complex numbers User type Collection of data Single and multidimensional Pointer Disk access Symbolic units - time, voltage, etc ASCII string

Binary Data Types

Syntax
Non-standard, limited to two values (1, 0): bit for single binary bit bit_vector (range) for bus or array of bits IEEE Standard type has 9 possible values including: 1, 0, unknown, high impedance, don't cares, etc.: std_logic for single binary bit std_logic_vector (range) for bus or array of bits Range can be LSB to MSB or MSB downto LSB

Example

For an eight bit data bus: std_logic_vector ( 7 downto 0 )

Enumerated Type Syntax Example

TYPE identifier is ( type values ); type op_code is (ADD, SUB, MUL, DIV);

Subtyping Syntax
subtype name type range num1 to or downto num2; Example: integer type value range is -2,147,483,647 to +2,147,483,647 Can use subtyping to limit an integer range. subtype short integer range 0 to 255; Two built in subtypes in VHDL are natural ( all positive numbers beginning with 0 ) positive ( all positive numbers beginning with 1 )

Using Std_logic_vector as an Array of Bits Sample Design

entity demux is

port ( e : in std_logic_vector ( 3 downto 0 ); s : in std_logic_vector (1 downto 0); d : out std_logic_vector (3 downto 0)); end demux; architecture rt1 of demux is signal t : std_logic_vector (3 downto 0); begin -- Use single bits from two arrays: t(3) <= s(1) and S(0); t(2) <= s(1) and not S(0); t(1) <= not s(1) and S(0); t(0) <= not s(1) and not S(0); -- Assign entire array -- using the same size -- arrays: d <= e and t; end rt1;

Creating a User Array Syntax Example

TYPE array_name IS ARRAY (range) OF type; to create an unbound array use this for range: natural range <> as in: type myArray is array (natural range <>) of std_logic;

type array1 is array (0 to 15) of std_logic; creates an array of 16 bits that are not specified as inputs or outputs. type a2Darray is array (0 to 4) of array1; creates a two demensional array with five rows, each 16 bits. type a3Darray is array (6 to 9) of a2Darray; creates a 4 element three-demensional array. Each element has five rows of 16bits each.

Using OTHERS to Populate an Array. Format Populated Elements

Sets all elements of array1 to 0 array1 <= (2 => '1', 4 => '1', others => '0' ); Sets elements 2 and 4 high and the rest low

1. array1 <= (others => '0');

Concantenation Example Sectioning a Bus

signal d_bus : std_logic_vector (0 to 7); signal cntrl : std_logic_vector (0 to 1); signal enable, RW : std_logic; signal count : std_logic_vector (0 to 3); d_bus <= cntrl & enable & RW & count; '0' & '1' = "01" results: d_bus (0 to 1) = cntrl d_bus(2) = enable d_bus(3) = RW d_bus (4 to 7) = count. 'C' & 'a' & 't' = "Cat" "BA" & "LL" = "BALL"

Other Examples

8-Bit Counter
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity my_counter is port ( clk, reset, enable : in std_logic;

qb : out std_logic_vector (7 downto 0)); end my_counter; architecture my_bin_count of my_counter is begin process (clk, reset) variable count : integer range 0 to 255 := 0; begin if enable = '0' then qb <= ( others => 'Z'); elsif reset = '1' then qb <= (others => '0'); elsif clk = '1' and clk'event then if count = 255 then count := 0; else count := count + 1; end if; qb <= count; end if; end process; end my_bin_count;

Concantenation Example Sectioning a Bus

signal d_bus : std_logic_vector (0 to 7); signal cntrl : std_logic_vector (0 to 1);

Other Examples

signal enable, RW : std_logic; signal count : std_logic_vector (0 to 3); d_bus <= cntrl & enable & RW & count; '0' & '1' = "01" results: d_bus (0 to 1) = cntrl d_bus(2) = enable d_bus(3) = RW d_bus (4 to 7) = count. 'C' & 'a' & 't' = "Cat" "BA" & "LL" = "BALL"

Type Conversion Syntax

name <= conv_dataType ( name_orig, range );

Example
qout <= conv_std_logic_vector ( count, 3);

Notes on using this type conversion:

1. requires ieee.std_logic_arith library where conv_ is defined. if count is an integer type, its largest value must fit into the number of bits assigned to qout. in this example: qout is a vector range of 2 downto 0 or 3 bits count is an integer from 0 to 7 Notice that the range value of 3 matches the number of bits in qout represents integer values 0 to 7.

Attributes Syntax
name'left left most value name'right right most value

Example

signal sig1 : std_logic_vector ( 6

name'high upper end of string name'low lower end of string name'range upper downto lower lower to upper name'reverse_string shows order in reverse name'length number of elements in array or string name'event change of element's value

downto 0 ); signal sig2 : std_logic_vector ( 1 to 8 ); sig1'left = 6 sig1'right = 0 sig'high = 6 sig'low = 0 sig1'range = 6 downto 0 sig1'length = 7 sig1'reverse range = 0 to 6 sig2'left = 1 sig2'right = 8 sig2'high = 8 sig2'low = 1 sig2'length = 8

Record Type Syntax

TYPE name IS RECORD element_name : type; element_name : type;

Example

type INSTR_T is record mnemonic : string (1 to 14); code : std_logic_vector (3 downto 0); execycles : integer; end record; element_name : type; END RECORD; Record element access assignment: record_name.element_name : value; Assign record names: signal INSTR1, INSTR2, INSTR3 : INSTR_T; Assign element values: INSTR1.mnemonic : "ADD reg1,reg2"; INSTR1.code : "0010"; INSTR1.execycles : 2; or use initialization assignment: signal INSTR1 := ("ADD reg1,reg2", "0010", 2);

Record Example Records

Example

Elements are of type control is record different types start : boolean; Stored in left to right order parity : std_logic; when group assignment address : integer range 0 to 3; Records can be compared data : std_logic_vector (7

for equality specified assignments can be done in any order record elements can be assigned individual or in group

downto 0); end record; signal control1, control2, control3 : control; begin control1 <= (false, '0', 2, "00001111"); control2.address <= 3; control2.data <= (others => '0'); control3 <= ( parity => '1', data => "00110011", address => 3, start =>false); -- compare records if control1 = control2 then --statements end if;

4:Components and Signals

Components
Component Declaration component comp_name is port ( interface declarations ); Notes Component declaration must match the entity declaration for the design

end component; Component Instantiation

being used as the component. Port maps can be defined in two ways: A) positional association: Associated signals must be in the same order as they appear in the componet port declaration. B) named association: Signals are mapped by copy_names => components_names Examples positional association: p1 : Ex_Gate port map (in1, in2, in3, out1, out2); named association: p2: Ex_Gate port map ( in1 => A, in2 => B, in3 => C, out1 => X, out2 => Y );

label : comp_name port map (signal_names);

component Ex_Gate is port ( A, B, C : in std_logic; Y, X : out std_logic ); end component;

Signal Declaration Purpose

To declare interconnecting lines between components in a design. signal signal_name : type;

Syntax and Example

-signal set, reset : std_logic;

Components Example: Exclusive OR

-- create parts -- AND Gate library ieee; use ieee.std_logic_1164.all; entity my_and is port (A, B : in std_logic; Y : out std_logic ); end my_and; architecture and_gate of my_and is begin Y <= A and B; end and_gate; -- OR Gate library ieee; use ieee.std_logic_1164.all; entity my_or is port (A, B : in std_logic; Y : out std_logic ); end my_or; architecture or_gate of my_or is begin Y <= A or B; end or_gate;

-- Inverter Gate library ieee; use ieee.std_logic_1164.all; entity my_not is port (A : in std_logic; Y : out std_logic ); end my_not; architecture inv_gate of my_not is begin Y <= not(A); end inv_gate;

Components Example: Exclusive OR

-- Start Exclusive OR Design library ieee; use ieee.std_logic_1164.all; entity my_xor is port ( A, B : in std_logic; Y : out std_logic ); end my_xor; architecture xor_gate of my_xor is -- declare internal signals signal X, M, T, S : std_logic; -- declare components component my_and is port (A, B : in std_logic; Y : out std_logic ); end component; component my_or is port (A, B : in std_logic; Y : out std_logic ); end component; component my_not is port (A: in std_logic; Y : out std_logic ); end component; begin -- instantiate components n1 : my_not port map ( A, X ); n2 : my_and port map ( X, B, T ); n3 : my_or port map ( T, S, Y ); n4 : my_not port map ( B, M ); n5 : my_and port map ( M, A, S ); end xor_gate;

5:Process, Variables, Sensitivity List

Process Statement Notes Syntax

Sequential Satements Uses Sensitivity List to trigger process

Runs once on initiating simulation

process(sensitivity list) variable declarations; begin sequential statements; end process;

Variables Notes

Example

Assigned in a Process, Function, or Procedure only. Defined and initialized only when simulation begins Not effected by event occurance process(A) syntax: variable count_A : variable var_name : type := integer := -1; initial_value; begin count_A := count_A default initial value is 0 or null + 1; end process; The example keeps track of the amount of times A changes.

Process Example Code Explanation

X and Z are initialized to process(Y) 0 when simulation begins. variable X, Z : std_logic; When Y changes (say from 0 to begin 1) X := Y; X changes to Y's value (1) Z := not X; and then Z changes to the end process; complement of X (0 in this case) This follows the sequential nature of a process. What if these statements were not in a process. Their operation would be concurrent. X would change to the state of Y And at the same time Z would become the complement of X BEFORE it was changed by the X := Y statement!

Use of 'EVENT

Process Syntax

Example

process(var_name) begin if (var_name = 'state' and var_name'EVENT) then staements; end if; end process;

process(CLK) variable count : integer := 0; begin if (CLK = '1' and CLK'event) then count := count + 1; end if; end process;

Simulation sets count variable to 0 initially and starts process body. If statement prevents count := count + 1 from executing because an event on CLK did not occur.

'EVENT will also force statements to be executed on the CLK edge since the if condition requires a change in CLK due to the CLK'EVENT condition.

Generic

GENERIC STATEMENT
Syntax Example

entity my_nand generic ( N : natural := 5 ); generic ( identifier : type := port ( A : in std_logic_vector ( 1 value ); to N ); Y : out std_logic ); end my_nand; Used to declare a constant in an entity. Global to the that design only.

The number of inputs to the nand gate can be changed simply by changing the value of N.

Conditional Statements
IF..THEN..ELSE

Syntax
IF condition THEN statements; ELSE statements; END IF;

Example

IF SEL = '1' THEN Y <= in0; ELSE Y <= in1; ELSE section is optional END IF;

Nested IF..THEN..ELSE Syntax

IF condition THEN statements; ELSIF condition THEN statements; ELSE statements; END IF;

Example

IF OUTEN = '0' THEN Qout <= "ZZZZ"; ELSIF LOAD = '1' THEN Qout <= Din; ELSE section is optional ELSE Qout <= Dbus; END IF;

Shorthand IF..THEN..ELSE Syntax

identifier <= expression_true WHEN condition ELSE expression false;

Example

Y <= A and B WHEN S = '0'

Shorthand IF..THEN..ELSE Syntax

identifier <= expression_true WHEN condition ELSE expression false; Y <= A and B WHEN S = '0' ELSE A or B;

Example

WHEN Construct

Sequential Condition Test

Example

identifier <= expression1 WHEN condition 1 ELSE expression2 WHEN condition2 ELSE expression3 WHEN print1 <= condition3 user1 WHEN (en = '1' and sel ELSE expressionN WHEN = '0') ELSE OTHERS; user2 WHEN (en = '1' and sel = '1') ELSE user3 WHEN OTHERS;

WITH/SELECT

Syntax
WITH test_variable SELECT identifier <=

Example

expression1 WHEN test_val1, expression2 WHEN test_val2, expression3 WHEN test_val3, expression4 WHEN OTHERS;

WITH SEL SELECT Y <= A WHEN "00", B WHEN "01", C WHEN "10", D WHEN "11", 'Z' WHEN OTHERS;

CASE Statement

Syntax

Example

CASE test_var IS WHEN test_val1 => identifier <= expression1; WHEN test_val2 => identifier TYPE op IS (ADD, SUB, MUL, DIV); <= expression2; SIGNAL op_code : op; WHEN test_val3 => identifier PROCESS (op_code, A, <= expression3; B) WHEN test_val4 => identifier BEGIN <= expression4; CASE op_code IS WHEN test_val5 => identifier WHEN ADD => Y := A + <= expression5; B; WHEN OTHERS => identifier WHEN SUB => Y := A <= expression6; B; WHEN MUL = > Y := A := may be used instead of <= * B; Conditional test is done on all WHEN DIV => Y := A / values concurrently. B; WHEN OTHERS => Y := Y; END CASE; END PROCESS;

8.Loops

Unconditional LOOP

Syntax

Example

label : LOOP statements; END LOOP label; Label is optional

process begin L1 : loop clk <= not clk after 5ns; end loop L1; wait end process;

FOR LOOP

Syntax

Example

Used in a process, function or procedure only. FOR count_var IN start_value TO end_value LOOP statements; END LOOP; DOWNTO can be used to replace TO var'RANGE can be used in place of the specified range for i in 7 downto 0 loop Y := Y xor X(i); end loop; Using 'range: for n in word'range loop Y := Y xor word(n); end loop;

Loop Example

Parity Generator
signal X : std_logic_vector (7 downto 0); process (X) variable P : std_logic; begin P := '0'; for i in 7 downto 0 loop P := P xor X(i); end loop; end process; Assignment statement P := P xor X(i) executes 8 times. Variable P is updated each loop by exclusive OR process with each bit in word X. This process finds the even parity state for word X.

WHILE Loop

Syntax

Example

Used in a process, function or procedure only. WHILE condition LOOP statements; END LOOP; An initial value must be given the condition before entering the WHILE loop and the condition must be modified in the LOOP.

Shift operation process (X) variable i : integer := 1; begin while i <= 8 loop X(i) <= X(i+1) after 5 ns; i := i + 1; end loop; end process;

EXIT

Syntax
EXIT is used to exit a loop early. LOOP statements; EXIT WHEN condition; END LOOP; Alternate Syntax LOOP statements; IF condition THEN EXIT; END LOOP:

Example

for i in 0 to 10 loop X := X + Y; exit when X = 20; end loop; or: for i in 0 to 10 loop X := X + Y; if X = 20 then exit; end loop;

Generate

Notes
Used as looping construct to create multiple instanitations of components. Syntax: FOR variable IN range GENERATE statements; END GENERATE;

Example

C(0) <= Cin; for i in 0 to 7 generate FA(i) : my_fulladd port map ( Ain(i), Bin(i), C(i), Sum(i), C(i + 1); end generate; Cout <= C(8);

9.Subprograms - Functions and Procedures

Subprograms

Concepts Contains Sequential Statements Are used in: Architectures Processes Packages (Libraries) Types of Subprograms: Function - returns a single value Procedure - zero to many returned values

Function
1. Pass input parameters only return single output must use RETURN statement called using an assignment statement

Function

Syntax
function function_name ( parameter : type ) return return_type is variable declarations; begin statements; return return_variable_name; end function_name;

Function Call

variable <= function_name ( actual parameter );

Function Example

4-Bit Adder
function add4 ( A, B : std_logic_vector( 3 downto 0 ); carry : std_logic ); return std_logic_vector is variable cout : std_logic; variable cin : std_logic := carry; variable sum : std_logic_vector( 4 downto 0 ) := "00000"; begin loop1 : for i in 0 to 3 loop cout := ( A(i) and B(i) ) or ( A(i) and cin ) or ( B(i) and cin ); sum(i) := A(i) xor B(i) xor cin; cin := cout; end loop; sum(4) := cout; return sum; end add4;

Typical call: result <= add4( X, Y, '0' );

Using 'RANGE

Application
The 'range event is used when the size of parameter is unknown. Parity Generator: function parity ( word : std_logic_vector ) return std_logic is variable tmp : std_logic; begin for i in word'range loop tmp := tmp xor word(i); end loop; return tmp; end parity;

Call : parity_bit <= parity (data_in);

Procedure

1. pass input and output parameters 2. multiple results 3. no return statement 4. called as a procedure

Syntax
procedure procedure_name ( parameter : mode type ) is variable declarations; begin statements; end procedure_name;

Procedure Call

procedure_name ( actual parameter );

Procedure Example

Adding n-bit Numbers

procedure addvec ( add1, add2 : in std_logic_vector; cin : in std_logic; sum : out std_logic_vector; cout : out std_logic; n : in integer ) is variable c : std_logic; begin c := cin; for i in 0 to n-1 loop sum(i) <= add1(i) xor add2(i) xor c; c := ( add1(i) and add2(i) ) or (add1(i) and c ) or ( add2(i) and c ); end loop; cout <= c; end addvec;

call: addvec( A, B, '0', Sum, Carry, 8 );

Procedure Example

ALU
type op_code is (ADD, SUB, MUL, DIV, LT, LE, EQ ); procedure arith_unit ( A, B : in integer; op : in op_code; Z : out integer; Zcomp : out boolean ) is begin case op is when ADD => Z := A + B; when SUB => Z := A - B; when MUL => Z := A * B; when DIV => Z := A / B; when LT => Zcomp := A < B; when LE => Zcomp := A <= B; when EQ => Zcomp := A = B; when others => Z := Z; end case; end arith_unit;

call: arith_unit( Numb1, Numb2, MUL, Product, Compare);

10.State Diagram Design

State Diagram Example

Design Code
entity my_state is port (reset, clk, enable : in std_logic; qout : out std_logic); end my_state; architecture machine of my_state is type statetype is ( state0, state1 ); signal state, next_state : statetype := state0; begin process (clk, reset) begin if reset = '1' then next_state <= state0; elsif clk = '1' and clk'event then

State Diagram

Toggle Flip Flop

State Diagram Example

Design Code
-- Check state case state when state0 => if enable = '1' then next_state <= state 1; else next_state <= state0; end if; when state1 => if enable = '1' then next_state <= state0; else next_state <= state1; end if; when others => next_state <= next_state; end case; end if;

State Diagram

Toggle Flip Flop

State Diagram Example

Design Code

State Diagram

state <= next_state; -- Set output condition case state when state0 => qout <= '0'; when state1 => qout <= '1'; when others qout <= '0'; end case; end process; end machine; Toggle Flip Flop

11.Libraries, Packages

Libraries

WORK Library

Current files are stored in work library as well as user defined library.

No library declaration Must have USE statement:

Allows access to any designs in current work library.

use work.my_designs.all;

User Defined Library

User defined library entries: Functions Procedures Enumerated Types and Subtypes Components Constants Shared Variables

PACKAGE - Hold commonly used declarations for global use in designs.

PACKAGE BODY - required when including functions and procedures.

WORK Library

Compiled designs are stored here if no user library specified. Requires a use statement to access designs for use in other designs: use.work.design_pkg.all; use statement must precede each entity declaration. Package Visibility Any package is visible (available for use) through the use statement. All items in my_package of work library: use.work.my_package.all; addMe procedure in my_package of work library: use.work.my_package.addMe.; All items in work library: use.work.all;

Libraries

Creating Packages
Packages can be included within the same source file as other design units or placed into a separate stand alone file. package package_name is function_names; procedure_names; component_declaration s; enumerated data types; end package name; Accessing Package - use statement must precede entity or architecture declaration of the design that is going to use the contents of the package.

library library_name; use library_name.package_name.al l;

Subprograms Stored in Package - Package Body Only one package body per package declaration. package body package_name is complete function declarations; complete procedure declarations; end package body package_name;

Package Example

Package Declaration
package conversion is function to_vector ( size : integer; num : integer) return std_logic_vector; end conversion;

Package Body
package body conversion is function to_vector ( size : integer; num : integer) return std_logic_vector is variable ret : std_logic_vector(1 to size); variable a : integer; begin a := num; for i in size downto 1 loop if ((a mod 2) = 1) then ret(i) = '1'; else ret(i) = '0'; end if; a : = a/2; end loop; return ret; end to_vector; end conversion;

Using Package - Carry Out Example

Creating Package
package logic_ops is component AND2_OP port ( A, B : in std_logic; Z : out std_logic); end component; component OR3_OP port ( A, B, C : in std_logic; Z : out std_logic ); end component; component NOT_OP port ( A : in std_logic; Z : out std_logic ); end component; end logic_ops;

Using Package
use work.logic_ops.all; entity carry is port ( A_in, B_in, Cin : in std_logic: carry_out : out std_logic ); end carry; architecture structure of carry is signal int1, int2, int3 : std_logic; begin A1 : AND2_op port map (A_in, B_in, int1); A2 : AND2_op port map (A_in, C_in, int2); A3 : AND2_op port map (B_in, C_in, int3); O1 : OR3_op port map (int1, int2, int3, carry_out); end structure;

Libraries

Example Creating a Package

library ieee; use ieee_std_logic_all; -- package declaration package BCD_functions is function correct (decade : unsigned (3 downto 0)) return unsigned; end BCD_functions; -- package body package body BCD_functions is function correct (decade : unsigned (3 downto 0)) return unsigned is variable corrected : unsigned ( 3 downto 0 ) := decade; begin if corrected >= 5 then corrected := corrected + 3; end if; return corrected; end correct; end BCD_functions;

Full Design Using a Package:

ADC Data Delay Schematic

Circuit operation: COUNT is set high when ready to begin operation. RESET is set high momentarily to clear counter, D-FF and registers. Data from an ADC is applied to ADC DATA input. LOAD is set high momentarily to load register. Comparator senses difference between counter (00) and Buffer register (ADC Data). The high signal from the comparator enables the counter to begin counting. When the count reaches ADC Data value, the comparator switches state setting the D-FF. The comparator output is sent out as signal DELAY. Reg8Bit is loaded when the D-FF is set, placing ADC Data on ADC DLYD outputs. The larger the ADC Data value, the longer the delay.

ADC Delayed Parts - Mod 256 Counter

VHDL File
-- File: counter.vhd -- created by Mike Miller: 08/22/02 10:50:32 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity mod256ctr is port ( RST, CLK, EN1, EN2 : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (7 downto 0) ); end mod256ctr; architecture count_up of mod256ctr is begin process ( RST, CLK ) variable qtemp : integer; begin if RST = '1' then qtemp := 0; Q <= ( others => '0' ); elsif CLK = '1' and CLK'event then if EN1 = '1' and EN2 = '0' then if qtemp < 255 then qtemp := qtemp + 1; else qtemp := 0; end if; end if; end if; Q <= conv_std_logic_vector(qtemp, 8);

Comments
Counter Operation: Reset to 00H when RST is set high. Counts on positive edge of CLK. Counts when EN1 = 1 and EN2 = 0.

end process; end count_up;

Counter Waveform:

ADC Parts - Buffer VHDL Code

-- File: buffer.vhd -- created by Mike Miller: 08/22/02 11:18:50

Operation
1. Q = 00H when RST =1

library IEEE; use IEEE.std_logic_1164.all; entity latch8 is port ( CLK. RST, TRIG : in STD_LOGIC; Din : in STD_LOGIC_VECTOR (7 downto 0); Q : out STD_LOGIC_VECTOR (7 downto 0) ); end latch8; Q = Din when TRIG = 1 architecture buff8 of latch8 is begin on positive edge of process ( RST, CLK, TRIG ) CLK begin if RST = '1' then Q <= ( others => '0' ); elsif CLK = '1' and CLK'event then if TRIG = '1' then Q = Din; end if; end if; end process; end buff8;

ADC Parts - Comparator VHDL Code

-- File: comparator.vhd -- created by Mike Miller: 08/22/02 11:36:44 library IEEE; use IEEE.std_logic_1164.all; entity comp8 is

Operation
COMP is set high when Ain = Bin. Otherwise COMP is set low.

port ( Ain, Bin : in STD_LOGIC_VECTOR (7 downto 0); comp : out STD_LOGIC ); end comp8; architecture compare8 of comp8 is begin process ( Ain, Bin ) begin if Ain = Bin then comp <= '1'; else comp <= '0'; end if; end process; end compare8; Compare Waveform:

ADC Parts - Inverter and D-Flip Flop

VHDL Inverter Code

-- File: Inverter.vhd -- created by Mike Miller: 08/22/02 11:44:20 library IEEE; use IEEE.std_logic_1164.all; entity my_not is port ( A : in STD_LOGIC; Y : out STD_LOGIC ); end my_not; architecture invert of my_not is begin Y <= not A; end invert;

Operation

Output Y is the inverse of input A

VHDL D-FF Code

-- File: D_flipflop.vhd -- created by Mike Miller: 08/22/02 11:50:27 library IEEE; use IEEE.std_logic_1164.all; entity D_FF is port ( CLK, RST : in STD_LOGIC; Q : out STD_LOGIC ); end D_FF; architecture dataFF of D_FF is begin process (RST, CLK)

Operation
Q is set to 1 when RST = 0 and CLK =1 on positive edge of CLK Q is set to 0 when RST = 1

begin if RST = '1' then Q <= '0'; elsif CLK = '1' and CLK'event then Q <= '1'; end if; end process; end dataFF;

ADC Parts - Register VHDL Code

-- File: register.vhd -- created by Mike Miller: 08/22/02 11:28:40 library IEEE; use IEEE.std_logic_1164.all; entity reg_8bit is port ( CLK. RST, LDR : in STD_LOGIC;

Operation
1. Q = 00H when RST = 1 Register is loaded on positive edge of CLK Q = Din when LDR = 1 when clocked

Din : in STD_LOGIC_VECTOR (7 downto 0); Q : out STD_LOGIC_VECTOR (7 downto 0) ); end reg_8bit; architecture reg_buff of reg_8bit is begin process ( RST, CLK ) begin if RST = '1' then Q <= ( others => '0' ); ;elsif CLK = '1' and CLK'event then if LDR = '1' then Q <= Din; end if; end if; end process; end reg_buff;

ADC Delayed Package Package Code

library IEEE; use IEEE.std_logic_1164.all; package parts_pkg is component mod256ctr is port ( RST, CLK, EN1, EN2 : in STD_LOGIC; Q: out STD_LOGIC_VECTOR (7 downto 0) ); end component; component latch8 is port ( CLK, RST, TRIG : in STD_LOGIC; Din: in STD_LOGIC_VECTOR (7 downto 0); Q: out STD_LOGIC_VECTOR (7 downto 0) ); end component;

component reg_8bit is port ( CLK, RST, LDR: in STD_LOGIC; Din : in STD_LOGIC_VECTOR (7 downto 0); Q : out STD_LOGIC_VECTOR (7 downto 0) ); end component; component comp8 is port ( Ain, Bin : in STD_LOGIC_VECTOR (7 downto 0); comp : out STD_LOGIC ); end component; component my_not is port ( A: in STD_LOGIC; Y: out STD_LOGIC ); end component; component D_FF is port ( CLK, RST : in STD_LOGIC; Q : out STD_LOGIC ); end component; signal Abus, Bbus : std_logic_vector( 7 downto 0 ); signal TRIGON, S : std_logic; end parts_pkg;

ADC Delayed Cicuit

VHDL Code

Notes

-- File: ADC_Delay.vhd 1. Components and -- created by Mike Miller: 08/22/02 interconnecting signals 12:08:17 declared in package library IEEE; accessed through USE use IEEE.std_logic_1164.all; WORK.PARTS_PKG use IEEE.std_logic_arith.all; library. use work.parts_pkg.all; entity adc_delay is Parts instantiated from the port ( COUNT, RESET, CLK, components in the LOAD: in STD_LOGIC;

ADC_DATA : in STD_LOGIC_VECTOR (7 downto 0); ADC_DELAYED : out STD_LOGIC_VECTOR (7 downto 0); DELAY : out STD_LOGIC ); end adc_delay; architecture adc_out of adc_delay is begin U1 : mod256ctr port map ( RESET, CLK, COUNT, S, Abus ); U2 : reg_8bit port map ( CLK, RESET, LOAD, ADC_DATA, Bbus ); U3 : comp8 port map ( Abus, Bbus, S ); U4 : my_not port map ( S, DELAY ); U5 : D_FF port map ( S, RESET, TRIGON ); U6 : latch8 port map ( CLK, RESET, TRIGON, Bbus,

package.

ADC_DELAYED ); end adc_out;

ADC Delayed Waveforms:

Libraries TEXTIO Library: Provide input and output functions.

Internal Library, but must have USE statement before architecture block: write() appends information at end of line. writeln() sends line data to monitor and empties line for

use textio.all;

reuse.

library ieee; use ieee.std_logic_1164.all; entity counter is port ( X : in std_logic ); end counter; use textio.all; architecture count_it of counter is begin process ( X ) variable S : line; variable cnt : integer := 0; variable max_count : integer := 25; begin if ( X = '1' and X'last_value = '0' ) then cnt := cnt + 1; if ( cnt > max_count ) then write ( S, cnt ); writeln ( output, S ); end if; end if; end process; end count_it;

Test Benches - Virtual Circuit Testers

Notes
1. Set up stimuli for input signals Create clock signal Determine test vectors Generate report Begins with an empty entity declaration

"Example"

Uses component instantiation for unit under test (UUT) Syntax: ENTITY testbench_name IS END testbench_name; ARCHITECTURE testbench_archname of testbench_name is signal declarations; component declarations; begin UUT : component instantiation; stimuli; REPORT "Message" SEVERITY severity level; END testbench_archname;

Stimuli

Assertion Statement Notes

1. Generate Stimuli Set up test vector Reports Errors

Example

Syntax: ASSERT condition REPORT "string" SEVERITY severity_level;

library IEEE; use IEEE.std_logic_1164.all; library my_gates; use my_gates.all; entity bcd is end bcd; architecture decoder of bcd is component decoder_bcd is port ( led : out std_logic_vector (3 downto 0); bcd : in std_logic_vector (1 downto 0)); end component; begin UUT : decoder_bcd port map (led, bcd); bcd <= "00" after 5 ns, "01" after 15 ns, "10" after 25 ns, "11" after 35 ns; -- Note: times are actual time changes occur assert bcd = "00" and led = "0001" or bcd = "01" and led = "0010" or bcd = "10" and led = "0100" or bcd = "11" and led = "1000" report "There is an incorrect value on the output led." severity error; end decoder;

Severity Levels: NOTE Information Simulation unimpaired WARNING Unpredictable Results Simulation unimpaired ERROR Unpredictable Results Continuing simulation may no be possible FAILURE Fatal Error Simulation stopped immediately

Generating a Clock Signal Example 1 Example 2

process begin CLK <= '0'; wait for 20ns; CLK < = '1'; wait for 20ns; end process; endsim := false; clock : process begin if not endsim then CLK <= '0'; wait for 5ns; CLK <= '1'; wait for 5ns; else wait; end if; end clock;

CLK <= not CLK after 10ns;

Notes 1) Processes without a sensitivity list requires a WAIT statement within the body of the process. 2) Processes without a sensitivity list are begun when simulation is started and can be made to run continuously.

Formulas (Waveforms)

Reset Signal

Notes

reset : process begin rst <= '1'; wait for 10ns; rst <= '0'; wait for 350ns; endsim := true; wait; end reset;

Reset is made active for 10ns. After reset is made inactive, the simulation continues for 350ns and then sets endsim true which stops the CLK on the previous slide.

Projected Waveforms Examples

architecture test_waves of

Notes
1. Signals have previous, current,

test_bench is signal wave1, wave2 : std_logic; begin wave1 <= '0' after and future values 20ns, '1' after 50ns; Waveforms can be specified using process wait or after clauses begin wave2 <= '1'; wait for Known as projected signal 20ns; assignments wave2 <= '0'; wait for 30ns; wave2 < = '1'; wait; end process;

Test Bench Examples

BCD Decoder entity TB_BCD is end TB_BCD; architecture bcd_test of

Notes
1. Test bench starts with an empty entity

TB_BCD is component Decoder_BCD is port ( enable : in std_logic; led : in std_logic_vector ( 3 downto 0 ); bcd : out std_logic_vector ( 1 downto 0 )); end component;

* * *

In order to stop simulation, stimuli (inputs) are included signal bcd : std_logic_vector ( 1 downto 0 ) := "11"; in a process statement signal enable : std_logic; without a sensitivity list. An signal led : std_logic (3 downto unconditional wait 0); statement is required in the begin body of the process.
UUT : Decoder_BCD port map (enable, led, bcd);

* Includes input conditions *

bcd <= "00" after 5 ns, "01" after 15 ns, "10" after 25 ns, "11" Has test results for UUT after 35 ns; assert bcd = "00" and led = * "001" or bcd = "01" and led = "0010" Generates error message or bcd = "10" and led = "0100" or bcd = "11" and led = "1000" Sets severity level report "There is an incorrect led value." severity error; end bcd_test;

NAND Gate

Test Bench

Test Gate

library ieee; use ieee.std_logic_1164.all; use work.mygates.all; entity testnand is end testnand; architecture testgate of testnand is component my_nand is port ( A, B : in std_logic; Y : out std_logic ); end component; signal A, B, Y : std_logic; begin UUT : my_nand port map ( A, B, Y );

process constant period : time := 40 ns; begin A <= '1'; B <= '1'; wait for period; assert ( Y = '0' ) report "Test 11 failed." severity error; A <= '1'; B <= '0'; wait for period; assert ( Y = '1' ) report "Test 10 failed." severity error; A <= '0'; B <= '1'; wait for period; assert ( Y = '1' ) report "Test 01 failed." severity error; A <= '0'; B <= '0'; wait for period; assert ( Y = '1' ) report "Test 00 failed." severity error; wait; end process; end testgate;

Configuration Declaration

Notes
1. Specifies which architecture is bound to an entity - default is last architecture block 2. Allows for changes in how components are connected during simulation 3. Uses existing libraries for components
4.

Example

Use WORK for current library

Syntax: FOR entity_name component_name USE library.entity(architecture); all is used as an entity_name for multiple instances of a component.

FOR all AND2 USE my_gates.my_and(and_gate);

Configuration Block

Syntax

Example

library cmos_lib; library my_lib; configuration fulladd_con of configuration full_adder is config_name of for fulladd_struct use work.all; entity_name is for and1, and2, and3 : my_and for architecture_name use library; use entity for component_name : c_mos_lib.bigand2(and2str); component end for; use entity for others : or2; entity_name( architecture end for; _name ); for all : xor2 end for; use configuration end for; work.my_xor; end config_name; end for; end for; end fulladd_con;

Verilog Versus VHDL

Item
Case Typing Interface Signals Comments Format Interface Declaration Interconnecting lines Subprograms Constants

VHDL
does not care strong std_logic std_logic_vector -Entity Architecture entity port signal function procedure generic constant start with alpha alpha, numeric, underscore name : char := "string"; weak

Verilog
sensitive net, register vector // /* */ Module module port list input and output wire reg function procedure parameter defparam start with alpha or underscore alpha, numeric, underscore, dollar sign type [size*range] name; name = "string";

Identifiers

String Data Type

Verilog Versus VHDL

Item
Statements end with ; Basic <= assignment := Instantiation Logic Levels Libraries Binary Constants Vectors

VHDL

Verilog
end with ; or end assign = refName instName (port list); 1, 0, x, z 'include 8'b00110111 reg [msb : lsb] wire [msb : lsb] reg name[n1 : n2]; wire[n1 : n2] single demension only

requires component compName port map(list); 1, 0, X, Z, -, U H, L, W library use '1' "00110111" 2#00110111 std_logic_vector(num1 downto/to num2) type a-name is array (range) of type; unlimited demensions

Arrays