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CORDIC v3.0
DS249 April 28, 2005
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Product Specification

Features
Available for Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Spartan-II, Spartan-IIE, Spartan-3, and Spartan-3E FPGAs Functional configurations - Vector rotation (polar to rectangular) - Vector translation (rectangular to polar) - Sin and Cos - Sinh and Cosh - Atan and Atanh - Square root Optional coarse rotation module to extend the range of CORDIC from the first quadrant (+Pi/4 to - Pi/4 Radians) to the full circle Optional amplitude compensation scaling module to compensate for CORDIC algorithms output amplitude scale factor Output rounding modes: Truncation, Round to Pos Infinity, Round to Pos/Neg Infinity, and Round to Nearest Even
Figure Top x-ref 1

Word serial architectural configuration for small area Parallel architectural configuration for high throughput Control of the internal add-sub precision Control of the number of add-sub iterations Optional input and output registers Optional control signals: CE, ND, ACLR, SCLR, RFD, and RDY X and Y data formats: Signed Fraction, Unsigned Fraction, and Unsigned Integer Phase data formats: Radian, Pi Radian Fully optimized for speed and area Fully synchronous design using a single clock Incorporates Xilinx Smart-IP technology for maximum performance To be used with v7.1i and later of the Xilinx CORE Generator system

Input Stage
I n p u t R e g C o a r s e R o t I n p u t F m t

CORDIC Engine
Shift Add-Sub Stages

Output Stage
O u t p u t R n d C o a r s e R o t O u t p u t R e g
RDY

X_IN

X_OUT Y_OUT P_OUT

Y_IN
P_IN

CLK

CE

ND ACLR SCLR
CONTROL LOGIC

RFD

Figure 1: The CORDIC Core

2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

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CORDIC v3.0

Functional Description
The CORDIC core implements a generalized coordinate rotational digital computer (CORDIC) algorithm, initially developed by Volder[1] to iteratively solve trigonometric equations, and later generalized by Walther[2] to solve a broader range of equations, including the hyperbolic and square root equations. The CORDIC core implements the following equation types: Rectangular <-> Polar Conversion Trigonometric Hyperbolic Square Root Two architectural configurations are available for the CORDIC core: A fully parallel configuration with single-cycle data throughput at the expense of silicon area A word serial implementation with multiple-cycle throughput but occupying a small silicon area A coarse rotation is performed to rotate the input sample from the full circle into the first quadrant. (The coarse rotation stage is required as the CORDIC algorithm is only valid over the first quadrant). An inverse coarse rotation stage rotates the output sample into the correct quadrant. The CORDIC algorithm introduces a scale factor to the amplitude of the result, and the CORDIC core provides the option of automatically compensating for the CORDIC scale factor.

The CORDIC Algorithm

The CORDIC algorithm was initially designed to perform a vector rotation, where the vector (X,Y) is rotated through the angle yielding a new vector (X,Y). Equation 1: Vector Rotation Equation 1a) 1b) 1c)
X' = ( cos ( ) X sin ( ) Y ) Y' = ( cos ( ) Y + sin ( ) X ) ' = 0

The CORDIC algorithm performs a vector rotation as a sequence of successively smaller rotations, each of angle atan(2-i), known as micro-rotations. Equation 2: Vector rotation expressed as a series of n micro-rotations.
n

2a)

X' =

cos ( atan ( 2i ) ) ( Xi i Yi 2
i=1 n

2b)

Y' =

cos ( atan ( 2 i ) ) ( Yi + i Xi 2
i=1

2c)

' =

( i
i=1

atan ( 2 ) )

i = (+ or -) 1.

See Vector Rotation or Vector Translation for details on selecting i .

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CORDIC v3.0

Each micro-rotation stage can be expressed as a simple shift_addsub operation. Equation 3: Expression for the ith microrotation. 3a) 3b) 3c)
x i + 1 = x i i y i 2 i y i + 1 = y i + i x i 2 i i + 1 = i + i atan ( 2 i ) ) i = (+ or -) 1

The CORDIC algorithm can be used to generate either a vector rotation or a vector translation. Vector Rotation Vector rotation rotates the vector (X, Y) through the angle to yield a new vector (X,Y), as illustrated in Figure 3. Vector rotation is performed by selecting i , such that ' converges towards zero. I.e., when i 1 >= 0, i is set to -1 and when i 1 < 0, i is set +1. Equation 4: Vector Rotation Equations 4a) 4b) 4c)
X = Zi ( cos ( ) X sin ( ) Y ) Y = Zi ( cos ( ) Y + sin ( ) X ) ' = 0

1 -----------------------------------------------Zi =
i=1

acos ( atan ( 2 i ) )

Vector Translation Vector translation rotates the vector (X,Y) around the circle until the Y component equals zero as illustrated in Figure 5. The outputs from vector translation are the magnitude, X, and phase, ' , of the input vector (X,Y). Vector translation is performed by selecting i such that Y converges towards zero. I.e., when Yi-1 >= 0, i is set to -1 and when Yi-1 < 0, i is set +1. Equation 5: Vector Translation Equations 5a) 5b) 5c)
X = Z i Y' = 0 ' = atan ( X Y ) (X + Y )
2 2

1 -----------------------------------------------Zi =
i=1

acos ( atan ( 2 i ) )

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CORDIC v3.0

The CORDIC Scale Factor The outputs of the CORDIC algorithm, equations 4 and 5, are equivalent to a vector rotation or vector translation scaled by a constant Zi. The constant Zi is known as the CORDIC scale factor. Equation 6: The CORDIC Scale Factor 6a)
Zi = 1 ------------------------------------------------

acos ( atan ( 2 i ) )
i=1

The Taylor series expansion of acos (atan (2-i ) ) is (1 + 2-2i)-1/2. Hence, the constant Zi can be expressed as 6b)
Zi =

( 1 + 2 2i ) 1
i=1

The CORDIC scale factor, Zi, is only dependent on the number of iterations, n. Only functional configurations: Rotate, Translate, Rectangular to Polar, and Polar to Rectangular are affected by the CORDIC scale factor. When these functional configurations are selected, the CORDIC core provides the option of multiplying by 1 / Zi to cancel out the scaling factor. See Compensation Scaling for detailed information. Output Quantization Error The Output Quantization Error can be split into two components; the Output Quantization Error due to the Input Quantization (OQEIQ) and the Output Quantization Error due to Internal Precision (OQEIP). OQEIQ is due to the 1/2 lsb of quantization noise on the X,Y and Phase inputs. In a vector rotation this input quantization noise results in OQEIQ of 1/2 an lsb on both the X and Y outputs. In a vector translation this input quantization noise results in OQEIQ of 1/2 an lsb on the X output however OQEIQ on the phase output is dependant on the ratio (Y/ X). Thus for small X inputs the effect of input quantization noise on OQEIQ is greatly magnified. OQEIP is due to the limited precision of internal calculations. In the CORDIC core the default internal precision is set such that the accumulated OQEIP is less than 1/2 the OQEIQ. The internal precision can be manually set to (input width + output width + log2(output_width)). This will reduce OQEIP to 1/2 an lsb (i.e. the phase will be calculated to full precision regardless of the magnitude input vector). The Output Quantization Error, for a CORDIC core with default internal precision, is dominated by OQEIQ. OQEIQ can only be reduced by increasing the number of significant magnitude bits in the input vector (X,Y). Increasing the internal precision or zero padding X and Y inputs only affects OQEIP and will have minimal effect on the total output quantization error. The effect of input quantization and internal quantization on the CORDIC phase output quantization error is illustrated in the following examples. Example 1a: The quantization error in phase output for a small input vector, (Xin_small, Yin_small). Xin_small : 0000000001 => 1/256. Yin_small : 0000000001 => 1/256. Vector translation with no input quantization:

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CORDIC v3.0

Xin_ideal : 0000000001 => 1/256. Yin_ideal : 0000000001 => 1/256. Pout_ideal : 0001100100 => 0.79. Output quantization error due to the input quantization: Xin_Quant = X_in - 1/2 lsb and Yin_Quant = Yin + 1/2 lsb. Xin_Quant : 00000000001 => 1/512. Yin_Quant : 00000000011 => 3/512. Pout_Quant : 0010100000 =>1.25. OQEIQ = abs( abs(Pout_Quant) - abs(Pout_Ideal) ). OQEIQ = "0000111100" => 0.47. Output quantization error due to the internal precision: Xin_cordic : 0000000001 => 1/256. Yin_cordic : 0000000001 => 1/256. Pout_cordic : 0001111010 => 0.95. OQEIP = abs( abs(Pout_cordic) - abs(Pout_Ideal) ). OQEIP = "0000010110" => 0.17. Example 1b: Quantization error in phase output for a large input vector, (Xin_large, Yin_large). Xin_large : 0100000000 => 256/256. Yin_large : 0100000000 => 256/256. Vector translation with no input quantization: Xin_ideal : 0100000000 => 256/256. Yin_ideal : 0100000000 => 256/256. Pout_ideal : 0001100100 => 0.79. Output quantization error due to the input quantization: Xin_Quant = X_in - 1/2 lsb and Yin_Quant = Yin + 1/2 lsb. Xin_Quant : 00111111111 => 511/512. Yin_Quant : 01000000001 => 513/512. Pout_Quant : 0001100101 =>0.79. OQEIQ = abs( abs(Pout_Quant) - abs(Pout_Ideal) ). OQEIQ = "0000000001" => 0.00. Output quantization error due to the internal precision: Xin_cordic : 0100000000 => 256/256. Yin_cordic : 0100000000 => 256/256.

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CORDIC v3.0

Pout_cordic : 0001100100 => 0.79. OQEIP = abs( abs(Pout_cordic) - abs(Pout_Ideal) ). OQEIP = "0000000000" => 0.00.

CORDIC Graphical User Interface (GUI)

The CORDIC Graphical User Interface (GUI) contains four screens for configuring the core: Screen 1 (Figure 2): Used to configure the functional selection and architecture of the CORDIC core. Screen 2 (Figure 10): Used to configure the phase and magnitude data formats, optional control signals, and synchronization. Screen 3 (Figure 11): Provides options for configuring the rounding mode and input-outputs. Screen 4 (Figure 12): Provides options for advanced configuration parameters: Coarse Rotation, Iterations, internal Precision, and Compensation Scaling. In addition, the fourth screen displays the latency and controls the inclusion of placement information.

GUI Options
All of the GUI screens display the following selections: Next and Back: moves forward or backward one screen at a time, respectively. Generate: generates the CORDIC core with the currently configured parameters. Dismiss: cancels generation of the CORDIC and returns to the first screen of the GUI. Datasheet: displays a PDF document of the CORDIC data sheet. Version Info: displays a popup window with new features and bug fixes for CORDIC v3.0. Display Core Footprint: when selected, the Footprint View window appears when the core is generated and displays a graphical representation of the placement of the generated core. Note that if Create RPM is deselected, the window is empty.

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DS249 April 28, 2005 Product Specification

CORDIC v3.0

CORDIC GUI: Screen 1

Figure Top x-ref 2

Figure 2: CORDIC Configuration GUI: Screen 1

Component Name
Used as the base name of the output files generated for the core. Names must begin with a letter and be composed from the following characters: a to z, 0 to 9, and _.

Functional Selection
The CORDIC core can be used in a variety of functional configurations. All functional configurations are exclusive and each lists the input/output ports and the range of valid data. The following functional selections are available: Rotate Sin and Cos Arc Tan Square Root Translate Sinh and Cos Arc Tanh In general, X_IN, Y_IN, X_OUT and Y_OUT express signed binary numbers of 1QN format and PHASE_IN and PHASE_OUT express signed binary numbers of 2QN format. When Square Root is selected, two new data formats are available: Unsigned Integer and Unsigned Fraction. For details about CORDIC binary data formats see Input/Output Data Representation.

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CORDIC v3.0

Vector Rotation
Polar to Rectangular Translation When the vector rotation functional configuration is selected the input vector, (X, Y), is rotated by the input angle, , using the CORDIC algorithm. This generates the scaled output vector, Zi * (X, Y), as shown in Figure 3. The inputs, X_IN, Y_IN and PHASE_IN, are limited to the ranges given in Table 1. Inputs outside these ranges will produce unpredictable results. See Input/Output Data Representation for detailed information regarding CORDIC binary data formats. An optional coarse rotation module is provided to extend the range of the inputs, X, Y and Phase, to the full circle. For this functional configuration the coarse rotation module is selected by default but can be manually deselected by the user. See Coarse Rotation for detailed information. An optional compensation scaling module is provided to compensate for the CORDIC scale factor Zi. For this functional configuration the compensation scaling module is selected by default but can be manually deselected by the user. See Compensation Scaling for detailed information. A Polar to Rectangular Translation can be implemented by setting the functional configuration to vector rotation, the input vector to (Mag, 0), and the rotation angle to , as shown in Figure 4. Vector rotation is linear with respect to magnitude, thus the user can scale the input/output range, that is: If (X, Y) rotated by angle = (X, Y) then K*(X, Y) rotated by angle = K*(X, Y).

Figure Top x-ref 3

Y Zi.(X,Y) Output Vector (X,Y) (X,Y) Input Vector X

Figure 3: Vector Rotation

Figure Top x-ref 4

Y Zi.(X,Y) Output Vector (X,Y) X (X, 0) Input Vector

Figure 4: Polar to Rectangular Conversion

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DS249 April 28, 2005 Product Specification

CORDIC v3.0

Table 1: Vector Rotation I/O

Signal
X_IN Input X Coordinate Range: -1 <= X_IN<=1 Input Y Coordinate Range: -1 <= Y_IN<=1 Input Rotation Angle

Description

Y_IN

PHASE_IN

Range: -Pi <= PHASE_IN <= Pi Output X Coordinate * Z Range: -Sqrt2 <= X_OUT<= Sqrt2 Output Y Coordinate * Z Range: -Sqrt2 <= Y_OUT<= Sqrt2

X_OUT

Y_OUT

Example 1: Vector Rotation The input vector, (Xin, Yin), is expressed as a pair of signed 1QN format numbers. The input rotation angle, Pin radians, is expressed as a signed 2QN number. The output vector, (Xout, Yout), is expressed as a pair of signed 1QN format numbers. In this example, the input/output width is set to 10 bits and the output vector (Xout, Yout) is scaled to compensate for the CORDIC scale factor. Xin : 0010110101 => 00.10110101 => 0.707 Yin : 0001000000 => 00.01000000 => 0.25 Pin : 1100110111 => 110.0110111 => -Pi/2 Xout : 0001000001 => 00.01000001 => 0.25 Yout : 1101001011 => 11.01001011 => -0.707

Vector Translation
Rectangular to Polar Translation When the vector translational functional configuration is selected, the input vector (X,Y) is rotated using the CORDIC algorithm until the Y component is zero. This generates the scaled output magnitude, Zi * Mag(X,Y), and the output phase, Atan(Y/X), as shown in Figure 5. The inputs, X_IN and Y_IN, are limited to the ranges given in Table 2. Inputs outside these ranges will produce unpredictable results. See Input/Output Data Representation for detailed information regarding CORDIC binary data formats. An optional coarse rotation module is provided to extend the range of inputs, X and Y, to the full circle. For this functional configuration the coarse rotation module is selected by default but can be manually deselected by the user. See Coarse Rotation for detailed information. An optional compensation scaling module is provided to compensate for the CORDIC scale factor Zi. For this functional configuration the compensation scaling module is selected by default but can be manually deselected by the user. See Compensation Scaling for detailed information. A rectangular to polar translation can be implemented by setting functional configuration to vector translation, and the input vector to (X,Y), as shown in Figure 5.

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CORDIC v3.0

Vector translation is linear with respect to magnitude, thus the user can scale the input/output range; that is: If vector (X, Y) is translated to (X, ), then vector K*(X, Y) is translated to K*(X, ). The phase angle of a zero length vector, (0,0), is indeterminate and the output phase angle generated by the core will be unpredictable. The accuracy of the phase output from the CORDIC vector translation algorithm is limited by the number of significant magnitude bits of the input vector (X, Y). See Output Quantization Error for detailed information.
Figure Top x-ref 5

Y (X,Y) Input Vector

Output Phase Zi.(Mag,0) Output Mag X (Mag,0)

Figure 5: Vector Translation (Polar to Rectangular) Table 2: Vector Translation I/O

Signal
X_IN Input X Coordinate Range: -1 <= X_IN <= 1 Input Y Coordinate Range: -1 <= Y_IN <= 1 Output Magnitude * Z

Description

Y_IN

X_OUT

Range: 0 <= X_OUT <= Sqrt2 Output Phase Range: -Pi <= Phase Out <= Pi

PHASE_OUT

Example 2: Vector Translation The input vector, (Xin, Yin), is expressed as a pair of signed 1QN format numbers. The output magnitude, Xout, is expressed as a signed 1QN format number. The output phase angle, Pout radians, is expressed as a signed 2QN number. In this example the input/output width is set to 10 bits and the output Xout is scaled to compensate for the CORDIC scale factor. Xin : 0010110101 => 00.10110101 => 0.707 Yin : 0001000000 => 00.01000000 => 0.25 Xout : 0011000000 => 00.11000000 => 0.75 Pout : 0000101011 => 000.0101011 => 0.336

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CORDIC v3.0

Sin and Cos

When the Sin Cos functional configuration is selected, the unit vector is rotated, using the CORDIC algorithm, by input angle, . This generates the output vector (Cos( ), Sin( )). The input, PHASE_IN, is limited to range given in Table 3. Inputs outside this range will produce unpredictable results. See Input/Output Data Representation for detailed information regarding CORDIC binary data formats. An optional coarse rotation module is provided to extend the range of input angle, , to the full circle. For this functional configuration the coarse rotation module is selected by default but can be manually deselected by the user. See Coarse Rotation for detailed information. The compensation scaling module is disabled for the Sin and Cos functional configuration as it is internally prescaled to compensate for the CORDIC scale factor.
Table 3: Sin and Cos

Signal
PHASE_IN Input Angle

Description
Range: -Pi <= PHASE_IN <= Pi Output Cos( ) Range: -1 <= X_OUT <= 1 Output Sin( ) Range: -1 <= Y_OUT <= 1

X_OUT

Y_OUT

Example 3: Sin and Cos The input angle, Pin, is expressed as a signed 2QN number. The output vector, (Xout, Yout), is expressed as a pair of signed 1QN numbers. In this example the input/output width is set to 10 bits. Pin: 0001100100 => 000.1100100 => 0.781 Xout : 0010110110 => 00.10110110 => 0.711 Yout : 0010110100 => 00.10110100 => 0.703

Sinh and Cosh

When the SinhCosh functional configuration is selected, the CORDIC algorithm is used to move the vector (1,0) through hyperbolic angle, p, along the hyperbolic curve as shown in Figure 6. The hyperbolic angle represents the log of the area under the vector (X, Y) and is unrelated to a trigonometric angle. This generates the output vector (Cosh(p), Sinh(p)). The input hyperbolic angle, PHASE_IN, is limited to range given in Table 4. Inputs outside this range will produce unpredictable results. See Input/Output Data Representation for detailed information regarding CORDIC binary data formats. The coarse rotation module is disabled for the Sinh and Cosh functional configuration, as it does not apply to hyperbolic transformations.

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CORDIC v3.0

The compensation scaling module is disabled for the Sinh and Cosh functional configuration, as it is internally prescaled to compensate the CORDIC hyperbolic scale factor.
Figure Top x-ref 6

Y Output Vector (Sinh, Cosh) Hyperbolic Angle (PHASE_IN) p X Input Vector(X_IN,0) Hyperbolic Curve

Figure 6: Hyperbolic Sinh Cosh Table 4: Sinh and Cosh

Signal
PHASE_IN Input Hyperbolic Angle

Description
Range: -Pi/4 <= PHASE_IN <= Pi/4 Output Cosh Range: 1 =< X_OUT < 2 Output Sinh Range: -2 <= Y_OUT < 2

X_OUT

Y_OUT

Example 4: Sinh and Cosh The input hyperbolic angle, Pin, is expressed as a signed 2QN number. The output vector, (Xout, Yout), is expressed as a pair of signed 1QN Numbers. In this example the input/output width is set to 10 bits. Pin : 0001001110 => 000.1001110 => 0.781 Xout : 0100110001 => 01.00110001 => 1.191 Yout : 0010100110 => 00.10100110 => 0.648

ArcTan
When the Arc Tan functional configuration is selected, the input vector (X,Y) is rotated (using the CORDIC algorithm) until the Y component is zero. This generates the output angle, Atan(Y/X). The inputs, X_IN and Y_IN, are limited to the ranges given in Table 5. Inputs outside these ranges will produce unpredictable outputs. See Input/Output Data Representation for detailed information regarding CORDIC binary data formats. An optional coarse rotation module is provided to extend the range of inputs X and Y to the full circle. For this functional configuration the coarse rotation module is selected by default but can be manually deselected by the user. See Coarse Rotation for detailed information. The compensation scaling module is disabled for the Arc Tan functional configuration as no magnitude data is output. The ArcTan of a zero length vector, (0,0), is indeterminate and the output angle generated by the core will be unpredictable.

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DS249 April 28, 2005 Product Specification

CORDIC v3.0

The accuracy of the output angle from CORDIC vector translation algorithm is limited by the number of significant magnitude bits of the input vector (X, Y). See Output Quantization Error for detailed information.
Table 5: ArcTan

Signal
X_IN Input X Coordinate Range: -1 <= X_IN <=1 Input Y Coordinate Range: -1 <= Y_IN <=1 Output Angle

Description

Y_IN

PHASE_OUT

Range: -Pi <= Phase Out <= Pi

Example 5: Arc Tan The input vector (Xin, Yin) is expressed as a pair of signed 1QN numbers. The output angle, Pout radians, is expressed as a signed 2QN number. In this example, the input/output width is set to 10 bits. Xin : 0010100000 => 00.10100000 => 0.625 Yin : 0010000000 => 00.10000000 => 0.500 Pout : 0001010110 => 000.1010110=> 0.672

ArcTanh
When the ArcTanh functional configuration is selected, the CORDIC algorithm is used to move the input vector (X,Y) along the hyperbolic curve (Figure 7) until the Y component reaches zero. This generates the hyperbolic angle, Atanh(Y/X). The hyperbolic angle represents the log of the area under the vector (X,Y) and is unrelated to a trigonometric angle. The inputs, X_IN and Y_IN, are limited to the ranges given in Table 6. Inputs outside these ranges will produce unpredictable outputs. Additionally, Y_IN must be less than or equal to (4/5 * X_IN) or the CORDIC algorithm will not converge. See Input/Output Data Representation for detailed information about CORDIC binary data formats. The coarse rotation module is disabled for the Arc Tanh functional configuration, as it does not apply to hyperbolic transformations.

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CORDIC v3.0

The compensation scaling module is disabled for the Arc Tanh functional configuration as no output magnitude data is output.
Figure Top x-ref 7

Y Input Vector (Xin, Yin) Hyperbolic Angle (Phase_out) p X Internal Vector(Xout,0) Hyperbolic Curve

Figure 7: Hyperbolic ArcTanh Table 6: ArcTanh

Signal
X_IN Input X Coordinate Range: 0 < X_IN <2

Description

Y_IN

Input Y Coordinate Range: -2 <= Y_IN <= 2 -X_IN * 4/5 <= Y_IN <= X_IN * 4/5 Output Hyperbolic Angle Range: -Pi/2 <= Phase Out <= Pi/2

PHASE_OUT

Example 6: Arc Tanh The input vector, (Xin, Yin), is expressed as a pair of signed 1QN numbers. The output, Pout, is expressed as a signed 2QN number. In this example, the input/output width is set to 10 bits. Xin : 0001100101 => 00.01100101 => 0.395 Yin : 0001100101 => 00.01100101 => 0.395 Pout : 0001110001 => 000.1110001=> 0.883

Square Root
When the square root functional configuration is selected a simplified CORDIC algorithm is used to calculate the positive square root of the input. The input, X_IN, and the output, X_OUT, are always positive and are both expressed as either, unsigned fractions or unsigned integers. When data format is set to Unsigned Fraction, X_IN is limited to the range: 0 <= X_IN < +2. When data format is set to Unsigned Integer, X_IN is limited to the range: 0 <= X_IN < 2**Input Width, and the output width is determined automatically based on the input width. See Input/Output Data Representation for detailed information regarding CORDIC binary data formats. The coarse rotation module is disabled because coarse rotation is not required for the Square Root functional configuration.

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CORDIC v3.0

The compensation scaling module is disabled because no output compensation is required for the Square Root functional configuration.
Table 7: Square Root

Signal
X_IN Input X Value Range: 0 <= X_IN Output Square Root Range: 0 <= X_OUT

Description

X_OUT

Example 7a: Square Root - Unsigned Fraction The input, Xin, is expressed as an unsigned 1QN format fraction. The output, Xout, is expressed as an unsigned 1QN format fraction. In this example the input/output width is set to 10 bits. Xin : 0000100000 => 0.000100000 => 1/16 Xout : 0010000000 => 0.010000000 => 1/4 Example 7b: Square Root - Unsigned Integer The input, Xin, is expressed as an unsigned integer. The output, Xout, is expressed as an unsigned integer. In this example the input width is set to 10 bits so the output width is automatically set to 6 bits. Xin : 0000100000 => 32 Xout :000110 => 6

Architectural Configuration
Two architectural configurations are available for the CORDIC core: Parallel, with single-cycle data throughput and large silicon area, and Word Serial, with multiple-cycle throughput and a smaller silicon area.

Word Serial Architectural Configuration

The CORDIC algorithm requires approximately one shift-addsub operation for each bit of accuracy. A CORDIC core implemented with the word serial architectural configuration, implements these shift-addsub operations serially, using a single shift-addsub stage and feeding back the output. A word serial CORDIC core with N bit output width has a latency of N cycles and produces a new output every N cycles. The implementation size of a word serial CORDIC core is directly proportional to the internal precision.

Parallel Architectural Configuration

The CORDIC algorithm requires approximately one shift-addsub operation for each bit of accuracy. A CORDIC core with a parallel architectural configuration implements these shift-addsub operations in parallel using an array of shift-addsub stages. A parallel CORDIC core with N bit output width has a latency of N cycles and produces a new output every cycle. The implementation size of a parallel CORDIC core is directly proportional to the internal precision times the number of iterations.

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CORDIC v3.0

Figure Top x-ref 8

X_Feedback X_IN X_IN Y_Feedback Y_IN Y_IN P_Feedback PHASE_IN P_IN Shift AddSub Stage P_OUT PHASE_OUT Y_OUT Y_OUT X_OUT X_OUT

Figure 8: Word Serial Architectural Configuration

Figure Top x-ref 9

X_IN

X_OUT

Y_IN PHASE_IN

Y_OUT PHASE_OUT

CONSTANT N Shift Addsub Stages

Figure 9: Parallel Architectural Configuration

Pipelining Mode
The CORDIC core provides three pipelining modes: None, Optimal, and Maximum. The choice of pipelining mode is based on the selection of Functional Configuration and Architectural Configuration. Unavailable pipelining modes are greyed out in the GUI. None: the CORDIC core is implemented without pipelining. Optimal: the CORDIC core is implemented with as many stages of pipelining as possible without using any additional LUTs. Maximum: the CORDIC core is implemented with a pipeline after every shift-add sub stage.

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CORDIC v3.0

CORDIC GUI: Screen 2

Figure Top x-ref 10

Figure 10: CORDIC GUI: Screen 2

Data Format
The CORDIC core provides three formats for expressing the X and Y components of data samples: Signed Fraction: Default setting. The X and Y inputs and outputs express signed fractions of Q1 format. Example: 11100000 represents the value -0.5. Unsigned Fraction: The X and Y inputs and outputs express unsigned fractions of Q1 format. Available only for Square Root functional configuration. Example: 11100000 represents the value +1.75. Unsigned Integer: The X and Y inputs and outputs express unsigned integers. Available only for Square Root functional configuration. Example: 11100000 represents the value +224.

Phase Format
The CORDIC core provides two Phase Format options: Radians: the phase is expressed as signed fractions of Q2 format in radian units. Example: 01100000 represents the value 3.0 radians. Scaled Radians: the phase is expressed as signed fractions of Q2 format with pi-radian units. One scaled-radian equals Pi * 1 radians. Example: 11110000 represents the value -0.5 * Pi radians. See Input/Output Data Representation for detailed information about CORDIC binary data formats.

Synchronization Enable
The Sync Enable parameter has two states: Override: when CE overrides the SCLR signal, SCLR is ignored while CE is deasserted.

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No Override: default setting, resulting in a more efficient implementation.

Optional Pin Selection

Control Signals: ND, RDY, ACLR, SCLR, and CE control signals are optional. Note: The presence of the CLK and RFD control signals are determined based on the selected Architectural Configuration, Pipelining Mode, Register Inputs, and Register Outputs. Output Signals: X_OUT, Y_OUT and PHASE_OUT are optional. The default states of these signals are determined based on the selected functional configuration but can be manually overridden by the user.

CORDIC GUI: Screen 3

Figure Top x-ref 11

Figure 11: CORDIC GUI: Screen 3

Round Mode
The CORDIC core provides four rounding modes: Truncate: The X_OUT, Y_OUT, and PHASE_OUT outputs are truncated. Positive Infinity: The X_OUT, Y_OUT, and PHASE_OUT outputs are rounded (1/2 rounded up). Pos Neg Infinity: The outputs X_OUT, Y_OUT, and PHASE_OUT are rounded (1/2 rounded up, -1/2 rounded down). Nearest Even: The X_OUT, Y_OUT, and PHASE_OUT outputs are rounded toward the nearest even number (1/2 rounded down and 3/2 is rounded up).

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Table 8: Rounding Modes

Truncate
1.50 1.00 0.50 0.25 0.00 - 0.25 - 0.50 - 0.75 1 1 0 0 0 -1 -1 -1

Round+/2 1 1 0 0 0 -1 -1

Round +
2 1 1 0 0 0 0 -1

Even
2 1 0 0 0 0 -1 -1

Input / Output Common Configuration Options

The CORDIC core provides four input / output common configuration options: Register Inputs: input signals X_IN, Y_IN, PHASE_IN and ND are registered. Register Outputs: output signals, X_OUT, Y_OUT, PHASE_OUT, RFD and RDY are registered. Input Width: input Width controls the widths of the input ports, X_IN, Y_IN and PHASE_IN. The Input Width can be configured in the range 8 to 48 bits. Output Width: output Width controls the widths of the output ports, X_OUT, Y_OUT, PHASE_OUT. The Output Width can be configured in the range 8 to 48 bits.

Advanced Configuration Parameters

Figure Top x-ref 12

Figure 12: CORDIC GUI: Screen 4

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Iterations Controls the number of internal add-sub iterations to perform.When Iterations is set to zero, the number of iterations performed is determined by the required accuracy of the output. By default, Iterations is set to zero, thus the number of iterations is automatically determined. Precision: Configures the internal precision of the internal add-sub iterations. When Precision is set to zero, internal precision is determined automatically based on the required accuracy of the output and the number of internal iterations. By default, Precision is set to zero, thus the internal precision is automatically determined. When Precision is set to (input width + output width + logbase2(output_width)) the output phase is precise to the full output width regardless of input magnitude. However, the output phase accuracy is still limited by the OQEIQ component of Output Quantization Error and by the number of Iterations of the Cordic Micro-Rotation block. Coarse Rotation: Controls the instantiation of the coarse rotation module. Instantiation of the coarse rotation module is the default for the following functional configurations: Vector rotation, Vector translation, Sin and Cos, and Arc Tan. If Coarse Rotation is turned off for these functions then the input/output range is limited to the first quadrant (-Pi/4 to + Pi/4). Coarse rotation is not required for the Sinh and Cosh, Arctanh, and Square Root configurations. The standard CORDIC algorithm operates over the first quadrant. Coarse Rotation extends the CORDIC operational range to the full circle by rotating the input sample into the first quadrant and inverse rotating the output sample back into the appropriate quadrant. Compensation Scaling Controls the compensation scaling module used to compensate for CORDIC magnitude scaling. CORDIC magnitude scaling affects the Vector Rotation and Vector Translation functional configurations, and does not affect the SinCos, SinhCosh, ArcTan, ArcTanh and Square Root functional configurations. For the latter configurations, compensation scaling is set to No Scale Compensation. CORDIC magnitude scaling is a side effect of the CORDIC algorithm. The magnitude outputs, X and Y, are generated scaled by the CORDIC scale factor, ZI. The compensation scaling module compensates for the effect of CORDIC magnitude scaling by scaling the outputs, X and Y, by 1/ZI. - No Scale Compensation: The outputs X and Y will not be compensated and will be generated scaled by the ratio ZI. - CCM Scale Compensation: The outputs X and Y are compensated using a LUT-based Constant Coefficient Multiplier. - Block Multiplier: The outputs X and Y are compensated using the built-in Block Multiplier. Note that Block Multiplier mode is only available when the projects target architecture has built-in multipliers.

Layout
Create RPM: The core is generated with relative location attributes attached. Note that when a core is created as an RPM (relationally placed macro) it is possible that one or more of the core dimensions may exceed those of the device being targeted. When this happens, mapping errors occur and the compilation process fails. To correct the situation, deselect Create RPM and regenerate the core.

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Design Feedback
Latency: Reports the latency of the design with the currently selected parameters. Latency is defined as the number of clock cycles between the input being sampled and the corresponding sample appearing on the outputs.

Physical Description
Pinout
Table 9: Core Pinout

Port Name
X_IN Y_IN PHASE_IN X_OUT Y_OUT PHASE_OUT ND RFD RDY CLK CE ACLR SCLR

Port Width
Input_Width Input_Width Input_Width Output_Width Output_Width Output_Width 1 1 1 1 1 1 1

Direction
IN IN IN OUT OUT OUT IN OUT OUT IN IN IN IN

Has Pin
Dependent Dependent Dependent Optional Optional Optional Dependent Dependent Dependent Dependent Optional Optional Optional

Description
X component of input sample Y component of input sample Phase component of input sample X component of output sample Y component of output sample Phase component of output sample New sample on input ports Ready for new data sample New output data is ready Clock Clock enable Asynchronous clear Synchronous clear

CORDIC Data Inputs

X_IN, Y_IN and PHASE_IN are the data input ports for the CORDIC Core. All data input ports are read simultaneously to form a single input sample. The width of the data input ports is configured using the parameter Input Width. The data input ports are optionally registered. The set of data input ports required for a particular Functional Configuration are automatically determined by the GUI as shown in Table 10. X_IN Data Input Bus: Contains the X component of the input data sample. Y_IN Data Input Bus. Contains the Y component of the input data sample. PHASE_IN Data Input Bus. Contains the phase component of the input data sample.
CORDIC Data Outputs

X_OUT, Y_OUT and PHASE_OUT are the data output ports for the CORDIC core. The default settings for data output ports required for a particular Functional Configuration are automatically determined by the GUI as shown in Table 10, but may be modified from the default settings by the user. The width of the CORDIC data output ports is set using the parameter Output Width. The data output ports are optionally registered.

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X_OUT Data Output Bus: Contains the X component of the output data sample. Y_OUT Data Output Bus: Contains the Y component of the output data sample. PHASE_OUT Data Output Bus: Contains the Phase component of the output data sample.

Table 10: Input/Output Pins vs. Functional Configuration

XIN
Rotate Translate Sin Cos Arc Tan Sinh Cosh Arc Tanh Sq. Root 1 1 0 1 0 1 1

YIN
1 1 0 1 0 1 0

PIN
1 0 1 0 1 0 0

XOUT
1 1 1 0 1 0 1

YOUT
1 0 1 0 1 0 0

POUT
0 1 0 1 0 1 0

Input/Output Data Representation

Data Signals The Data Signals are: X_IN, Y_IN, X_OUT and Y_OUT. For Functional Configurations, Rotate, Translate, Sin Cos and Atan the Data Signals are represented in 1QN Format. Input data signals, X_IN and Y_IN, must be in the range: -1 <= input data signal <= 1. Input data outside this range will produce unpredictable results. In 1Q10 format values, +1 and -1, are represented: "0100000000" => 01.00000000 => +1.0 "1100000000" => 11.00000000 => - 1.0 For Functional Configuration, Square Root, the Data Signals, X_IN and X_OUT, are both represented in either Unsigned Fractional or Unsigned Integer data format. Phase Signals The Phase Signals are: PHASE_IN and PHASE_OUT. The phase signals are always represented in 2QN format. When Phase Format is set to Radians, PHASE_IN must be in the range: -Pi <= (PHASE_IN) <= Pi. PHASE_IN outside this range will produce unpredictable results. In 2Q10 format values, +Pi and -Pi, are represented: "01100100100" => 011.00100100 => +3.14 "10011011100" => 100.11011100 => - 3.14 When Phase Format is set to Scaled Radians PHASE_IN must be in the range: -1 <= (PHASE_IN) <= +1. PHASE_IN outside this range will produce unpredictable results. In 2Q10 format values, +1 and -1, are represented:

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"0010000000" => 001.0000000 => +1.0 "1110000000" => 111.0000000 => - 1.0 Q Format Signed Numbers A QN format number is an N bit 2s complement binary number; a sign bit followed by an N bit mantissa (fraction). QN format can be used to express numbers in the range -1 to (1 - 2-N). An XQN format number is a QN format number left shifted by X bits. XQN format can be used to express numbers in the range: ( -2X ) to ( 2X - 2(X-N) ). Examples of XQN Format Numbers
Table 11: 1QN Format Data

SB
+1 -1 +Pi/4 -Pi/4 0 1 0 1

D8
1 1 0 1

D7
0 0 1 0

D6
0 0 1 0

D5
0 0 0 1

D4
0 0 0 1

D3
0 0 1 0

D2
0 0 0 1

D1
0 0 0 1

^ <---Binary Point
Table 12: 2QN Format Phase

SB
+1 -1 +Pi -Pi 0 1 0 1

D8
0 1 1 0

D7
1 1 1 0

D6
0 0 0 1

D5
0 0 0 1

D4
0 0 1 0

D3
0 0 0 1

D2
0 0 0 1

D1
0 0 1 1

^ <---Binary Point
Control Signals

The following section describes the control signals used by the CORDIC core. All control signals are synchronous to the rising edge of CLK, except ACLR. A timing diagram for a CORDIC core with a Word Serial Architectural Configuration is shown in Figure 13. A timing diagram for a CORDIC core with a Parallel Architectural Configuration is shown in Figure 14.

Optional Control Pins

CLK All core operations are synchronous with the rising edge of the CLK (Clock) input, except the optional ACLR input. CLK is mandatory when ((Pipeline Mode /= Pipeline None) or (Register Inputs = True) or (Register Outputs = True)). Otherwise, CLK is not present.

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ND When the ND (New Data) input is high, the input data is sampled on the same rising clock edge. ND is ignored if CE is low or if RFD is low. ND is mandatory when (Architectural Configuration = Word Serial). Otherwise, ND is optional. RFD RFD (Ready for Data) indicates that the core is ready to sample new input data. The RFD signal is set high upon startup or during reset. RFD is mandatory when (Architectural Configuration = Word Serial). Otherwise, RFD is not present. RDY The RDY (Ready) output signals that a new valid data sample is present on the Data Output Ports. RDY is pulsed high on the first clock cycle of valid data at the output. The RDY signal is set low upon startup or during reset. RDY is mandatory when (Architectural Configuration = Word Serial). Otherwise, RDY is optional. ACLR All control signals are synchronous to the rising edge of CLK except ACLR. When ACLR is asserted (High), all the core flip-flops are asynchronously initialized. The core remains in this state until ACLR is deasserted. ACLR is optional. SCLR When SCLR is asserted (High), all the core flip-flops are synchronously initialized. The core remains in this state until SCLR is deasserted. SCLR is optional. CE When CE (Clock Enable) is Low, all the synchronous inputs are ignored and the core remains in its current state. CE is optional.

Figure Top x-ref 13

CORDIC Latency CLK CE SCLR ND Data Inputs Data Outputs RDY RFD Multiple Clock Cycles Di0 <0> Do0

Figure 13: Control Signal Timing Diagram (Word Serial Architecture)

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Figure Top x-ref 14

CORDIC Latency CLK CE SCLR ND Data Inputs Data Outputs RDY Multiple Clock Cycles Di0 <0> Di1 Di2 Do0 Do2

Figure 14: Control Signal Timing Diagram (Parallel Architecture)

Characterization Data
The Characterization Data in Table 13 and Table 14 is was generated for CORDIC Cores with 16 bit Input and Output widths, automatically determined Iterations and Precision, Coarse Rotation, no Compensation Scaling and Maximum Pipelining.
Table 13: Characterization Data - Parallel Architecture

Parallel
Size Speed in MHz

Rotate
680 170

Translate
613 164

Sin Cos
613 164

ArcTan
571 165

Sinh Cosh
660 168

Arctanh
625 160

Sqrt Frac
235 207

Sqrt Int
103 227

Table 14: Characterization Data - Word Serial Architecture

Word Serial
Size Speed

Rotate
366 133

Translate
300 134

Sin Cos
299 134

ArcTan
279 134

Sinh Cosh
273 114

Arctanh
279 116

Sqrt Frac

Sqrt Int

Parameter Values in the XCO File

Names of the XCO parameters and their values correspond to the names and values shown in the GUI. Underscore characters (_) are used instead of spaces. The text in an XCO file is case insensitive. The following sample provides an example of the CSET parameters in an XCO file. CSET Parameters in an XCO File CSET synchronization_enable = No_Override CSET create_rpm = true CSET register_inputs = true CSET sclr = false CSET architectural_configuration = Parallel CSET phase_format = Radians

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CSET nd = false CSET data_format = SignedFraction CSET register_outputs = true CSET rdy = true CSET aclr = false CSET ce = true CSET y_out = true CSET component_name = cordic_rotate CSET pipelining_mode = Maximum CSET compensation_scaling = No_Scale_Compensation CSET input_width = 16 CSET round_mode = Round_Nearest_Even CSET iterations = 0 CSET precision = 0 CSET functional_selection = Rotate CSET output_width = 16
Table 15: Parameter File Information

Parameter Name
aclr architectural_configuration ce compensation_scaling component_name coarse_rotation create_rpm data_format functional_selection input_width iterations nd output_width phase_format True, False

XCO Filename Values

Default GUI Setting

False Parallel True no_scale_compensation blank True True SignedFraction Rotate 16 0 False 16 Radians

Word_Serial, Parallel True, False no_scale_compensation, ccm_scale_compensation, block_scale_compensation ASCII text starting with a letter and based upon the following character set: a..z, 0..9 and _ True, False True, False SignedFraction, UnsignedFraction, UnsignedInteger Rotate, Translate, Sin_and_Cos, Sinh_and_Cosh, Atan, Atanh, Square_Root 8 to 48 0 to 48 True, False 8 to 48 Radians, Scaled_Radians

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Table 15: Parameter File Information (Continued)

Parameter Name
phase_out pipeline_mode precision rdy register_inputs register_outputs rfd round_mode sclr synchronization_enable x_out y_out True, False

XCO Filename Values

Default GUI Setting

False maximum 0 True True True False Round_Pos_Neg_Inf false No_Override True True

minimum, optimum, maximum 0 or output_width to 48 True, False True, False True, False True, False Round_Truncate, Round_Pos_Inf, Round_Pos_Neg_Inf, Round_Nearest_Even true, false No_Override, Override True, False True, False

Background Information
References
1. 2. Volder, J., The CORDIC Trigonometric Computing Technique IRE Trans. Electronic Computing, Vol. EC-8, Sept. 1959, pp330-334 Walther, J.S., A Unified Algorithm for Elementary Functions, Spring Joint computer conf., 1971, proc., pp379-385

Ordering Information
This core may be downloaded from the Xilinx IP Center for use with the Xilinx CORE Generator system v7.1i and later. The Xilinx CORE Generator system is bundled with all ISE Foundation software packages, at no additional charge. To order Xilinx software, please visit the Xilinx Xpresso cafe or contact your local Xilinx sales representative. Information on additional Xilinx LogiCORE modules is available on the Xilinx IP Center.

Revision History
Date
03/28/03 03/28/03 03/28/03 05/21/04 04/28/05

Version
1.0 1.1 2.0 3.0 3.1

Revision
Revision History added to document. Updated Hyperbolic Transformations and PiRadian format. Improved parameterization, new rounding modes, and new data formats. Added Virtex-4 support and update to v6.2i of Xilinx CORE Generator system. Updated to indicate support for Spartan-3E and Xilinx ISE software v7.1i.

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