ECE453 Lab 3 Fall 2007

Assigned: Thu. Sep. 20, 2007 Due: Thu. Oct. 4, 2007

ECE453 Lab 3 Differential Amplifier Design

1 Objective:
This lab will explore the design of a differential amplifier. Schematic entry and layout are needed. A careful review of the previous two labs is very helpful. By this time you should be familiar with most basic operations in Cadence.

2 Lab Instructions:
2.1 design specification: Input signal: sine wave, amp=5m, offset=1.5 Load: 50f Power supply: 2.5 Gain: >2.8 Bandwidth: >3.6GHz Power consumption: <2.5mw Layout area: <800 um^2 2.2 Schematic Generation and Entry: Make a new cell with name: lab3_DiffAmp_yourNetID In the CIW window, File new Cellview Library Name: ece453 Cell Name: lab3_DiffAmp_yourNetID View Name: schematic Input the differential amplifier schematic as Fig1. vout1 and vout2 are output pins and the rest of the pins are input pins. nfets and resistors are from bicmos6hp library. The resistor here is oppcres. You are welcome to explore other types of resistor to fit your design. Make sure you have subc included. Missing subc will lead to unrealistic simulation and LVS fail. Now, it is your turn to design the differential amplifier by sizing the transistors and resistors to meet the design goal.

ECE453 Lab 3 Fall 2007

Assigned: Thu. Sep. 20, 2007 Due: Thu. Oct. 4, 2007

Fig. 1 schematic of differential amplifier Generate symbol In the schematic window, Design Create Cellview from Cellview In the pop up window, Hit OK. In the next pop up window, Hit OK. (Or you can modify the pin configuration) Save the symbol and close the symbol window. Create a new test cell In the CIW window, File new Cellview Library Name: ece453 Cell Name: lab3_sim_yourNetID Vie Name: schematic In put the schematic as Fig2. Power supply (vdd) is 2.5 v. Load is 50f.

ECE453 Lab 3 Fall 2007

Assigned: Thu. Sep. 20, 2007 Due: Thu. Oct. 4, 2007

Fig.2 Schematic of the test cell Make differential inputs. Samples are provided as following.

Fig 3. input 1

ECE453 Lab 3 Fall 2007

Assigned: Thu. Sep. 20, 2007 Due: Thu. Oct. 4, 2007

Fig4 input 2 2.3 Simulation: Click on Check and Save and make sure your design is error free. Warnings are allowed if you know they wont affect your simulation. You may need to setup the following under the setup tab. Simulator/Directory/Host Design Model Libraries If you have trouble setting up this, please check previous lab instructions.

DC Analyses:
Select Analyses-Choose Select dc. Disable all other analyses. Select Save DC Operating Point Select enabled.

ECE453 Lab 3 Fall 2007

Assigned: Thu. Sep. 20, 2007 Due: Thu. Oct. 4, 2007

Hit OK. In the Analog Design Environment window, Select Simulation - Netlist and Run. When the simulation is done. In the Analog Design Environment window, Select Results Annotate DC Node Voltages. Then the DC node voltages will show up in the schematic window. You can check the operating region of the transistors. In the Analog Design Environment window, Select Results Annotate DC Operating Points. Then the transistor operating point data will show up on the schematic window for you to design the circuit. You can check the operating region of the transistors. This is very helpful for designers to set the DC operating point, bias voltage, etc. Basically, you want the diff pair in saturation region and current source transistor in saturation.

AC analysis:
Select Analyses-Choose Select ac. Select sweep variable frequency Select sweep range start-stop 1 to 20G Select enabled. Hit OK In the Analog Design Environment window, Select Simulation - Netlist and Run. When the simulation is done, (A)Find the Bandwidth In the Analog Design Environment window, Select Results AC magnitude for Out put in the unit of V find the BW by locating the frequency when the output drop to 0.707x. Select Results AC dB20 for Out put in the unit of dB (20log[Vout]). find the BW by locating the frequency when the output drop by 3db. (B)Find the gain Select Results AC magnitude, then select both output and input nets. The ratio of the two is the gain. Modify the design to meet the specs. You may spend a lot of time here

Transient Analysis:
Select Analyses-Choose Select tran. Select stop time 1u Select enabled.

ECE453 Lab 3 Fall 2007

Assigned: Thu. Sep. 20, 2007 Due: Thu. Oct. 4, 2007

Hit OK. In the Analog Design Environment window, Select Simulation - Netlist and Run. When the simulation is done, Plot the differential inputs and outputs.

2.4 Layout
For convenience, the following are layout tips. Vias can be placed by selecting Create Contact and they can be placed on top of each other. Place multiple or an array of contacts or vias for robust design. Try to make your layout compact for less parasitic. Use multi-finger transistor if necessary It is more than welcome to use common centroid layout.

Starting Layout Open your lab3_DiffAmp_NETID schematic window. Select Tools Design Synthesis Layout XL. In the window that appears, select the Create New Cellview checkbox. Make sure the cell name agrees with your schematic name and that the tool is Virtuoso. Press OK. In the Virtuoso XL Layout window: Design-Gen From Source. In the Defaults fields: Specify Layer/Master. Width and Height. There are several layers, but only the dg, drawing layer is what we need. For example: Layer/Master : M1 dg Width= 2 Height= 2 Num= 1 Check Create. Click Apply Pin Defaults, you should see all pins are changed accordingly. You should now see the components and an outline box in the virtuoso window. Select one of the cells and move it to a new location. You will see lines extending from the cell as you move it. These lines are called flight lines and they represent connections that must be made in the layout. You should also notice that when you select a component in the layout, it selects the corresponding component in the schematic window. If you are having trouble moving the cells, select Options layout editor and de-select the gravity check box and click none for types. Also be sure to go into Options display and change the layers option to 0 to 20 instead of 0 to 0. You can also change your x and y snap increments to 0.02. To enable moving a cell in any direction press F3 while moving a cell and select any angle for snap mode. Arrange all the parts in the purple outline box taking care to arrange them in a manner that makes the wiring convenient. A good way to start would be to think about where you would like the pins to be located. If you start from the pin locations and work in you may have less difficulty in planning your layout. It would be a very good idea to put some thought into how you are going to route signals before you actually start your layout. Additionally, it would also be a good idea to run DRC intermittently to see if you have violated any design rules. This can be done by selecting Verify DRC. If you run into DRC problems you

ECE453 Lab 3 Fall 2007

Assigned: Thu. Sep. 20, 2007 Due: Thu. Oct. 4, 2007

can highlight the DRC errors that have been found using Verify markers find. The documentation for the DRC errors can be found in the design manual. Again, there are many functional aids that can be found in the layout tool, and we encourage you to explore to see what different commands and shortcuts will do for you. *NOTE* In order to keep your design fit to the window, be sure to delete all DRC markers before saving. This can be done by going to Verify markers delete and selecting delete all. Tie Downs : Tie-downs are reverse biased diodes to the substrate that prevent damage to the circuits during processing. Tie downs will be required for FET gates, PFET wells and MIM Cap top and bottom plates. Tie downs may be added as instances in the layout. They are located in the bicmos6hp library. To tie down the FET gates, the gate metallization must be contacted with a tie down somewhere on M1. For PFET wells, connect the tie down to the metallization for the well contact of the device. The tie down must be placed outside the pcell for the PFET. For MIM caps, connect the tie downs to the AM connection to both the top and bottom plates (separately) using via stacks to connect the AM layer to the M1 layer of the tie down.

2.5 Extraction and LVS

Once you have made all the necessary connections perform a final DRC. Now, generate an extracted netlist by choosing Verify extract. The rules file must be set to divaEXT6.rul and bicmos6hp must be set as the rules library. From here, choose Verify LVS and be sure to fill in the names of your schematic netlist and extracted netlist including that the views are schematic and extracted. The rules file should be divaLVS.rul and the rules library should be bicmos6hp. Once this is done, choose Run. Once the LVS has finished, you can examine the output by choosing output. If the file says The netlists match then youre finished. Print this file for your final report. If not, examine the error warnings and figure out what needs to change in your layout so that it matches the schematic. You can then repeat the extraction and LVS process to view the new results.

2.6 About the specs

Try your best to meet the specs, though there will not be too high a penalty for not meeting all of them.

3 Report
An individual lab write-up showing your schematic, simulation results, layout, and DRC clean, LVS match file is required. The report should be brief (perhaps 1-2 pages of writing plus plots), but include a summary of the insights you gained from the lab. Indicate the layout area in the layout picture. Calculate the power consumption. Gain and BW as showed below.

4 Acknowledgment:
This lab was originally designed by Zhongtao Fu for ECE453 Fall 2005. Updated by Xiao Wang and Paul Chen for subsequent years.

ECE453 Lab 3 Fall 2007

Assigned: Thu. Sep. 20, 2007 Due: Thu. Oct. 4, 2007

check the -3 db drop, delta f is BW.

The gain is the ratio of the two, 14.2/5

Questions ? Post it on the forum

http://groups.google.com/group/ECE453