JAN 2009 VOL 1.
VLSI JAGRITI
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“Excuses are the nails used to
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Tech Byte
VLSI Physical design
Introduction
The size of present-day computing systems demands the elimination
of repetitive manual operations and computations in their design. This
motivates the development of automatic design systems. To
accomplish this task, a fundamental understanding of the design
problem and full knowledge of the design process are essential. Only
then could one hope to efficiently and automatically fill the gap
between system specification and manufacturing. Automation of a
given (design) process requires an algorithmic analysis of it. The
availability of fast and easily implementable algorithms is essential to
the discipline.
In order to take full advantage of the resources in the very-large-scale
integration (VLSI) environment, new procedures must be developed.
The efficiency of these techniques must be evaluated against the
inherent limitations of VLSI. Previous contributions are a valuable
starting point for future improvements in design performance and
evaluation.
Physical design (or layout phase) is the process of determining the
physical location of active devices and interconnecting them inside
the boundary of a VLSI chip (i .e. an integrated circuit). This issue
focuses on the layout problem that plays an important role in the
design process of current architectures. The measure of the quality of
a given solution to the circuit layout problem is the efficiency with
which the circuit (corresponding to a given problem) can be laid out
according to the formal (design) rules dictated by the VLSI
technology. Since the cost of fabricating a circuit is a function of the
circuit area, circuit layout techniques aim to produce layouts with a
small area. Also, a smaller area implies fewer defects, hence a higher
yield. These layouts must have a special structure to guarantee their
wirability (using a small number of planes in the third dimension).
Other criteria of optimality, for example, wire length minimization,
delay minimization, power minimization, and via minimization also
have to be taken into consideration. In present-day systems, delay
minimization is becoming more crucial. The aim is to design circuits
that are fast while having small area. Indeed, in "aggressive" designs,
used for example in the medical electronics industry, speed and
reliability are the main objectives.
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In the past two decades, research has been directed toward
automation of layout process. Many invaluable techniques have been
proposed. The early layout techniques, designed for printed circuit
boards containing a small number of components, assumed a fixed
position for the components. The earliest work along this line is a
wiring algorithm based on the propagation of "distance wave." Its
simplicity and effectiveness have been the reasons for its success. As
the number of components increased and with the advent of VLSI
technology, efficient algorithms for placing the components and
effective techniques for component (or cell) generation and wiring
have been proposed.
Because of the inherent complexity of the layout problem, it is
generally partitioned into simpler sub problems, with the analysis of
each of these parts providing new insights into the original problem
as a whole. In this framework, the objective is to view the layout
problem as a collection of sub problems; each sub problem should be
efficiently solved, and the solutions of the sub problems should be
effectively combined. Indeed, a circuit is typically designed in a
hierarchical fashion. At the highest level of hierarchy, a set of ICs
are interconnected. Within each IC, a set of modules, for example,
memory units, ALUs, input-output ports, and random logic, are
arranged. Each module consists of a set of gates, where each gate is
formed by interconnecting a collection of transistors. Transistors and
their interconnections are defined by the corresponding masks. Here
first we will give a brief overview of VLSI Technology layout rules,
cell generation techniques, followed by layout environments, layout
methodologies and VLSI Packaging issues
VLSI Technology
The most prevalent VSLI technology is metal-oxide-semiconductor
(MOS) technology .The three possibilities of functional cells (or sub
circuits) are p-channel MOS (PMOS), n-channel MOS (NMOS), and
complementary MOS (CMOS) devices. PMOS and NMOS are not
used anymore. CMOS offers very high regularity and often achieves
much lower power dissipation than other MOS circuits.
Although this is an overview of MOS
technology, most concepts developed in this book are to a large
extent technology-independent. CMOS is likely to be current for
some time, as it satisfies VLSI system requirements
 Conductor 9 Mask 6 defines contact cuts
9 Mask 7 defines the metal layer pattern.
4 SiO2
9 Mask 8 is an overall passivation layer that is required to
2 n+ n+ 3 define the openings for access to bonding pads
p Layout Rules and Circuit Abstraction
1 A circuit is laid out according to a set of layout rules (or geometric
Vertical Section design rules). The layout rules, being in the form of minimum
allowable values for certain widths, separations, and overlaps, reflect
the constraints imposed by the current technology. These values are
Source Gate Drain expressed as a function of a parameter), that depends on the
2 4 3 technology. The parameter x is approximately the maximum amount
of accidental displacement. (In the early 1980s, x was about 3
microns; in the early 1990s, submicron fabrication became feasible
Top View and now we are at deep sub micron.)
In realizing the interconnections, the following set of rules
4 is adopted. Assume that layers L1, . . . , L„ are available, ordered from
1 to v, so that Li is below Li+1 . L1 is typically polysilicon and L2. L„
3 are metal. (There is a diffusion layer below L1; however, it is not used
for interconnection)
2 Symbol R1. Wire width: Each wire in layer L, (1 < i < v) has a minimum
width w i), (see Figure 2a). Due to possible displacement x for each
Fig 1 : Geometry of an NMOS switch . edge of a wire in layer L1, wl > 2. In this case, even if an edge of the
wire displaces by x, the width of the wire remains nonzero. Also
VLSI technology offers the user a new and more complex range of since a wire in layer Li runs over more wires than a wire in layer Li_1
"off the shelf' circuits (i .e. predesigned circuits), but MOS VLSI (i .e ., in upper layers the surface becomes less smooth),
design processes are such that system designers can readily design wi > w i _1
their own special circuits of considerable complexity. This provides R2. Wire separation: Two wires in layer Li have a minimum
a new degree of freedom for designers. separation of six (see Figure 2b). Normally sl = 3 since there is a
The geometry of an NMOS switch is shown in Figure 1. On a silicon possible displacement of x for each wire, and after possible
substrate (1) of the p-type (i .e., doped with 3-valent atoms)-where displacement the two wires must be separated by x units to avoid
positive carriers (holes) are available-two strips (2) and (3), cross-talk. Also si > si_ 1 .
separated by a narrow region (4), are heavily doped with 5-valent
atoms . This modified material is called diffusion, with reference to
the doping process. The two regions (2) and (3) are respectively
called the source and drain, and region (4) is called the channel.
Over the channel, a thin layer of silicon dioxide, SiO2, is created,
and a conductor plate is placed on top of it . The latter, called the
gate, is typically realized in polysilicon
Photolithography is used to pattern the layers of an integrated circuit
.Photoresist (PR) is placed on the wafer surface and the wafer is spun
at high speed to leave a very thin coating of PR. PR is a ajλ
photosensitive chemical used with a mask to define areas of wafer
surface by exposure to ultraviolet ` light . The mask consists of
opaque and transparent materials patterned to define areas on the w iλ siλ
wafer surface. It is the pattern of each mask that an engineer designs
ejλ
MOS design is aimed at turning a specification (a) (b) (c)
into masks for processing silicon. Typical NMOS circuits are formed
on three layers, diffusion, polysilicon and metal, that are isolated
from one another by thick or thin silicon dioxide insulating layers. Fig 2 : Layout Rules
The thin oxide (thinox) region includes n-diffusion, p-diffusion, and λui
transistor channels. Polysilicon and thinox regions interact so that a
transistor is formed where they "cross" one another. Layers may be λs+λe
deliberately joined together where contacts, also called vias, are
formed for electrical connection
Typical processing steps are:
9 Mask 1 defines the areas in which the deep p-well λs
diffusions are to take place (similar to region 1 in Figure 1)
on an n-type substrate
9 Mask 2 defines the thinox (or diffusion) regions, namely,
those areas where the thick oxide is to be stripped and thin
oxide grown to accommodate p and n-transistors and wires
(similar to regions 2-4 in Figure 1).
9 Mask 3 is used to pattern the polysilicon layer that is λe
deposited after the thin oxide.
9 Mask 4 is a p-plus mask used to define all areas where p- (a) (b)
diffusion is to take place. Fig 3 : Abstract Model (a) Mask Layout (b) abstract layout
9 Mask 5 is usually performed using the negative form of the
p-plus mask and defines those areas where n-type diffusion
is to take place.

R3. Contact rule: To connect two wires in layers Li and Lj (i < j) a
contact (via) must be established. The two wires must overlap for ej λ
x ej λ, units and the contact cut must be ajλ x ajλ units (see Figure 2) .
Typically ei > ei_1 and ai > ai_t.
To facilitate the analysis of the layout problem, assume for every pair
of layers: (Al) wiλ = wvλ = λw, (A2) siλ. = svλ =λs for 1 < i < v, (A3)
ejλ=ekλ,=λe and ajλ. = akλ = λa . Thus, in an abstract model, the wires
are viewed as segments (i .e, they have zero width) on the plane with
λs + λe separation between two wires, as shown in Figure 3. Actually,
in the situation shown in the figure, the separation is λs + (λs + λe)/2
between two wires . However, to make all separations uniform (for
simplicity), it is assumed that all separations are caused by vias, and
thus λs+λe is used as the corresponding separation. When the number
of layers is small (e.g. v = 3) the wasted area, due to assumptions A1-
A3, is negligible. A layout conforming with the given set of design
rules is called a legal layout.
The chip area, which must be minimized, is the smallest
rectangle (IC packages are rectangular in shape) enclosing a legal
layout of the circuit. In order to simplify design rule checking,
consider a grid environment. A circuit, represented by a circuit graph
(to be defined), will be mapped into or placed in a grid.
A formal definition of a grid follows. A plane figure is
called a tile if the plane can be covered by copies of the figure
without gaps and overlaps (the covering is then called a tessellation) .
A square tessellation is one whose tiles are squares. The dual of the
tessellation is called a (square) grid-graph. The vertices (grid points)
of the grid-graph are the centers of the tiles, and edges join grid
points. belonging to neighboring tiles . The separation between two
adjacent columns or two adjacent rows is 1 unit, that is, λs+λe (see
Figure 4). When a grid-graph is placed on the plane (a graph is a
topology), we call it a grid.
Vertex circuit consisting of one or more basic cells, such as NAND or
1unit
Edge
A tile
Fig 4 : A square grid graph
A circuit C = {M, .N} consists of a collection M = {M1…. M„,} of
modules-each module being a collection of active devices-and a set N
= {Nl, . . . , N„} of nets . Each net specifies a subset of points on the
boundary of the modules to be interconnected. A circuit graph GC is a
hypergraph associated with C, where vertices correspond to the
modules and hyperedges correspond to the nets. In certain problems,
it is more convenient to deal with a circuit graph than with the circuit.
A solution to the grid layout problem consists of embedding each
module M, (1 < i < m) of the circuit on the grid using a finite
collection T of tiles and interconnecting the terminals of each net by
means of wires in the region outside the modules . An example is
shown in Fig 5 A conducting layer is a graph isomorphic to the
layout grid . Assume that layers L 1 , . . ., L„ are available, ordered
from 1 to v, so that Li-1 is below Li . Contacts (vias) between two
distinct layers can be established only at grid points.
A wiring of a given two-dimensional layout (e .g., the 2D layout
shown in Figure 5) is a mapping of each edge of wires to a
conducting layer, where a wire is a tree interconnecting terminals of
a net . A via is established between layers Lh and Lk (h < k) at a grid
point, then layers Lj , h < j < k, cannot be used at that grid point . A
layout W is v-layer wirable if there exists a v-layer wiring of W.
The terms routing, interconnection, and layout refer to a
two-dimensional problem, and the terms wiring and layer-
assignment refer to the mapping of the two-dimensional entities to
the third dimension.
Fig 5 : An example of grid layout
Cell Generation
In VLSI design, a logic function is implemented by means of a
NOR gates. The set of cells form a library that can be used in the
design phase. Basic cells have a smaller size and better
performance, for they have been optimized through experience.
Thus, employing predesigned basic cells decreases design time and
produces structured designs. In CMOS circuits, it is possible to
implement complex Boolean functions by interconnecting NMOS
and PMOS transistors.
Cell generation techniques are classified as random generation or
regular style. A random generation technique is obtained by placing
the basic components and interconnecting them. That is, there is no
regular connection pattern. It is difficult to create a library of such
cells because of their complexity. Thus, they must be designed from
scratch. In contrast, the interconnection in a regular style technique
admits a pattern. Compared to the regular cells (e .g., PLAs, ROMs,
and RAMs), random logic cells occupy less silicon area, but take
longer design time . Regular cells can be used to easily implement a
set of Boolean expressions. The disadvantage of a regular cell, for
example, a ROM-based cell, is that it takes a lot of area, for it uses
many redundant transistors. Clearly, reducing the space required is
important in designing functional cells. Several systematic layout
methods to minimize the total area, for example, gate matrices and
transistor chaining techniques, have been introduced
Programmable Logic Arrays
A programmable logic array (PLA) provides a regular structure for
implementing combinational and sequential logic functions. A PLA
may be used to take inputs and compute some combinational
function of these inputs to yield outputs. Additionally some of the
outputs may be fed back to the inputs through some flip flops, thus
forming a finite-state machine.
Boolean functions can be converted into a two-level sum-of-product
form and then be implemented by a PLA. A PLA consists of an
AND-plane and an OR-plane. For every input variable in the
Boolean equations, there is an input signal to the AND-plane. The
AND-plane produces a set of product terms by performing AND
operations. The OR Plane generates output signals by performing
The OR-plane generates output signals by performing an OR
operation on the product terms fed by the AND-plane. Reducing
either the number of rows or the number of columns results in a
more compact PLA. Two techniques have been developed, logic
minimization for reducing the number of rows and PLA folding for
reducing the number of columns. Using the technique, the number
of product terms can be reduced while still realizing the same set of
Boolean functions. Folding greatly reduces the area and is
performed as a post-processing step.
Layout Environments
A circuit layout problem, involves a collection of cells (or
modules). These modules could be very simple elements (e.g. ., a
transistor or a gate) or may contain more complicated structures (e
.g. a multiplier)
Layout architecture refers to the way devices are organized in the
chip area Different layout architectures achieve different trade-offs
among speed, packaging density, fabrication time, cost, and degree
of automation. The fabrication technology for these layout
architectures are generally identical. The design rules are also
independent of the layout architectures. The main difference lies in
design production.
There are three styles of design production: full custom,
semicustom, and universal. In fullcustom,, a designer designs all
circuitry and all interconnection paths, whereas in semicustom, a
library of predesigned cells is available . In universal circuitry, the
design is more or less fixed and the designer programs the
interconnections. Examples of universal circuitry are PLAs and
FPGAs (to be described next) . The designer chooses the
appropriate ones and places them in the chip. In full custom designs
there are no restrictions imposed on the organization of the cells.
Thus it is time-consuming to design them, and it is difficult to
automate them. However, area utilization is very good. In
semicustom design, there are restrictions imposed on the
organization of the cells (e .g. row-wise or grid wise arrangements)
. These circuits can be designed faster and are easier to automate,
but area efficiency is sacrificed. Universal circuitries rely on
programmable memory devices for cell functions and
interconnections
Layout Methodologies
The layout problem is typically solved in a hierarchical framework
.Each stage should be optimized, while making the problem
manageable for subsequent stages. Typically, the following sub
problems are considered (Figures 6 shows each step)
Fig 6: An example demonstrating
hierarchical steps in the layout
process
• Partitioning is the task of dividing a circuit into smaller
parts. The objective is to partition the circuit into parts,
so that the size of each component is within prescribed
ranges and the number of connections between the
components is minimized. Different ways to partition
correspond to different circuit implementations.
Therefore, a good partitioning can significantly improve
circuit performance and reduce layout costs. A
hypergraph and a partition of it is shown in Figure 6a.
The cut (or general cuts) defines the partition.
• Floor planning is the determination of the approximate
location of each module in a rectangular chip area, given
a circuit represented by a hypergraph-the shape of each
module and the location of the pins on the boundary of
each module may also be determined in this phase. The
floor planning problem in chip layout is analogous to
floor planning in building design, where we have a set of
rooms (modules) and wish to decide the approximate
location of each room based on some proximity criteria.
An important step in floor planning is to decide the
relative location of each module. A good floor planning
algorithm should achieve many goals, such as making
the subsequent routing phase easy, minimizing the total
chip area, and reducing signal delays. The floor plan
corresponding to the circuit shown in Figure 6 a is
shown in Figure 6 b. Typically, each module has a set of
implementations, each of which has a different area,
aspect ratio, delay, and power consumption, and the best
implementation for each module should be obtained
• Placement, when each module is fixed, that is, has fixed
shape and fixed terminals, is the determination of the
best position for each module. Usually, some modules
have fixed positions (e .g., 1/O pads) . Although area is
the major concern, it is hard to control it. Thus,
alternative cost functions are employed. There are two
prevalent cost functions: wire-length-based and cut-
based. The placement corresponding to the circuit shown
in Figure 6a is shown in Figure 6c, where each module
has a fixed shape and area
• Global routing decomposes a large routing problem into
small, manageable problems for detailed routing. The
method first partitions the routing region into a
collection of disjoint rectilinear subregions. This
decomposition is carried out by finding a "rough" path (i
.e., sequence of "subregions" it passes) for each net in
order to reduce the chip size, shorten the wire length,
and evenly distribute the congestion over the routing
area . A global routing based on the placement shown in
Figure 6c is shown in Figure 6d
• Detailed routing follows the global routing to effectively
realize interconnections in VLSI circuits. The traditional
model of detailed routing is the two-layer Manhattan
model with reserved layers, where horizontal wires are
routed on one layer and vertical wires are routed in the
 •
Technology News
Other layer. For integrated circuits, the horizontal
segments are typically realized in metal while the vertical
segments are realized in poly silicon. In order to
interconnect a horizontal and vertical segment, a contact
(via) must be placed at the intersection points. More
recently, the unpreserved layer model has also been
discussed, where vertical and horizontal wires can run in
both layers. A detailed routing corresponding to the global
routing shown in Figure 6d is shown in Figure 6e; the
Manhattan model is used. Recent designs perform
multilayer detailed routing and over-the-cell (OTC)
routing,
• Layout optimization is a post-processing step. In this stage
the layout is optimized, for example, by compacting the
area. A compacted version of the layout shown in Figure
6e is shown in Figure 6f.
• Layout verification is the testing of a layout to determine if
it satisfies design and layout rules
The above steps are followed in their entirety in full custom
designs. In other layouts, such as standard cells and PLAs, some of
the steps are not taken: this is due to standardization or
prefabrication. Details of the steps taken in full custom designs and
in the special cases will be discussed in subsequent chapters. We
shall refer to the problems related to location of modules (i .e .,
partitioning, floor planning, and placement) as the placement
problem, and the problems related to interconnection of terminals (i
.e, global and detailed routing) as the routing problem . In addition,
there are other post-processing problems, such as via and bend
minimization, that will be discussed.
Packaging
The previous sections have emphasized designing fast and reliable
VLSI chips. These chips must be supported by an equally fast and
reliable packaging technology. Packaging supplies chips with
signals and powers, and removes the heat generated by circuitry.
Packaging has always played an important role in determining the
overall speed, cost, and reliability of high-speed systems such as
supercomputers. In such high-end systems, 50% of the total system
delay is usually due to packaging, and by the year 2010 the share of
packaging delay may rise to 80%. Moreover, increasing circuit
count and density in circuits place further demands on packaging. A
package is essentially a mechanical support for the chip and
facilitates connection to the rest of the system. One of the earliest
Packaging techniques was dual-in-line packaging (DIP) . An
example is shown in Figure 7. A DIP has a small number of pins.
Pin grid arrays (PGA) have more pins that are distributed around
the packages (see fig 7)
Fig 8 : A typical MCM
. This innovation led to major advances in interconnection density
at the chip level of packaging. Compared with single chip
packages or surface mount packages, MCMs can reduce circuit
board area by five to ten times and improve system performance
by 20% or more. Therefore, MCM has been used in high
performance systems as a replacement for the individual
packages. An instance of a typical MCM is shown in Figure 8,
where chips are placed and bonded on a surface at the top layer
(called the chip layer). Below the chip layer, a set of pin
redistribution layers is provided for distributing chip UO pins for
signal distribution layers. The primary goal of MCM routing is to
meet high performance requirements, rather than overly
minimizing the layout area
Requirements of a successful chip Design
In the field of modern VLSI circuit design, constructing a chip
from concept to silicon is an ultra complicated task that involves
many factors. For a successful project, the chip must be:
• Structurally correct to achieve its intended design
functions
• Functionally correct at the designed clock speed in
various working environments (voltage, temperature,
and process corner)
• Reliable throughout its life (e.g., 100k hours or eleven
years)
• Manufacturing-friendly
Further, it must be built such that:
• It can be handled safely in an assembly line and various
other environments without being damaged (e.g., it is
protected from electrostatic discharge or ESD and latch-
up).
• It can be packaged economically.
• It stays within its power budget.
• Cost is minimized.
• It is manufactured within its time schedule.
And, then, finally, there must be an existing or potential market
for this chip.

Fig 7 :Typical DIP and PGA Packages (a) DIP (b) PGA
In order to minimize the delay, chips must be placed close together.
Multichip module (MCM) technology has been introduced to
significantly improve performance by eliminating packaging. An
MCM is a packaging technique that places several semiconductor
chips, interconnected in a high density substrate, into a single
package
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