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A CMOS Passive Mixer With Low Flicker Noise for Low-Power Direct-Conversion Receiver
Sining Zhou, Member, IEEE, and Mau-Chung Frank Chang, Fellow, IEEE
AbstractA CMOS passive mixer is designed to mitigate the critical icker noise problem that is frequently encountered in constituting direct-conversion receivers. With a unique single-balanced passive mixer design, the resulted direct-conversion receiver achieves an ultralow icker-noise corner of 45 kHz, with 6 dB more gain and much lower power and area consumption than the double-balanced counterpart. CMOS switches with a unique bias-shifting network to track the LO DC offset are devised to reduce the second-order intermodulation. Consequently, the mixers IIP2 has been greatly enhanced by almost 21 dB from a traditional single-balanced passive mixer. An insertion compensation method is also implemented for effective dc offset cancellation. Fabricated in 0.18 m CMOS and measured at 5 GHz, this passive mixer obtains 3 dB conversion gain, 39 dBm IIP2, and 5 dBm IIP3 with LO driving at 0 dBm. When the proposed mixer is integrated in a direct-conversion receiver, the receiver achieves 29 dB overall gain and 5.3 dB noise gure. Index TermsComplementary switches, conversion gain, dc offset cancellation, direct conversion receiver, icker noise, input-referred baseband noise, LO bias, passive mixer, RF CMOS, second-order intermodulation, single-balanced.
Fig. 1. (a) DC offset generated in a typical DCR. (b) Baseband signal degraded by icker noise. (c) Even-order distortion caused by signal in-band and interferers in adjacent channels.

I. INTRODUCTION HE direct-conversion receiver (DCR) has attracted widespread attention recently for its simple architecture and easy integration with the baseband circuit, as well as for its low power consumption and potentially low manufacturing costs. In addition, wide-bandwidth signals can be more easily accommodated in a DCR when the on-chip LPF, rather than the off-chip bandpass lter, is used for the channel selection. As a result, low-frequency ADC and DSP engines can be inserted to demodulate the incoming signal, which enables the possible development of a multiband receiver to detect many standard signals simultaneously [1]. Nevertheless, there are many obstacles in pursuing the DCR design, including the icker noise, dc offset, and second-order . Those issues become more troubleintermodulation some when implementing the DCR in super-scaled CMOS technology, especially the icker noise problem. Although several publications in the past noted the low icker-noise property of the passive mixer [1][3], none of those has carefully investigated the circuit mechanism and validated its performance in a rigorous manner. Recently, the work in [4]
Manuscript received September 23, 2004; revised December 16, 2004. S. Zhou was with the Electrical Engineering Department, University of California, Los Angeles, CA 90095 USA (e-mail: siningzhou@yahoo.com). M.-C. F. Chang is with the Electrical Engineering Department, University of California, Los Angeles, CA 90095 USA (e-mail: mfchang@ee.ucla.edu). Digital Object Identier 10.1109/JSSC.2005.845981

achieved 70 kHz low icker-noise corner with high linearity by using a low-impedance loaded double-balanced passive mixer. If a single-balanced passive mixer were used, baseband circuit power and area could be reduced signicantly. DC offset cancellation is not given in [4]. Furthermore, the linearity of the low-impedance loaded passive mixer will degrade when the operation frequency increases, because the RF signal swing will be limited at the input of mixer due to smaller conductance of switches, regardless of the impedance at mixer output. In this paper, we rst analyze the passive mixer circuit function to understand the role it plays in icker noise generation and then study the single-balanced structure to overcome the drawbacks of the widely used double-balanced in conversion loss. The resulting mixer shows a positive conversion gain and lower icker-noise corner frequency (45 kHz) than those using active mixers [5][8]. Unique complementary CMOS switches, an LO bias-shifting network that automatically tracks the dc offset, and a dc offset insertion compensation method are also impleand mented to reduce the second-order intermodulation cancel dc offset. II. DCR IMPLEMENTATION ISSUES DC offset is generated due to the self-mixing of LO and LO leakage, which comes from restricted circuit and substrate isolation, as shown in Fig. 1(a). It must be minimized to avoid the sat-

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uration in subsequent circuit stages. The high-pass corner needs to be low (e.g., 10 kHz) to overtake the complete baseband and, on the other hand, it should be adjusted to a high frequency (e.g., 1 MHz) to constrain the settling time during the automatic gain control process. As shown in Fig. 1(b), the baseband signal below the ickeris overwhelmed by the noise. The noise corner frequency icker noise in CMOS might exceed the white noise up to several megahertz [9]. This of course seriously corrupts the signal bandwidth in various communication systems, such as 0.5 MHz for Bluetooth and 2 MHz for WCDMA. No universal mechanism is postulated for icker noise generation. Measurements show that icker noise is most prominent in surface-transport devices such as the CMOS due to random trapping/detrapping of charge carriers at the oxidesilicon interface [2]. An empirical formula for icker noise in the BSIM3V3.2 model is given as [10], [11] (1) where is the unit capacitance of oxide, is a device-speis the channel cic constant, is the length of the device, and are current and frequency index. Flicker bias current. and noise is proportional to the channel current and inversely proportional to the transistor length. Several approaches have been used in the past to mitigate the icker noise problem: 1) reducing the channel current, thus trading linearity and transconductance with the icker noise; 2) adopting a long channel device in icker-noise-sensitive areas, such as the tail current source and the input transistors, which, however, degrades the transconductance and slows the circuit operation; and 3) using PMOS in[2], which leads to the simstead of NMOS for its smaller ilar problems in 2). All of these approaches are useless in the RF mixer design, where both low parasitic and high transconductance are crucial to the circuit performance. of the desired baseband signal, as shown in Fig. 1(c), The is situated right inside of the band. Or, even worse, the , from much stronger interferers in adjacent channels, drops into can be reduced if the mixer is the baseband as well. The matched in the design and layout, in terms of, e.g., the switch dimensions, biasing, and parasitic capacitance. However, it is not sufcient because the balance of the switch operation points is spoiled with the single-balanced structure and/or the presence , it is necesof dc offset. Therefore, in order to achieve low sary to maintain a balanced environment for the mixer dynamic operation. III. SINGLE-BALANCED PASSIVE MIXER The RF mixer, which is the rst stage operating at the baseband, is the dominant contributor to icker noise. Even though the icker noise of an active RF mixer can be mitigated by decreasing the LO frequency and increasing the LO power [12], there is usually no freedom to do so. Our solution involves adopting a passive mixer to remove icker noise during the frequency transfer, because there is no dc biasing current involved. In reality, however, when a dc offset is present, a small amount of induced dc current could still exist in the

Fig. 2. (a) Simplied schematic of a typical single-balanced active mixer. (b) Simplied schematic of a single-balanced passive mixer.

passive mixer. Nevertheless, compared with the bias current in active mixers, the dc offset induced current is easily two to three orders lower, because the impedance in the induced current path is much higher. Also, this path only exists during the transients of LO switching when both of the switches are partially on or off. RF current through passive mixer switches has no effect on icker noise as it is far away from the . Once the signal is down-converted to baseband, the three approaches for low icker-noise design mentioned in Section II are readily available. Therefore, the icker noise of a passive-mixer DCR is determined mainly by the baseband blocks. A. Conversion Gain of Single-Balanced Passive Mixer Fig. 2(a) shows a single-balanced Gilbert cell active mixer. by a bias, After replacing M3 by an ac coupling cap, by loading capacitors, , and adding two biasing resistors, , the active mixer becomes a passive mixer, as shown in Fig. 2(b). The drawback of double-balanced passive mixer is the negative conversion gain, which prevents the passive mixer from many applications. The gain of LNA is determined by the ratio of transition frequency and operation frequency and the ratio of loading and degeneration impedance [13]. Apparently, it is constrained by the physical processing limitation. However, for the purpose of low noise, as long as the linearity requirement allows, the front-end needs a gain that is as high as possible. Otherwise, the following back-end circuits, such as an active RC LPF, need to be very low-noise at the cost of area and power. For example, assume that there are an active mixer front-end with a 30 dB gain and a double-balanced passive mixer front-end with a 24 dB gain. The high-gain LPF dominates the baseband noise performance. Assuming that the noise current is negligible at the high-impedance baseband input, therefore the noise is only represented by a series noise voltage. For a given 5 dB NF requirement for the whole DCR, where 4 dB is contributed by the front-end, the equivalent input noise voltage requirement for for a double-balanced the LPF is calculated to be 12.8 nV/ for an active mixer passive mixer DCR versus 25.5 nV/ DCR, according to Friis formula [14]. It can be interpreted as a difference in area of roughly two times between the LPF capacitance and a difference in power and area of four times between the input stages of the LPF opamp if the noise contribution from resistor and opamp are equal. It is interesting to note that the single-balanced passive mixer is able to achieve positive voltage conversion gain instead of loss. It is 6 dB higher

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than that of a double-balanced mixer. Therefore, in the above example, a single-balanced passive mixer DCR is able to employ a back-end circuit with power and area comparable to that of an active mixer DCR. In the meantime, the icker noise is still low. 1) Switch Conductance: The traditional square law is not accurate in submicrometer devices. According to the can be BSIM3V3.2 model, the triode region drain current expressed as
Fig. 3. (a) Switch conductance. (b) Small-signal equivalent circuit for the single-balanced passive mixer.

(2) is the mobility of charge carriers, is the width, where corresponds to the saturated electrical eld, is the threshold represents the bulk charge effect. Shown in voltage, and , operFig. 3(a), (i), the switch time-variant conductance ating in the triode region with zero , can therefore be derived as

(3) is the LO magnitude and is the dc bias for where LO, here assuming that the RF signal is a small signal. When the can be treated as square LO magnitude is adequate, the wave, as shown in Fig. 3(a), (ii). The sufciency of the LO magnitude is determined by the ratio of the average half-cycle switch on and off conductance, which indicates how much current signal is lost during switching. For example, a ratio of 100 gives less than 0.1 dB conversion gain error. A LO with a 125 mV magnitude in single-ended will provide such a ratio when m m. It can be driving a differential pair sizing at translated to 7 dBm in a 50 system. However, to allow reasonable swing at the input of passive mixers for linearity concerns, LO power needs to be higher. The LO magnitude and bias , which effect are represented by the equivalent turn-on time as is determined by the integral of

Fig. 4. (a) Two equivalent circuits with opposite LO and v . (b) Another pair of equivalent circuits, outputs of v are shorted in the right side circuit. (c) Single-balanced passive mixer achieves the same differential output as double-balanced but with half input.

2) Derivation of Conversion Gain: A single-balanced passive mixer small-signal equivalent circuit is shown in Fig. 3(b), is out of phase with , ex(i). According to (4), the cept for the dc term. Since the dc term does not affect frequency conversion, the two half circuits are identical and the conversion gain of a single-balanced mixer with differential output doubles its half circuit conversion gain, as shown in Fig. 3(b) (ii). The in a series RC network, excited by capacitor voltage , can be described by the differential equation on [3] as (5)

Decompose

into a Fourier series

where

Similarly,

on

can be obtained as

(4) and (iii). is the LO period. The fundamental tone is shown in Fig. 3(a),

where

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Fig. 5.

Equivalent circuit for single-balanced passive mixer noise calculation.

The passive mixer can be viewed as a series combination of , and a singlea frequency converter, . With pole RC low-pass lter with the fundamental tone in mixing with , the conversion gain is then achieved as

(7) does not relate to the Note that the loading capacitance is wider than conversion gain, given the assumption that , the conthe interested baseband frequency. When . version gain is positive, e.g., gain is 2.1 dB with Here, the conversion gain is dened in voltage domain, not in power domain. It does not violate the physical rule of power conservation. B. Comparison Between Single- and Double-Balanced Passive Mixers Similarly, double-balanced conversion gain is (8) Compared with (7), double-balanced conversion gain is 6 dB lower than that of the single-balanced conversion gain. Fig. 4(a) shows two equivalent circuits with opposite LO control and correspondingly opposite , as discussed above. Since they both have the same , their output can be shorted directly in the voltage domain, which results in another pair of equivalent circuits, as shown in Fig. 4(b). Extending both outputs to differential format, single- and double-balanced passive mixers are formed in Fig. 4(c). With identical differential outputs, the single-balanced mixer requires only half of the input signal that the double-balanced mixer needs. This can be understood in another way. For the single-balanced mixer, because of the presis held during the switch-off time, while, for ence of the double-balanced mixer, the outputs always face a turn-on switch. Because voltage signals cannot be summed up, the outputs are still the same as that of single-balanced mixer. However, the differential input is twice of that of the single-balanced. This mechanism differs from active mixers, which carry current
Fig. 6. Simulated NF and conversion gain of single-balanced passive mixer with respect to the opening ratio.

signal and achieve the same gain regardless of whether they are single- or double-balanced. C. Noise of Single-Balanced Passive Mixer The thermal noise needs to be considered in the passive mixer. Because a mixer is a periodically time-varying system, all LO harmonics can dump the associated RF noise to the output. Assuming that the RF thermal noise source is white in the harmonic bands before the mixer, the noise power is proportional to the combined strength of LO harmonics. The noise voltage of switch resistance is inversely proportional to . Fig. 5 shows the equivalent circuit used in noise calculation. The passive mixer NF can be expressed as

(9) Fig. 6 shows that the NF and conversion gain of a single, assuming balanced passive mixer vary with respect to and as a typical case for RF systems. is much less than 0.3, the noise gure is high, corWith responding to the fact of rich LO harmonics and low average switch conductance. The conversion gain reaches its maximum, on the other hand, since the conversion gain relies only on the fundamental LO tone. It is large when the switch opening time is short. The high switch turn-on resistance does not degrade the . When is gain, as long as the IF frequency is within higher than 0.4, the conversion gain drops and the NF increases due to less mixing function. An optimum opening ratio exists between 0.3 and 0.4.

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Fig. 8. Schematic of a single-balanced passive mixer with complementary switches.

Fig. 7. (a) NMOS switch conductance modulated by RF signal. (b) PMOS switch conductance modulated by RF signal with opposite polarity. (c) Complementary switch conductance immune from RF signal.

D. Even-Order Intermodulation Reduced by Complementary Switches There are three factors governing the in mixers: 1) leaking into output; and self mixing; 2) transconductor 3) switching pair nonlinearity and mismatch [15]. For the single-balanced passive mixer, 2) is out of concern without even having a transconductor, and 3) is associated with the fundamental limit of semiconductor processing. Nevertheless, 1) can be improved with circuit techniques. Revise the switch-on as a large signal, will yield conductance of (3), treating

cancellation circuit. The large series capacitor leads to the poor on-chip integration capability. To save the area, Fig. 9(b) illustrates an approach to convert the series C (MIM cap) into a shunt C (MOS cap) with a negative feedback to tilt the mixer load current [16]. Passive mixers do not have the current summation property at the output. Fig. 9(c) shows another approach for the TDMA system specically. With the accurate timing, the circuit cancels dc offset during the idle time and opens when the signal is coming [17]. However, for the system requiring continuous receiving, this approach fails. Shown in Fig. 9(d), the fourth approach is to utilize a baseband processor to sense the dc offset and to control the current to cancel the dc offset digitally. Obviously, this scheme has the problem of latency because of the digital processing and fails to track dynamic dc offset [18], [19]. A. Insertion-Compensated DC-Offset Cancellation A special mechanism for passive mixers, insertion-compensated dc-offset cancellation, is proposed in Fig. 10. Two sets of differential pairs, M1,2 and M3,4, are placed next to with are located in between opposite control. Identical resistors , the differential pair. If there is any dc offset appearing at then the negative feedback system, consisting of an opamp and a rst-order RC LPF, will differentiate the M1 and M2 currents and the M3 and M4 currents but with the opposite directions. Therefore, the same amount of dc offset with opposite polarity is built up on , and the dc offset is cancelled at relative to the BBout. Note that it is improper to try to annul the dc offset right at the output of the passive mixer. The deciency originates from the fact that the passive mixer acts like a voltage source to generate dc offset as long as there is an LO leakage at the input. The dc offset in voltage mode cannot be removed, unless there is a sufciently large inductor at the loading to null the dc and pass the baseband, which is not feasible. It is even harmful to establish an opposite dc to inject differential current to offset as the scheme in Fig. 9(b) for the active mixer. Due to , a considerable static current could the high resistance of be pushed into the switches during the LO switching transients, thus resulting in higher icker noise. To insertion-compensated dc-offset cancellation, since it only adds an opposite dc-offset voltage after the mixer output, there is no need to worry about the dc current owing through the switches. and ow into their As shown in Fig. 10, identical , yielding the same bias for the switches. is a respective long-channel device and biased by the source follower, M5 and . As M5 tracks the output of the opamp, is always biased

(10) and hence the conductance would Fig. 7(a) illustrates how , change with the RF signal. To remove the dependency on a complementary switches topology is applied to the mixer, as shown in Fig. 8. Shown in Fig. 7(b), PMOS conductance can be expressed as

(11) , and are corresponding parameters for where becomes PMOS. The sum of both conductance (12) which is irrelevant to the RF signal, given . However, because it is very difcult to maintain the equivalence and dynamically, the could still be generof ated during large-signal transients. Therefore, it is very important to keep the optimum biases of the PMOS and NMOS to maintain their complementarities during the LO swing. IV. DC-OFFSET CANCELLATION AND DC-OFFSET TRACKING LEVEL-SHIFTED LO BIAS There are several dc-offset cancellation schemes established for certain applications. Fig. 9(a) shows a capacitive coupling

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Fig. 9. Typical dc-offset cancellation schemes. (a) High-pass lter with extreme large R or C. (b) Negative feedback current subtraction for active mixers. (c) Switch capacitor in a TDMA system. (d) Digital-domain sensing and cancellation.

same potential as its drain because the passive mixer is nonuniobtains lateral. When it proceeds to time T2, the source of a potential lower than that in T1 by an amount of the dc offset and appears as a as well. Therefore, the source of modulated signal, with a period same as LO and with the amand are not balanced plitude half of the dc offset. any more. With the help of the PMOS switch, the imbalance and , is only reof the complementary switch, duced to a certain level, because the PMOS/NMOS switch bias is dragged away from the optimum point by the dc-offset modought to rise. ulation at their common sources. Therefore, C. DC-Offset-Tracking Level-Shifted LO Biasing
Fig. 10. Insertion-compensated dc-offset cancellation for passive mixers.

properly during the signal swing and carries no dc current. The resistance can be expressed as

Fig. 11(a) shows the symbolic model for dc-offset cancellation. The transfer function is derived as (13) where is the gain of opamp and represents the transconductance of the differential pair. Fig. 11(b) plots the frequency response. Corresponding to the dc value of the transfer function, . the dc-offset rejection is determined by the loop gain , is adThe 3 dB cutoff frequency, by tuning , without changing the rejustable through jection ratio. B. Constant LO Bias As shown in Fig. 12, large resistors can pass dc to the is approximately gates of the switch. The voltage of two thresholds higher than that of . The problem of the constant LO bias is shown in Fig. 13(a). Due to the dc offset, and deviates in voltage. When is the drain of is off in time T1, the source of obtains the on and

A special scheme, dc-offset-tracking level-shifted LO biasing, is proposed to solve the dc-offset modulation issue. and Illustrated in Fig. 13(b), when the LO biases, , are shifted by the same amount of dc offset, control signals of the NMOS switch become balanced. The same methodology applies to the PMOS switch. Therefore, the complementary switches maintain the optimum bias during by the LO signal swing, thus signicantly reducing the the dc-offset modulation. As shown in Fig. 14, from the mixer output, through a source follower, M1, the dc C offset is picked up and level-shifted to the desired LO dc level. Similar to , together with that in Fig. 10, a long-channel device, , serves as the IF signal attenuator. is the capacitor, designed signicantly large to prevent the active device icker noise from contributing to the mixer noise, because icker and are not coherent in noises from nodes the new bias. However, this is not an issue to the constant LO bias, where the icker noise is applied to both complementary switches and becomes a common mode. V. EXPERIMENTAL RESULTS To verify the concepts, two DCRs are implemented in the 0.18 m 1P6M mixed-mode CMOS technology, working at the 5.155.35 GHz UNII bands. As shown in Fig. 15(a), one DCR has single-balanced passive mixers with complementary m m, M6, m m) and switches (M5,

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Fig. 11.

(a) Symbolic model for insertion-compensated dc-offset cancellation. (b) Corresponding transfer function.

Fig. 12.

Schematic of constant LO biasing.

Fig. 14.

Schematic of dc-offset-tracking level-shifted LO bias.

Fig. 13. (a) Constant LO bias: dc-offset modulation at the switch common source distorts the switch control signals. (b) DC-offset-tracking level-shifted LO bias: switch control signals become balanced.

dc-offset-tracking level-shifted LO bias. A common-source m m) is used to interface the mixer buffer (M3, in order not to distort LNA performance because of the mixer resistive input. The other DCR, shown in Fig. 15(b), m m) has double-balanced passive mixer (M7, and constant LO bias. A single-to-differential buffer (M4, m m) is adopted to interface with the mixer. Both buffers have identical gain because the bias current and the input resistance of passive mixers are kept the same. However, because the parasitic at the common source of single-to-differential buffer causes certain loss, it has 0.7 dB lower gain in simulations than the common-source buffer. Both DCRs have the same LNA, insertion-compensated dc-offset cancellation, m m) and rst-order LPF. The cascode device (M2,

of LNA is half of the main gate (M1, m m) to save parasitic capacitance. Fig. 16 shows the chip microphotograph. The DCR front-end gain is measured as shown in Fig. 17. From 4.7 to 5.5 GHz, the single-balanced mixer DCR has 6.57.3 dB higher gain than double-balanced DCR. This proves the 6 dB gain advantage of the single-balanced over the double-balanced. The extra 0.51.3 dB difference comes from the loss of single-to-differential buffer. These measurements match well with the simulated 30 dB gain at peaking. The LNA and buffer provide 27 dB and the single-balanced passive mixer provides the additional positive 3 dB. LPF is set at 0 dB gain. The following measurements are based on the single-balanced DCR. The spot noise gure is shown in Fig. 18. The integrated NF is 5.3 dB over the baseband. The icker noise corner is found to be 45 kHz, less those adopting active mixers [5][8], which had a icker noise corner all equal or above 170 kHz. Their integrated NFs are similar to this work. from the LNA and buffer are removed by ac coupling. performance. PMOS switch and The mixer dominates the dc-offset-tracking level-shifted LO biasing can be disabled to compare the effects. The results are shown in Fig. 19. The of conventional single-balanced mixer is measured as 18 dBm. It is improved to 39 dBm with the complementary switches and dc-offset-tracking level-shifted LO biasing. The two-tone measurements are compared in Fig. 20 at the output of

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Fig. 15. (a) Schematic of single-balanced passive mixer DCR with complementary switch and dc-offset-tracking level-shifted LO biasing. (b) Schematic of the double-balanced passive mixer DCR.

Fig. 18. Flicker-noise corner measurement and comparison with active mixer references. Fig. 16. Die microphotograph of two DCRs.

and dBm, respectively. To mimic the integrated system, LO driving is limited to 0 dBm to save current consumption. with a decibel-by-decibel High LO power improves relationship [15]. The performance is summarized in Table I. VI. CONCLUSION Analysis of the single-balanced passive mixer is elaborated in terms of icker noise, conversion gain, dc-offset cancel. Passive mixers are used in the DCR for the lation, and unique property of negligible icker noise. The single-balanced passive mixer has 6 dB higher conversion gain than that of the double-balanced mixer, which saves much power and area in the baseband circuit because of the relaxed noise requirement. Containing an opamp, LPFs, gm cells, and resistors, insertion-compensated dc-offset cancellation is proposed for

Fig. 17. Conversion gain measurement comparison of DCRs with single-balanced and double-balanced passive mixers.

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TABLE I SUMMARY OF THE SINGLE-BALANCED PASSIVE MIXER DCR PERFORMANCE

Fig. 19. IIP improvement of complementary switch passive mixer with dc-offset-tracking level-shifted LO bias over NMOS switch with constant LO bias.

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[1] T. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 1998. [2] B. Razavi, Design of Analog CMOS Integrated Circuits. Boston, MA: McGraw-Hill, 1999, pp. 362363. [3] A. Shahari, D. Sharffer, and T. Lee, A 12-mW wide dynamic range CMOS front-end for a portable GPS receiver, IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 20612070, Dec. 1997. [4] E. Sacchi, I. Bietti, S. Erba, L. Tee, P. Vilmercati, and R. Castello, A 15 mW, 70 KHz 1=f corner direct conversion CMOS receiver, in Proc. IEEE Custom Integrated Circuits Conf., 2003, pp. 459462. [5] D. Manstretta, R. Castello, F. Gatta, P. Rossi, and F. Svelto, A 0.18 m CMOS direct-conversion receiver front-end for UMTS, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2002, pp. 240241. [6] P. Zhang, T. Nguyen, C. Lan, D. Gambetta, C. Soorapanth, B. Cheng, S. Hart, I. Sever, T. Bourdi, A. Tham, and B. Razavi, A direct conversion CMOS transceiver for IEEE 802.11a WLANs, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2003, pp. 354355. [7] A. R. Behzad, Z. M. Shi, S. B. Anand, L. Lin, K. A. Carter, M. S. Kappes, T.-H. Lin, T. Nyuyen, D. Yuan, S. Wu, Y. C. Wong, V. Fong, and A. Rofougaran, A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE 802.11a wireless LAN standard, IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 22092220, Dec. 2003. [8] J. Rogin, I. Kouchev, and Q. Huang, A 1.5 V 45 mW direct conversion WCDMA receiver IC in 0.13 m CMOS, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2003, pp. 268269. [9] T. Melly, A. S. Porret, C. C. Enz, and M. Kayal, A 1.3-V low-power 430-MHz front-end using a standard digital CMOS process, in Proc. IEEE Custom Integrated Circuit Conf., Santa Clara, CA, May 1998, pp. 503506. [10] J. Tsividis, Operation and Modeling of the MOS Transistors, 2nd ed. Boston, MA: McGraw-Hill, 1999. [11] W. Liu et al., BSIM3v3.2 MOSFET model users manual, The Regents of the University of California, 1998. [12] H. Darabi and A. A. Abidi, Noise in RF-CMOS mixers: A simple physical model, IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 1525, Jan. 2000. [13] D. Shaeffer and T. Lee, A 1.5-V, 1.5-GHz CMOS low noise amplier, IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745759, May 1997. [14] H. Friis, Noise gure of radio receiver, in Proc. Inst. Radio Eng., vol. 32, Jul. 1944, pp. 419422. [15] D. Manstretta, M. Brandolini, and F. Svelto, Second-order intermodulation mechanisms in CMOS downconverters, IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 394406, Mar. 2003. [16] B. Razavi, A 5.2-GHz CMOS receiver with 62-dB image rejection, IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 810815, May 2001. , RF Microelectronics. Upper Saddle River, NJ: Prentice-Hall, [17] 2000.

(a)

(b) Fig. 20. (a) IM of NMOS switches and constant LO bias. (b) IM reduced by complementary switches and dc-offset-tracking level-shifted LO bias.

passive mixers designed to operate in the voltage domain. To reduce the , complementary switches and dc-offset-tracking level-shifted LO bias are proposed. All of those concepts are validated through two DCRs realized in 0.18 m CMOS. Flicker noise corner is 45 kHz. A single-balanced passive mixer DCR has 6.57.3 dB higher gain than the double-balanced. With complementary switches and dc-offset-tracking is improved 21 dB over the convenlevel-shifted LO bias, tional single-balanced passive mixer.

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[18] D. Su, M. Zargari, P. Yue, S. Rabii, D. Weber, B. Kaczynski, S. Mehta, K. Singh, S. Mendis, and B. Wooley, A 5 GHz CMOS receiver for IEEE 802.11a wireless LAN, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2002, pp. 9293. [19] J. Crols and M. Steyaert, A 1.5 GHz highly linear CMOS downconversion mixer, IEEE J. Solid-State Circuits, vol. 30, no. 7, pp. 736742, Jul. 1995.

Sining Zhou (S00M02) received the B.S. and M.S. degrees from the University of Science and Technology of China, Hefei, China, in 1994 and 1997, respectively, and the Ph.D. degree from University of California, Los Angeles (UCLA), in 2002, all in electrical engineering. In 1998, he joined the High Speed Electronics Laboratory, UCLA, where he performed research on multi-I/O, recongurable RF/wireless interconnects for inter- and intra-ULSI communications. In 2000, he interned with RF Micro Devices, San Jose, CA, and worked on IEEE 802.11a wireless LAN receiver front-ends. In 2001, he was with Silicon Storage Technology (formerly G-plus), Santa Monica, CA, where he worked on the UNII-band wireless speaker system. Since 2002, he has been with Orion Microelectronics (Realtek Group), Irvine, CA, where he is a Product Design Manager, working on transceiver chip design for IEEE 802.11a/b/g wireless LAN and TV tuner systems. The wireless LAN transceiver and baseband chipset won Best Choice of Computex_Taipei 2004 award. He holds two issued and one pending U.S. patents. His research interests include CMOS RF integrated circuit design and analog/mixed signal circuit design.

Mau-Chung Frank Chang (M85F96) received the B.S. degree in physics from National Taiwan University, Taipei, Taiwan, R.O.C., in 1972, the M.S. degree in material science from National Tsing-Hua University, Hsinchu, Taiwan, in 1974, and the Ph.D. degree in electrical engineering from National Chiao-Tung University, Taiwan, in 1979. He is currently a full Professor with the Electrical Engineering Department and Director of the High Speed Electronics Laboratory, University of California, Los Angeles (UCLA). Before joining UCLA, he was the Assistant Director and Department Manager of the High Speed Electronics Laboratory, Rockwell Science Center (19831997), Thousand Oaks, CA. In this tenure, he successfully developed and transferred the AlGaAs/GaAs HBT technology form the research laboratory to the production line (Conexant Systems). The HBT production has now grown into a multibillion-dollar business worldwide. During his career, his research work has been mostly in the development of high-speed semiconductor devices and integrated circuits for mixed signal communication and sensor system applications. He was the principal investigator at Rockwell to lead the US-DARPA ADC and DAC development for direct-conversion transceiver (DCT) and digital radar receivers (DRR) systems. He was the inventor of the multi-I/O, recongurable RF/wireless interconnects based on FDMA and CDMA multiple access algorithms for inter- and intra-ULSI communications. He also pioneered in demonstrating the rst cantilever-type RF MEMS switch for microwave/millimeter-wave transmission applications. Recently, he has led the rst demonstration of a dual-mode (CDMA/AMPS) power amplier based on the Si/SiGe HBT technology for wireless handset transmitter applications; the rst K-band (2427 GHz) RFIC in CMOS and the rst CMOS ADC with 1 GHz instantaneous bandwidth. He has authored or coauthored over 200 technical papers, 10 book chapters, edited one book, and holds 18 U.S. patents. In 1997, he has founded a communication chip-design company (G-Plus, Westwood, CA, recently acquired by SST) and served as the Board Director for two GaAs manufacturing companies, including GCS (Torrance, CA) and GCT (Hsinchu, Taiwan). Both GCS and GCT are regarded as world-class pure-player foundry houses for microwave and millimeter-wave integrated circuits (MMIC) production. Dr. Chang was named an IEEE Fellow in 1996 for his pioneering contributions in ultra-high-speed HBT integrated circuit development. He was the recipient of Rockwells Leonardo Da Vinci (Engineer of the Year) Award in 1992, National Chiao-Tung Universitys Distinguished Alumni Award in 1997, and National Tsing-Hua Universitys Distinguished Alumni Award in 2002. He is a co-editor of the IEEE TRANSACTIONS ON ELECTRON DEVICES and was a guest editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS in 1991 and 1992, respectively, and the Journal of High-Speed Electronics and Systems in 1994.