Least Mean Square (LMS) Adaptive Line Enhancer (ALE) Design in VHDL

3 December 2012

Features
The Adaptive Line Enhancer (ALE) is an effective learning filter for reducing Gaussian noise with a large SNR. The filter adjusts the filter weights to pass the desired input signal while reducing the noise portion of the signal with little to no filter roll-off up to the Nyquist rate (Fs/2). An adaptive filter can alter its own frequency response in order to improve the filters performance on-the-fly. The following design topics will be covered: ALE filter architecture design fundamentals Filter stability dependant on learning coefficient, mu Filter scaling for more efficient implementation Custom VHDL component design and instantiation to include an 18-bit CODEC controller and ALE filter Filter characteristics and validation

Introduction
This reference design utilizes a Xilinx Spartan 6 development board and a National (by Texas Instruments) LM4550 audio CODEC. The design was developed in Xilinx ISE ver13.1. This design employs an audio CODEC, but it is not required. The Xilinx Spartan 6 FPGA is a good choice for DSP logic circuit design due to the integrated DSP48A1 blocks. The integrated DSP blocks allow for parallel math circuits resulting in a filter capable of ultra fast data processing. The ALE can be used with any FPGA given enough hardware multipliers, taking into account the word length of the filter. This filter implementation used 48 of the 58 Spartan 6 xc6slx45 DSP48A1 blocks; an FPGA with more DSP blocks can support more ALE taps yielding greater performance.

Background
It is not necessary that the user of this module have complete understanding of ALE filter design, but it can help in trouble shooting a filter if one understands the basic design principles. This background section covers the fundamentals of the ALE filter and VHDL module design itself. The design uses an internal Gaussian noise generator where the left channel routes the signal before the filter and after the noise, the right channel is the path after the filter where much of the noise is reduced. The effects of the filter on the noise + signal and reduced noise + signal can be seen in Figures 1 and 2 below.

Figure 1 -- Noise + Signal (Blue) and Reduced Noise + Signal (Yellow)

Figure 2 -- Increased Noise + Signal (Blue) and Reduced Noise + Signal (Yellow) The ALE was also tested with an external noise source from an arbitrary waveform generator. This can be seen in Figure 3 below.

Figure 3 -- External Noise + Signal (yellow) and Reduced Noise + Signal (blue)

The adaptive filter excel in filtering signals where one might experience changing conditions, spectral overlap between wide-band noise and the narrow-band signal, or in applications where the noise source is unknown or contentiously changing. The filter changes the weights to reduce noise and maximize the correlated signal output. The ALEs frequency response was plotted in Figure 4 below. Notice how there is not any significant roll-off all the way up through the Nyquist frequency at 24 KHz.

Figure 4 -- ALE Frequency Response up to Nyquist The input signal ( B(k) + N(k) ) is delayed one sample to de-correlate the Broadband noise signal from itself giving us ( Bu(k) + Nc(k) ). This happens because the noise is random and a small change in phase de-correlates the signal. Notice that the narrow band signal Nc(k) stays correlated with N(k) because it is not random but largely periodic and contentious. The signal flow diagram can be seen in Figure 5 below.

Figure 5 -- ALE Signal Flow Diagram

The ALE filter works by initializing the filter weights to arbitrary values and adjusting them each sample period. This is done by computing the filter output N-hat-k, using equation 1 below. This narrow band signal (N-hat-k) is used to compute the error estimate (ek), see equation 2 below. The ALE implements a least-squares-error cost function to find optimal filter weights to estimate the signal output. Instead of using the expected values from the gradient vector in the parabolic mean-square-error cost function, the current input FIFO values (the instantaneous gradient) are multiplied by a learning coefficient (mu). This adjusts the weights by using a least-mean-square approximation; a step in the greatest decent is taken using equation 3 below. The decent moves down a parabolic structure in n-dimensions, the dimension is determined by the order of the filter. When the gradient is zero the least-mean-squared error has been maximally reduced. To avoid overstepping, we take small steps determined by the learning coefficient mu. The mu value is chosen by using equation 4 below. This mu value governs how much the filter values change in a given sample period. It is handy to choose a value for mu which allows one to simply barrel shift the product of the error estimate and FIFO values, but also important to keep mu small enough to avoid divergence from the error surface of the n-dimensional parabola. A simplified representation of the Mean-Squared-Error surface with two weights can be seen below in Figure 6.

Equation 1

Equation 2

Equation 3

Equation 4

Figure 6 Simplified Representation of Mean-Squared-Error Surface

Application
Building the Circuit
The ALE filter module uses the following processes: 16 deep by 18 bit shift register for shifting in samples State update for timing and flag control 16 bit linear feedback shift register for dithering during truncation Timer dependent process for control of data path flags 16 term parallel multiplier process Process for truncation and dithering of output terms Large adder tree as part of convolution Feedback subtraction process Error estimation block Feedback truncation and dithering process Filter tap adjustment process 32-bit to 18-bit truncation block for output to DAC

The ALE architecture can be seen in Figure 7 below.

Figure 7 -- Adaptive Line Enhancer Filter Architecture Instantiating the ALE Filter Module The ALE filter is easily instantiated by including the ALE.vhd file in a project and either port mapping the top level ports in Xilinx ISE or using a schematic file to connect to the ports. After creating a schematic symbol within the processes tab, the ports can be connected by adding wires within the schematic editor. The top level schematic can be seen in Figure 8 below. When verifying the module in hardware, the noise_gen.vhd module must be manually reset on the board to seed the pseudo-random number generator.

Figure 8 -- Xilinx ISE Schematic Top Level This application was run at 100MHz with plenty of slack for running at faster speeds. Hardware Test and Verification

The module was thoroughly tested through the use of Xilinxs simulation software, ISim. A basic timer-driven state machine controls enable flags for synchronizing the math operations, truncating and dithering intermediate operations, and latching in the output each sample period. Each sample period advances the delay lines and starts the flag state machine. The module was also verified in hardware as seen above in Figures 1 through 3.

Design Software, and Hardware

This reference design utilizes a Xilinx Spartan 6 development board and a National (by Texas Instruments) LM4550 audio CODEC. The design was developed in Xilinx ISE ver13.1. The Audio CODEC in this design is not required. The design can be scaled to many non-audio applications, not limited to a 48 KHz sampling rate.

Conclusion
The adaptive filter excels in filtering signals where one might experience changing conditions, spectral overlap between wide-band noise and the narrow-band signal, or in applications where the noise source is unknown or contentiously changing. This design was targeted and tested in audio applications, although the design can be scaled down for a faster filter with less resolution. The fundamentals of ALE VHDL modules filter design have also been covered.

Additional Information
The AC97 Codec driver, NbitSatAdder, and noise_gen modules are covered in further detail on the eeWiki Logic page. Further DSP topics and filter design information can be found in the book: Digital Signal Processing, A Practical Approach, By Emmanuel C. Ifeachor and Barrie W. Jervis.

Appendix:
The complete, Adaptive Line Enhancer Design in VHDL and VHDL files can be downloaded from the eewiki.net website under the Programmable Logic section.

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