A Fully Depleted Lean-channel Transistor(DELTA) -- A novel ve r tical ultra thi n Sal MOSFET --

Digh Hisamoto,

Toru Kaga,

Yoshifumi Kawamo to an d Eiji Takeda Hitachi Ltd.

Central Research Laboratory. Kokubunji. Tokyo

185. JAPAN SOl

that is formed utilizing se lective process

A fully depl eted lean channel transistor (DELTA) having a new "gate -structure and vertical ultra thin SOl structure with selective field oxide is reported. In the deep submicron region, se lective oxidation is usef u l for achieving SOl is olation. It provides a high qU'tlity crystal and a Si-SiO, interface as goo d as those of conventional bulk single. crystal devices. Using experiments and simulation, it was shown that the new gate structure of DELTA has

ABSTRACT:

crystal

oxidation.

The

DELTA

s elective

oxidation

is illustrated in Figs.l ohm (100) wafers are

(a)-(c). used.

Boron doped 10a 25-nm

On

thick
and us ing over a

thermal oxide pad. by CVD. The

200-nm of nitr ide is. deposi ted thermal are ion then etching oxide pad,

ni tride.

silicon

subs trate reactive mask. Next.

e t ched (RIE) is

channel controllabi I ity and its effective vertica l ultra thin 0. Z /.tm) SOl structure provides superior device charact eristics. e. g. the reduction of short channel effects, minimized subthreshold swing. and high t ran sconductance.

anisotropic photores ist (Fig. 1 (a thermal .

Thus, a and

Si

island is

formed by is

lO -nm a

layer

fo rmed layer

ox idat ion by

100-nm

nitride RIE.

deposited

CVD.

Then,

using

nitr i de island. of the .

1.

introduction
Three-dimensional MOSFET are structures. impor t an t such for as the MOSFETs [1)- [3). of superior

s pacers are formed at the sides of the Si Next. the bottom of are etched the the spacers and part

vertical

substrate By

away

by H F/IINO, at 1100 in

(Fig.l (b

achievement

device can

performance. be 3-D in a fata l

oxi dizing is

s ubs t rate as

an

SOl The the

How ever,
because submicron

f loating-substrate

structure rest of same as

formed. device for

shown

Fig. 1 (c).

problem for conventional the vertical

integrated

devices. the deep

the

fabrication a

processes are gate approach

s tructures

those

conventional this

se lfis A is

region

impede to to

substrate eliminate attain deep

contac t. floating-

a ligned

n-MOSFET. with that

Thus.
for the final

Consequent ly, substrate device are

methods essential in

consistent cross

conventional DELTA

LOCOS.

sophisticated region

section

of

structure

structures

the

s ubmi c ron

presented in Fig. 2. Cross sectional structures TEM are pictures of shown in both non-SOl (a) and

and more below 0.1 /.tm. In this paper, (DELTA) a fully deplet ed lean-channe l is proposed. device has Using

and SOl
(b). a

Figs. 3

.!rnsistor and

s im u l ator are feat ures. ultra is by

The fact that selective oxidation results in

experiments , DELTA gate

characteristics specia l that

l ot o f defects at the edge of the field oxides the in slippi ng (a). surface (111) can be clearly shows

investigated. One thin that is a new

three

along seen

structure

induces

Fig . 3

Neverthe l ess .

Fig. 3 (b)

SOL
a

effects [4) [5) single

vert ical ly.

Another is formed

that once the ,appear. fo llows. beaks in This It

SOl

struct ure is formed, can be

no defects as

bulk

crystal

SOL
nor that

difference that (a) is

understoo d of the

selective

o xidation.

Therefore

nei ther

seems Figs. 3

the and no

shapes (b)

bi r d ' s

re crystallization r equir ed [6) [7). forme d on a The

technology other is

SlMOX
channel the

is is

are

identica l. in stress .

the so

Consequent ly, As a result, the overall

there

difference

vertica l

surface.

channel

one would expect to be f o rmed during s elective oxidation process. However,

width depends on t.he height of t he Si i sland.

the excess

defects period

in Fig. 3 after this

(a) the

are formed during oxidation for step the of SOl

2. Dcvice Design and Fabrication Process

A unique feature of DELTA

the si ngle the

cooling process.

is

its

bulk

During

period,

34.5.1
CH2637-7J89JOOOO-0833 $1.00 1989 IEEE IEDM 89-833

structure. relieve

the

SiO,

layer

under of

the

Si

can Si

the
has

layou t

channel of

width

and

its

scal ing. DELTA of

the

stress.

instead

allowing

Moreover.

because

ult ra -th i n (Gm). Fig.8.

e ffects.

defects to form.

high transconductance W is shown in

The d ependenc e

the Gm on 3. Device Characteristics The channel ultra DELTA gate effectively both sides controls and the

Gm

is

1. 5

times

highe r than for Gm' (Wg+2Wl)

for Wg=O. 15Mm.

potential thin

from

induces

4. Impact of DELTA on ULSIs

SOl
Fig.

ef f ects

vertically. of c ross with

Simulated are of

DELTA is Isolation isolated pack Ing

excellent is

for

ULSl

applications. DELTA

No is

potential shown in

distributions

section that

area

necessary

because

4.

Compared

vertically. density is

Therefore. As

high shown

dev ice in 'the is

conventional devices. and means flat the potential is a

the potential bend is small is flat. field This and

attainable. a large

distribution surface

illustration possible. DRAM area

below.

storage

area

there

low

electric

b y using For

DELTA as a switching IN) S i n a for 1.6 5-Mm

x

inversion

charge

distribution.

This

results

c ell. with

example.

0. 8 depth

Mrn'

cell

in the following superior device characteristics. even if the substrate is thicker than that of

sheath

type

trench

capacitor.

105.9 fF/bit capacitance is obtained.

WORD

conventional ultra-thin SOl devices[4] [5]. Subthreshold (DELTA) and 10 characteristics Mm for Wg=0.2 both Mm with

(conventi onal) . and identical

Um/

Leff=0.15Mm. profiles. For Wg=10

Tox=8.5nm

impurity and (b). but

PLAIE

are demonstrated in Figs.5 Mm. punch-through Mm. Thus. leakages

(a)

occur.

does not for Wg=0.2 channe l for e ffects.

MID

DELTA reduces short characteristics are prov ided in 5. Conclusion Using vertical

The and

I-V

static Mm

Leff=0.57

Wg=O. 15 there

e xper i ments
ultra-thin

and SOl

simulation. device

novel was

Fig. 6. is

It is clear that all by the

are no humps. characteristics the two of

This are gate the

(DELTA)

because

channel

investigated. (1) In the

Some key results are as follows. deep submicron useful f or offers region. selective an SOl

dominanted field top

the In

balance addi tion. of the

between the
501

effects.

effects its

oxidation is structure

fabricating high-quality

corner

edges

and

pointed (2)

that

single

Qottom are negligible. An imp ortant is a ultra small thin SOl device swing. (3)

crystal Si and Si-SiO,

Interface.

The DELTA gate structure is so effective that a vertical ultra-thin mode can indeed be

characteristic This is because

subthreshold layer

the

depletion

capa citance the

realiz ed. The DELTA structure Still the current uses vertical surface.

that determines the swing strongly depends on substrate swings on thickness. channel Dependences are of

subthreshold in less Fig.7. than A 0.3

direction

is the same as Therefore the with the

width

shown to

that for a conventional device. DELTA layout is

decrease

in substrate thickness

consistent

Mm results in a smaller swing. this new gate for a structure. device

Consequently. with
effects are width of less than

conventional ULSI circuit layout. Thus. DELTA offers both consistency with

ultra-thin a

expected 0.3 Mm.

with

conventional D device. -approach less than

IN)SFETs and good scalability as a 3DF.LTA provides a promising IN)SFET structure of

For Wg=O. 15 Mm.

the swing decreases to 62

As a resul t. for

mY/decade. The the channel width (W) of (Wg) WI DELTA and is consists side the of

the

ultimate

upper

surface (WI) (see

channel Fig. 2).

surface

channels height. the

Si-island Thus.

which depends on the etching depth. current of DELTA is

channel

independent

of

ACKNOWLEDGMENTS The authors wish to thank Dr. Kunihiro Yagi and the other members of the Process Integration Center f or the device fabrication. They also would like to thank Dr. Shin ' i chir o Kimura. Akira Sato. Shoji Shukuri. Ryuichi Izawa. and Dr. Masao Tamura for the supports and helpfu l dis c ussion s .

0.1 ILm

in size.

34.5.2
834-IEDM 89

A.H.

[1]W. F. Richardson. D. M. Bordelon. G. P. Pollack. Shah. S. D. S.Malhi. H. Shichijo. S. K. Banerjee. M. Elahy. R. H. Womack. C-P. Wang. J. Gi 11 ia. H. E. Davis and P. K. Chatterjee. "A TRENCH TRANSISTOR CROSS POINT DRAM CELL." in IEDM Tech. Dig .. Dec. 1985. pp.714-717. [2]K.Hieda. F. Horiguchi. H. Watanabe. K. Sunoueh i.

REFERENCES

for UI tra High Dens i ty LSIs. " in IEDM Tech. Dig .. Dec.1986.pp. 222-225. [4]J. P. Coli nge. "Reduction of Kink Effec t in Thin
vol. ED L - 9. no. 2. pp. 97-99.1 988.

I. Inoue and T. Hamamoto. "NEW EFFECTS OF TRENCH ISOLATED TRANSISTOR USING SIDE-WALL GATES. "in IEDM Tech. Dig .. Dec. 1987. pp.736-739. [3]H.Takahashi. K. Sunouchi. N. ka b e. A. Nita yama. O K. Hieda. F. Horiguehi and F. Masuoka. "High Performance CIDS S urr oun din g Gate T r ans i s tor (SGT)

Film

SOl

MOSFETs. "IEEE

Electron

De vice

Lett ..

Il.llazama. M. Takahashi. [5JM. Yoshi mi. S. Kambay a s hi. T. Wada. K. Kato. and H. Tang o. "Two Dimensional Simulation and Measure ment of High
Performance Film. "IEEE IDSFET's Made Trans. Electro n pp.493-503. 1989.

on a Very Thin SOl D evices. vol. ED-36.

[6]M. Kubota.

T. Tamaki.
SOl

T. Takemoto. "NEW

K. Kawamoto. N. Nomura and CIDS PROCESS WITH SELECTIVE

OXIDATION. "in IEDM Tech. Dig .. Dec.

1986. pp. 814-8 1 6. of [7] S. C.Ar ne y and N. C . MacDonald. "Format i on silicon-an-insulato r st ru ct u res submicron by lateral oxidation of substrate-silicon islands . " J. Vac. Sci. Techno!. B. vol. 6. N o . 1 . pp.341-344. 198ft

(')

( b)

both

Fig.3

(a) non-SOl

Cross-sectional selective
and

TEM

pictures

(b) SOl

structure

of

(e)

made using

oxidation

1 1
Fig. 1 ( a ) process -

( e)

DELTA

se

l e c t i ve

oxidation

O.15 Fig.4 Fig.2 Schematic cross section of Simulated

DELTA

source-drain nodes

across

c h annel

region

potential
(Vd=3V.

distribution middle of Vs=OV. Vg=3V)

in

34.5.3
IEDM 89835

6 10"

10-2
10-6

10" 10-

<t c Cb .... U

1 0-

10 -

10

10 16 1 10"1 1 0-1 1

III '0

10-14

-1

2
Vg (V)
C a)

- 13 10 10 -14 -05 0 Vg (V)

characteri sties as

0.5

1 0-2

Fig. 7 (a) Subthreshold a function of Wg

120

u 0

Vds=O.IV

100

:; E

80
Vl

Cr" / , .&

... . 1 O-14 '--_....J._---"'--_...L._---"'--_.... 0 2 3 4

-1

60 0.1

a-..o.l=061-'"

0-0 L=1.2I'm

Vg (V)
(b)
Fig.5 Subthreshold ch aracteristics for various Vd (a)Wg=O.2 IJ.m, Leff=O.15 IJ.m (b) Wg=10 IJ.m, Leff=O. 15 IJ.m

1.0 Wg (}.1m)

10

Fig. 7 (b) Relationship between subthreshold swings and Wg

500 ,---------,..,

C :;

0.5 0.4 0.3 0.2 0.1

2 Vds (V)

Vg(Y)
3.5

400

3.0
2S 20

tg, 300

200
l00

/ /

J'

//

1.5
to 0.5

.9'

Gnia:(Wg+2WI)

'----'---'---'

Wg
for

(m)

Fig.6 Typical I-V ch aracteristics Leff=O.57 IJ.m and Wg=O. 15 IJ.m

Fig.8 Relationship between transconductance and Wg (Leff1. 0 IJ.m, Vds=3 V)

34.5.4
836-IEDM 89